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| am186 ? cc/ch/cu microcontrollers users manual order #21914b
? 1998 advanced micro devices, inc. all rights reserved. advanced micro devices, inc. ("amd") reserves the right to make changes in its products without notice in order to improve design or performance characteristics. the information in this publication is believed to be accurate at the time of publication, but amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves t he right to make changes at any time, without notice. amd disclaims responsibility for any consequences resulting from the use of the informatio n included in this publication. this publication neither states nor implies any representations or warranties of any kind, including but not limited to, any im plied warranty of merchantability or fitness for a particular purpose. amd products are not authorized for use as critical components in life sup port devices or systems without amds written approval. amd assumes no liability whatsoever for claims associated with the sale or use (includi ng the use of engineering samples) of amd products, except as provided in amds terms and conditions of sale for such products. trademarks amd, the amd logo, and combinations thereof, am186, am188, comm86, e86, slac, smartdma, and codekit are trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies . am186?cc/ch/cu microcontrollers users manual iii if you have questions, were here to help you. the amd customer service network includes u.s. offices, international offices, and a customer training center. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff to answer e86? and comm86? family hardware and software development questions. frequently accessed numbers are listed below. additional contact information is listed on the back of this manual. amds www site lists the latest phone numbers. technical support answers to technical questions are available online, through e-mail, and by telephone. go to amds home page at www.amd.com and follow the service link for the latest amd technical support phone numbers, software, and frequently asked questions. for technical support questions on all e86 and comm86 products, send e-mail to epd.support@amd.com (in the us and canada) or euro.tech@amd.com (in europe and the uk). you can also call the amd corporate applications hotline at: (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline www support for specific information on e86 and comm86 products, access the amd home page at www.amd.com and follow the embedded processors link. these pages provide information on upcoming product releases, overviews of existing products, information on product support and tools, and a list of technical documentation. support tools include online benchmarking tools and codekit? softwaretested source code example applications. many of the technical documents are available online in pdf form. questions, requests, and input concerning amds www pages can be sent via e-mail to webmaster@amd.com . documentation and literature support data books, users manuals, data sheets, application notes, and product cds are free with a simple phone call. internationally, contact your local amd sales office for product literature. to order literature, call: (800) 222-9323 toll-free for u.s. and canada (512) 602-5651 direct dial worldwide (512) 602-7639 fax third-party support amd fusione86 sm partners provide an array of products designed to meet critical time-to-market needs. products and solutions available include emulators, hardware and software debuggers, board-level products, and software development tools, among others. the www site and the e86 family products development tools cd, order# 21058 , describe these solutions. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. iv am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual v table of contents preface introduction xix comm86 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix purpose of this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix intended audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix overview of this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi amd documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii microcontroller-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii chapter 1 architectural overview 1-1 1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 am186cc communications controller . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2.1 am186ch hdlc microcontroller . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.2 am186cu usb microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.3 feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4.1 am186 embedded cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4.2 serial communications support . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4.2.1 universal serial bus. . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4.2.2 hdlc channels and tsas . . . . . . . . . . . . . . . . . . . . 1-7 1.4.2.3 general circuit interface . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4.2.4 smartdma channels . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4.2.5 asynchronous serial ports. . . . . . . . . . . . . . . . . . . . . 1-9 1.4.2.6 synchronous serial port . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.3 system peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.3.1 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.3.2 general-purpose dma channels . . . . . . . . . . . . . . 1-10 1.4.3.3 programmable i/o signals . . . . . . . . . . . . . . . . . . . . 1-10 1.4.3.4 programmable timers . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.4.3.5 hardware watchdog timer . . . . . . . . . . . . . . . . . . . 1-11 1.4.4 memory and peripheral interface . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.4.4.1 system interfaces and clock control. . . . . . . . . . . . 1-11 1.4.4.2 dynamic random access memory support . . . . . . 1-11 1.4.4.3 chip selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.4.5 in-circuit emulator support. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.5 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 chapter 2 configuration basics 2-1 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2.1 processor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2.2 processor status flags register . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.3 peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3 memory organization and address generation. . . . . . . . . . . . . . . . . . . . 2-5 2.4 i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.6 segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 table of contents vi am186?cc/ch/cu microcontrollers users manual 2.7 data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.8 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.8.1 register and immediate operands . . . . . . . . . . . . . . . . . . . . . . 2-9 2.8.2 memory operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 chapter 3 system overview 3-1 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 initialization and reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.6 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.6.2 block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.6.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 3.6.3.1 address and data buses . . . . . . . . . . . . . . . . . . . . . 3-30 3.6.3.2 programmable bus sizing . . . . . . . . . . . . . . . . . . . . 3-30 3.6.3.3 byte write enables. . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.6.3.4 output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.6.3.5 bus mastering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.6.3.6 dram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.7 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.7.1 clock features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.7.2 pll bypass mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.8 hardware-related considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.9 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.10 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 chapter 4 emulator support 4-1 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.1 multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.2 emulator connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.2 emulator-related signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.2.1 a19Ca0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.2.2 ad15Cad0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.2.3 {aden } / bhe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.2.4 ale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.2.5 ardy and srdy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.2.6 bhe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.2.7 bsize8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.2.8 [cas1 Ccas0 ] and [ras1 Cras0 ] . . . . . . . . . . . . . . 4-3 4.3.2.9 clkout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.2.10 lcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.2.11 mcs3 Cmcs0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.2.12 {once } . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.2.13 qs1Cqs0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.2.14 [ras1 Cras0 ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.2.15 rd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.2.16 res . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.2.17 resout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.2.18 s2 Cs0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2.19 s6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2.20 srdy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2.21 ucs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2.22 {ucsx8 } and wlb . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table of contents am186?cc/ch/cu microcontrollers users manual vii 4.3.2.23 whb and wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2.24 wlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2.25 wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.3 hardware-related considerations . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.4 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 chapter 5 chip selects 5-1 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.5.2 selecting memory and i/o space . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5.2.1 ucs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5.2.2 lcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5.2.3 mcs3 Cmcs0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5.2.4 pcs7 Cpcs0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.5.3 selecting dram using the chip selects . . . . . . . . . . . . . . . . . . 5-7 5.5.4 overlapping chip selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.5.5 configuring address and data buses . . . . . . . . . . . . . . . . . . . . 5-9 5.5.5.1 ucs and lcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.5.5.2 non-ucs and non-lcs . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.5.5.3 pcs i/o space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.5.6 programming ready signals and wait states . . . . . . . . . . . . . 5-10 5.5.7 chip select timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.5.8 hardware-related considerations . . . . . . . . . . . . . . . . . . . . . . 5-10 5.5.9 software-related considerations . . . . . . . . . . . . . . . . . . . . . . 5-10 5.5.10 comparison to other devices. . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 chapter 6 dram controller 6-1 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.5.2 dram supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.5.3 dram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.5.4 option to overlap dram with pcs . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.5 dram refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.5.1 dram refresh cycle . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.5.2 dram refresh intervals . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.6 hardware-related considerations . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.7 software-related considerations . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.8 comparison to other devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 chapter 7 interrupts 7-1 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 table of contents viii am186?cc/ch/cu microcontrollers users manual 7.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.1.1 types of interrupt channels . . . . . . . . . . . . . . . . . . . . 7-6 7.5.1.2 using maskable interrupts . . . . . . . . . . . . . . . . . . . . . 7-7 7.5.1.3 using nonmaskable interrupts. . . . . . . . . . . . . . . . . . 7-8 7.5.2 definitions of interrupt terms . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.5.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.5.3.1 requesting the interrupt . . . . . . . . . . . . . . . . . . . . . . 7-9 7.5.3.2 servicing the interrupt . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.5.3.3 acknowledging the interrupt . . . . . . . . . . . . . . . . . . 7-10 7.5.3.4 end-of-interrupt (eoi) . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.5.3.5 returning from the interrupt . . . . . . . . . . . . . . . . . . . 7-10 7.5.4 interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.5.4.1 nonmaskable interrupt and software interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.5.4.2 maskable hardware interrupt priority. . . . . . . . . . . . 7-11 7.5.5 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.5.5.1 maskable interrupt cycle . . . . . . . . . . . . . . . . . . . . . 7-13 7.5.5.2 interrupts in polled mode . . . . . . . . . . . . . . . . . . . . . 7-14 7.5.5.3 considerations for nmi, software interrupts, and traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.5.5.4 maskable interrupt overview . . . . . . . . . . . . . . . . . . 7-14 7.5.5.5 maskable interrupt block diagram . . . . . . . . . . . . . . 7-15 7.5.5.6 pios as interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7.5.5.7 registers used . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7.5.6 nonmaskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7.5.6.1 software interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.5.6.2 divide error exception (interrupt type 00h). . . . . . . 7-19 7.5.6.3 trace interrupt (interrupt type 01h) . . . . . . . . . . . . . 7-19 7.5.6.4 nonmaskable interrupt (interrupt type 02h) . . . . . . 7-19 7.5.6.5 breakpoint interrupt (interrupt type 03h) . . . . . . . . . 7-19 7.5.6.6 int0 detected overflow exception (interrupt type 04h) . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.5.6.7 array bounds exception (interrupt type 05h) . . . . . 7-20 7.5.6.8 unused opcode exception (interrupt type 06h) . . . 7-20 7.5.6.9 esc opcode exception (interrupt type 07h). . . . . . 7-20 7.5.7 software-related considerations . . . . . . . . . . . . . . . . . . . . . . 7-20 7.5.8 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 chapter 8 dma controller 8-1 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.1 when to use dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.2 dma priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.3 dma request synchronization . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.5.4 dma acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.5.5 dma and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.5.6 general-purpose dma channels . . . . . . . . . . . . . . . . . . . . . . 8-11 8.5.6.1 general-purpose dma usage . . . . . . . . . . . . . . . . . 8-12 8.5.6.2 general-purpose dma cycle. . . . . . . . . . . . . . . . . . 8-12 8.5.6.3 general-purpose dma transfer suspension. . . . . . 8-13 8.5.6.4 general-purpose dma source and destination addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 table of contents am186?cc/ch/cu microcontrollers users manual ix 8.5.6.5 general-purpose dma terminal count . . . . . . . . . . 8-14 8.5.6.6 general-purpose dma channel operations . . . . . . 8-14 8.5.7 smartdma channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 8.5.7.1 smartdma channels introduction . . . . . . . . . . . . . . 8-26 8.5.7.2 smartdma channel request source and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 8.5.7.3 smartdma channel memory overview . . . . . . . . . . 8-28 8.5.7.4 smartdma channel usage . . . . . . . . . . . . . . . . . . . 8-31 8.5.7.5 smartdma channel cycle . . . . . . . . . . . . . . . . . . . . 8-35 8.5.7.6 smartdma channel descriptor format . . . . . . . . . . 8-38 8.5.7.7 smartdma channel descriptor polling . . . . . . . . . . 8-41 8.5.7.8 smartdma channel interrupts . . . . . . . . . . . . . . . . . 8-42 8.5.7.9 smartdma channel use without cpu intervention 8-42 8.5.8 dma and usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 8.5.9 software-related considerations . . . . . . . . . . . . . . . . . . . . . . 8-43 8.5.10 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 8.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 chapter 9 programmable i/o signals 9-1 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5.2 defining the pio signal as input or output . . . . . . . . . . . . . . . . 9-5 9.5.3 driving data on the pio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.5.4 using pios as open-drain outputs . . . . . . . . . . . . . . . . . . . . . . 9-6 9.5.5 setting and clearing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.5.6 hardware-related considerations . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.5.7 software-related considerations . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.5.8 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 chapter 10 programmable timers 10-1 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.5.2 timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.5.3 timer 0 and timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.5.4 requesting interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.5.5 software polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.5.6 generating waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.5.7 pulse width demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.5.7.1 handling short signal durations . . . . . . . . . . . . . . . 10-7 10.5.7.2 handling long signal durations . . . . . . . . . . . . . . . 10-7 10.5.8 software-related considerations . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.9 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 chapter 11 watchdog timer 11-1 11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 table of contents x am186?cc/ch/cu microcontrollers users manual 11.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.5.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5.3 hardware-related considerations . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5.4 software-related considerations . . . . . . . . . . . . . . . . . . . . . . 11-5 11.5.5 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 chapter 12 serial communications overview 12-1 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.1 multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.2 sample applications for the am186cc communications controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3 serial communications introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3.1 asynchronous and synchronous communications . . . . . . . . . 12-6 12.3.2 hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3.3 fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.3.4 polled, interrupt, and dma modes . . . . . . . . . . . . . . . . . . . . . . 12-7 12.3.5 simplex, half-duplex, and full-duplex systems . . . . . . . . . . . 12-8 chapter 13 asynchronous serial ports (uarts) 13-1 13.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.5.1.1 transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.5.1.2 receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.5.1.3 autobaud mode (high-speed uart only) . . . . . . . 13-7 13.5.2 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.5.2.1 data overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.5.2.2 address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.5.2.3 receive status and data . . . . . . . . . . . . . . . . . . . . 13-10 13.5.2.4 extended reads and writes . . . . . . . . . . . . . . . . . 13-10 13.5.3 fifos (high-speed uart only) . . . . . . . . . . . . . . . . . . . . . . 13-11 13.5.3.1 transmit fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.5.3.2 receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.5.3.3 using the fifos in polled, interrupt, or dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.5.4 cts/rtr hardware flow control . . . . . . . . . . . . . . . . . . . . . 13-13 13.5.5 clock sources and baud rate . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.5.5.1 programming the baud rate . . . . . . . . . . . . . . . . . 13-15 13.5.5.2 receiver bit sampling . . . . . . . . . . . . . . . . . . . . . . 13-16 13.5.5.3 detecting the baud rate automatically (high-speed uart only). . . . . . . . . . . . . . . . . . . . 13-16 13.5.6 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.5.7 break detection and generation. . . . . . . . . . . . . . . . . . . . . . . 13-20 13.5.8 receive special-character matching (high-speed uart only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 13.5.9 interface to general-purpose dma channels . . . . . . . . . . . . 13-21 13.5.10 hardware-related considerations . . . . . . . . . . . . . . . . . . . . . 13-22 13.5.11 software-related considerations . . . . . . . . . . . . . . . . . . . . . 13-22 13.5.12 comparison to other devices. . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 table of contents am186?cc/ch/cu microcontrollers users manual xi chapter 14 synchronous serial port (ssi) 14-1 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.5.2 master/slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.5.3 signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.5.3.1 sclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.5.3.2 sdata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.5.3.3 sden . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.5.3.4 ssi transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.5.4 software-related considerations . . . . . . . . . . . . . . . . . . . . . . 14-8 14.5.5 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 14.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 chapter 15 high-level data link control (hdlc) 15-1 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.5.2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.5.2.1 smartdma interface . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.5.2.2 programmed i/o interface . . . . . . . . . . . . . . . . . . . . 15-8 15.5.3 general hdlc options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.5.4 hdlc transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.5.5 hdlc receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.5.6 hdlc and smartdma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.5.6.1 hdlc transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.5.6.2 hdlc receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.5.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.5.7.1 transmit interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.5.7.2 receive interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.5.8 hardware-related considerations . . . . . . . . . . . . . . . . . . . . . 15-20 15.5.9 software-related considerations . . . . . . . . . . . . . . . . . . . . . 15-21 15.5.10 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 chapter 16 hdlc external serial interface configuration (tsas) 16-1 16.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.5.2 programmable time slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.5.3 muxing logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.5.4 external interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.5.4.1 raw dce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.5.4.2 pcm highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.5.4.3 gci. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.5.5 software-related considerations . . . . . . . . . . . . . . . . . . . . . 16-14 16.5.6 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 table of contents xii am186?cc/ch/cu microcontrollers users manual chapter 17 general circuit interface (gci) 17-1 17.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.5.1.1 transmitting data. . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.5.1.2 receiving data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.5.2 gci structure: channels and frames . . . . . . . . . . . . . . . . . . . 17-8 17.5.3 gci applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.5.4 gci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.5.4.1 gci bus deactivation/activation . . . . . . . . . . . . . . . 17-9 17.5.4.2 gci bus reversal . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.5.5 gci interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17.5.5.1 four-pin interface . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17.5.5.2 gci-to-pcm converted pin interface . . . . . . . . . . 17-14 17.5.6 operating frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 17.5.7 gci channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 17.5.7.1 gci hdlc channel steering . . . . . . . . . . . . . . . . . 17-14 17.5.7.2 monitor channel operation . . . . . . . . . . . . . . . . . . 17-14 17.5.7.3 monitor channel collision detection . . . . . . . . . . . 17-14 17.5.7.4 c/i channel operation . . . . . . . . . . . . . . . . . . . . . . 17-15 17.5.7.5 tic bus support . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.5.7.6 ic channel operation . . . . . . . . . . . . . . . . . . . . . . 17-19 17.5.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.5.9 software-related considerations . . . . . . . . . . . . . . . . . . . . . 17-20 17.5.10 comparison to other devices . . . . . . . . . . . . . . . . . . . . . . . . 17-20 17.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 chapter 18 universal serial bus (usb) 18-1 18.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3 system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3.1 signal trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3.1.1 usb transceiver interface . . . . . . . . . . . . . . . . . . . . 18-3 18.3.1.2 programmable connect and disconnect . . . . . . . . . 18-3 18.3.1.3 usb clock source . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.3.1.4 isochronous synchronization signals . . . . . . . . . . . 18-6 18.3.2 dma trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 18.5.1 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 18.5.1.1 general usb peripheral controller programming issues . . . . . . . . . . . . . . . . . . . . . . . 18-10 18.5.1.2 programming the control endpoint . . . . . . . . . . . . 18-11 18.5.1.3 programming the interrupt endpoint . . . . . . . . . . . 18-11 18.5.1.4 programming data endpoints . . . . . . . . . . . . . . . . 18-12 18.5.2 data transmission and data types . . . . . . . . . . . . . . . . . . . . 18-16 18.5.2.1 usb suspend, resume, and remote wakeup . . . 18-16 18.5.2.2 usb reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17 18.5.2.3 usb protocol handling, in direction . . . . . . . . . . . 18-17 18.5.2.4 usb protocol handling, out direction . . . . . . . . . 18-17 18.5.3 handling usb data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 18.5.4 polled i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 18.5.5 interrupt-driven i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 table of contents am186?cc/ch/cu microcontrollers users manual xiii 18.5.6 using usb with dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 18.5.6.1 dma availability . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 18.5.6.2 dma/fifo interaction . . . . . . . . . . . . . . . . . . . . . . 18-20 18.5.6.3 setting up dma for usb . . . . . . . . . . . . . . . . . . . . 18-21 18.5.6.4 short packets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 18.5.6.5 error recovery on bulk and interrupt endpoints . . 18-22 18.5.6.6 error recovery on isochronous endpoints . . . . . . 18-23 18.5.7 isochronous transfer synchronization . . . . . . . . . . . . . . . . . 18-23 18.5.8 isochronous transfer features . . . . . . . . . . . . . . . . . . . . . . . 18-24 18.5.9 command handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26 18.5.9.1 commands handled by device software . . . . . . . 18-26 18.5.9.2 commands handled by the usb peripheral controller hardware . . . . . . . . . . . . . . . . . . . . . . . . 18-27 18.5.10 command protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28 18.5.10.1 data transfer using the control endpoint . . . . . . . 18-29 18.5.10.2 control endpoint interrupts . . . . . . . . . . . . . . . . . . 18-29 18.5.11 interrupt endpoint programming . . . . . . . . . . . . . . . . . . . . . . 18-29 18.5.11.1 usb command processing and the interrupt endpoint . . . . . . . . . . . . . . . . . . . . . . . . . 18-30 18.5.11.2 data transfer with the interrupt endpoint . . . . . . . 18-30 18.5.11.3 interrupt endpoint interrupts . . . . . . . . . . . . . . . . . 18-30 18.5.12 endpoint definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30 18.5.12.1 control endpoint definition . . . . . . . . . . . . . . . . . . 18-30 18.5.12.2 interrupt endpoint definition . . . . . . . . . . . . . . . . . 18-31 18.5.12.3 data endpoint definition . . . . . . . . . . . . . . . . . . . . 18-32 18.5.13 software-related considerations . . . . . . . . . . . . . . . . . . . . . 18-33 18.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 appendix a register summary a-1 glossary glossary-1 index index-1 table of contents xiv am186?cc/ch/cu microcontrollers users manual list of figures figure 1-1 am186cc communications controller block diagram . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 1-2 am186ch hdlc microcontroller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 1-3 am186cu usb microcontroller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 1-4 isdn terminal adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 figure 1-5 isdn-to-ethernet low-end router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 figure 1-6 32-channel linecard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 figure 2-1 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 figure 2-2 processor status flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 figure 2-3 physical address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 figure 2-4 memory and i/o space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 figure 2-5 supported data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 figure 3-1 typical microcontroller memory system with dram . . . . . . . . . . . . . . . . . . . . . . . 3-29 figure 3-2 typical microcontroller memory system with sram . . . . . . . . . . . . . . . . . . . . . . 3-29 figure 3-3 am186cc/ch/cu microcontroller clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 figure 5-1 chip selects and dram block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 figure 5-2 chip selectable memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-3 chip selectable i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 figure 6-1 chip selects and dram block diagram (same as figure 5-1) . . . . . . . . . . . . . . . . 6-2 figure 7-1 interrupts block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 figure 7-2 interrupt vector translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 figure 7-3 partial block diagram of interrupt controller scheme . . . . . . . . . . . . . . . . . . . . . . 7-15 figure 8-1 dma block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 figure 8-2 source versus destination synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 figure 8-3 dma request sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 figure 8-4 source-synchronized general-purpose dma transfers . . . . . . . . . . . . . . . . . . . . 8-18 figure 8-5 destination-synchronized general-purpose dma transfers . . . . . . . . . . . . . . . . . 8-19 figure 8-6 smartdma channel descriptor ring example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 figure 8-7 smartdma channel memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 figure 8-8 smartdma transmit channel flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 figure 8-9 smartdma receive channel flow diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38 figure 9-1 pio operation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 figure 10-1 programmable timers block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 figure 10-2 pulse width demodulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 figure 11-1 watchdog timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 figure 11-2 access to the wdtcon register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 figure 12-1 hdlc control application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 figure 12-2 pots linecard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 figure 12-3 isdn application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5 figure 12-4 isdn application with gci-to-pcm highway conversion . . . . . . . . . . . . . . . . . . . 12-5 figure 12-5 cts /rtr protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 figure 13-1 uarts block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 figure 13-2 uarts frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 figure 13-3 uarts timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8 figure 13-4 rtr_u signal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 figure 13-5 rtr_hu signal behavior with receive fifos. . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 figure 13-6 uarts clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 figure 13-7 worst case % error per bit vs. baud divisor without autobaud enhancement . 13-17 figure 13-8 detectable baud ranges for various frequencies. . . . . . . . . . . . . . . . . . . . . . . . 13-17 figure 13-9 autobaud enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 figure 13-10 break character example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 figure 14-1 ssi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4-2 figure 14-2 synchronous serial interface system application example . . . . . . . . . . . . . . . . . . 14-3 figure 14-3 ssi multiple transmit with sden as external device enable . . . . . . . . . . . . . . . . 14-7 figure 14-4 ssi multiple transmit with pio as external device enable . . . . . . . . . . . . . . . . . . 14-7 figure 14-5 ssi single-transmit, multiple-receive with sden as external device enable . . . 14-8 figure 15-1 hdlc frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1 table of contents am186?cc/ch/cu microcontrollers users manual xv figure 15-2 hdlc, tsa, and gci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 figure 15-3 hdlc transmitter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 figure 15-4 cts controlled start of transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 figure 15-5 cts controlled end of transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 figure 15-6 cts inactive at end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 figure 15-7 hdlc receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 figure 15-8 rtr timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 figure 16-1 block diagram for tsa multiplexing (am186cc communications controller) . . . 16-3 figure 16-2 block diagram for tsa multiplexing (am186ch hdlc microcontroller). . . . . . . . 16-3 figure 16-3 hdlc, tsa, and gci block diagram (same as figure 15-2) . . . . . . . . . . . . . . . . 16-4 figure 16-4 isdn pcm system application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 figure 16-5 isdn basic-rate gci application (am186cc communications controller) . . . . 16-10 figure 16-6 programmable frame sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 figure 16-7 converted gci clock and frame sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 figure 17-1 hdlc, tsa, and gci block diagram (same as figure 15-2) . . . . . . . . . . . . . . . . 17-2 figure 17-2 isdn ta gci-to-pcm conversion system application example . . . . . . . . . . . . . . 17-3 figure 17-3 gci terminal mode frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 figure 17-4 bus activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 figure 17-5 downstream versus upstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 figure 17-6 gci with bus reversal enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 figure 17-7 gci with bus reversal disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 figure 17-8 tic bus downstream format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 figure 17-9 tic bus upstream format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 figure 18-1 usb interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 figure 18-2 usb with internal transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 figure 18-3 usb with external transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 table of contents xvi am186?cc/ch/cu microcontrollers users manual list of tables table 0-1 documentation conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii table 1-1 feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 table 2-1 internal processor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 table 2-2 configuration register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 table 2-3 peripheral register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-4 segment register selection rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 table 2-5 memory addressing mode examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 table 3-1 multiplexed signal trade-offs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 table 3-2 multiplexed signal trade-offs ordered by pio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 table 3-3 system configuration register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 table 3-4 cpu and internal peripheral states immediately following power-on reset . . . . . 3-6 table 3-5 reset configuration pins (pinstraps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 table 3-6 signal descriptions table definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 table 3-7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 10 table 3-8 programming am186cc/ch/cu microcontrollers bus width . . . . . . . . . . . . . . . . 3-31 table 5-1 chip selects multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 table 5-2 chip select register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 table 5-3 signal function when ucs or lcs is configured for dram. . . . . . . . . . . . . . . . . . 5-7 table 6-1 dram multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 table 6-2 dram controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 table 6-3 dram supported by the am186cc/ch/cu microcontrollers . . . . . . . . . . . . . . . . . 6-4 table 6-4 address multiplexing reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 table 6-5 refresh interval times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 6 table 7-1 interrupt multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 table 7-2 interrupt controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 table 7-3 interrupt types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-12 table 7-4 interrupt channel map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 table 7-5 interrupt channel sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 table 8-1 dma multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 table 8-2 dma controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 table 8-3 am186cc communications controller dma channel use . . . . . . . . . . . . . . . . . . . 8-8 table 8-4 am186ch hdlc microcontroller dma channel use . . . . . . . . . . . . . . . . . . . . . . . . 8-8 table 8-5 am186cu usb microcontroller dma channel use . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 table 8-6 general-purpose dma data transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 table 8-7 general-purpose dma request source and synchronization . . . . . . . . . . . . . . . 8-17 table 8-8 maximum dma transfer rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 table 8-9 example register settings for uarts and circular buffers . . . . . . . . . . . . . . . . . . 8-22 table 8-10 am186cc smartdma channel request source and synchronization . . . . . . . . . 8-27 table 8-11 am186ch smartdma channel request source and synchronization . . . . . . . . . 8-28 table 8-12 am186cu smartdma channel request source and synchronization . . . . . . . . . 8-28 table 8-13 smartdma transmit channel descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 table 8-14 smartdma receive channel descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 table 9-1 pio multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 table 9-2 pio register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 table 9-3 pio mode and pio direction register bit settings. . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 table 9-4 pio set and pio clear registers effect on pio data register . . . . . . . . . . . . . . . . 9-6 table 10-1 programmable timer multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 table 10-2 programmable timers register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 table 10-3 timer 0 and timer 1 behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 table 11-1 watchdog timer multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 table 11-2 watchdog timer register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 table 12-1 multiplexed signal trade-offs for serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 12-2 table 13-1 uarts multiplexed signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 table 13-2 uarts register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 table 13-3 baud rate table for uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 table 13-4 examples of autobaud enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 table of contents am186?cc/ch/cu microcontrollers users manual xvii table 13-5 uarts interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 table 14-1 ssi multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 table 14-2 ssi register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 table 15-1 hdlc/tsa/gci multiplexed signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 table 15-2 hdlc register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 table 16-1 hdlc/tsa/gci multiplexed signals (same as table 15-1) . . . . . . . . . . . . . . . . . . 16-5 table 16-2 tsa register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 table 16-3 timing parameters per device (supported pcm codecs in gci mode) . . . . . . . 16-14 table 17-1 hdlc/tsa/gci multiplexed signals (same as table 15-1) . . . . . . . . . . . . . . . . . . 17-3 table 17-2 gci register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 table 17-3 gci signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 table 17-4 converted gci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 table 17-5 tic bus bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 table 18-1 usb multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 table 18-2 usb pll mode pinstraps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 table 18-3 usb register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 table 18-4 usb endpoints used with dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 table 18-5 usb commands handled by device software. . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 table 18-6 usb commands handled by usb peripheral controller hardware. . . . . . . . . . . 18-28 table 18-7 control endpoint definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-31 table 18-8 interrupt endpoint definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-31 table 18-9 data endpoints aCd definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32 table a-1 am186cc/ch/cu microcontrollers register summary . . . . . . . . . . . . . . . . . . . . . .a-2 table of contents xviii am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual xix preface introduction comm86 family the am 186?cc communications controller, am186ch hdlc microcontroller, and am186cu usb microcontroller, the first members of the amd comm86? family, are cost- effective, high-performance embedded microcontroller solutions for communications applications. these highly integrated microcontrollers enable customers to save system costs and increase performance over 8-bit microcontrollers and other 16-bit microcontrollers. all of these microcontrollers offer the advantages of the x86 development environments widely available native development tools, applications, and system software. additionally, the microcontrollers use the industry-standard 186 instruction set that is part of the amd e86? family, which continually offers instruction-set-compatible upgrades. built into each of the microcontrollers is a wide range of communications features required in many communications applications. purpose of this manual this manual describes the technical features and programming interface of the am186cc, am186ch, and am186cu microcontrollers. intended audience the am186cc/ch/cu microcontrollers users manual , order #21914, is intended for computer software and hardware engineers and system architects who are designing or are considering designing systems based on one of these controllers. overview of this manual this manual is organized into the following chapters: n chapter 1, architectural overview, provides an overview of the features of the microcontrollers, including a block diagram and sample application diagrams. n chapter 2, configuration basics, provides basic information about configuring the microcontrollers, including discussions of the registers, memory organization, address generation, i/o space, peripheral control block, instruction set, segments, data types, and addressing modes. n chapter 3, system overview, contains descriptions of the microcontrollers system configuration registers, initialization and processor reset, signals, bus interface, and clock control. n chapter 4, emulator support, describes the various features available in the microcontrollers to facilitate the design and operation of in-circuit emulators, and discusses common concerns shared among emulator developers. n chapter 5, chip selects, describes the six chip selects provided for use with memory devices and the eight provided for use with peripherals in either memory or i/o space. n chapter 6, dram controller, discusses the fully integrated dram controller that provides a glueless interface to 40-, 50-, 60-, and 70-ns extended data out (edo) dram. introduction xx am186?cc/ch/cu microcontrollers users manual n chapter 7, interrupts, describes the microcontrollers support for interrupts, both maskable and nonmaskable. it discusses interrupt sequence and priority as well as how to configure the maskable interrupt sources through the interrupt channels. it also describes the nonmaskable interrupts. n chapter 8, dma controller, describes how to use the dma channels (general-purpose and smartdma channels) to transfer data between memory and internal and external peripherals. n chapter 9, programmable i/o signals, discusses the user programmable input/output signals (pios). n chapter 10, programmable timers, tells how to use the programmable timers for the following tasks: counting or timing external events, generating nonrepetitive or variable- duty-cycle waveforms, generating interrupts, supporting real-time coding and time-delay applications through polling, prescaling the other timer, requesting dma, or measuring pulse widths (as a pwd). n chapter 11, watchdog timer, describes how to use the watchdog timer to generate nonmaskable interrupts (nmis), microcontroller resets, and system resets when the programmable time-out value is reached. n chapter 12, serial communications overview, discusses the serial communications features of the microcontrollers and their trade-offs, and provides a brief overview of serial communications. n chapter 13, asynchronous serial ports (uarts), describes how to use the uart and high-speed uart for asynchronous serial data transfer. n chapter 14, synchronous serial port (ssi), discusses how to use the ssi synchronous serial port to provide half-duplex, bidirectional communications between the microcontrollers and other system components n chapter 15, high-level data link control (hdlc), provides a brief overview of hdlc and describes how to configure the hdlc channels to support data movement in a variety of applications. n chapter 16, hdlc external serial interface configuration (tsas), describes how to use the time-division multiplex features to configure the hdlc external serial interfaces. each time-slot assigner (tsa) can be programmed to select between raw dce and dedicated pcm highway external interfaces, as well as to multiplex gci/pcm highway data. n chapter 17, general circuit interface (gci), discusses how to configure the gci controller for a gci interface on hdlc channel a, or multiplexed gci/pcm highway interfaces to the other channels n chapter 18, universal serial bus (usb), covers the highly flexible integrated usb peripheral controller and how to implement a variety of microcontroller-based usb peripheral devices for telephony, audio, or other high-end applications. n appendix a, register summary, provides a summary of all the microcontroller peripheral control block (pcb) registers, listed in offset order. n the glossary provides definitions of significant terms used in this manual. n the index contains extensive references to make it easier to find specific information. ch cc ch cc cc cu cc introduction am186?cc/ch/cu microcontrollers users manual xxi related documents the following documents contain additional information that will be useful in designing an embedded application based on the am186cc/ch/cu microcontrollers. amd documentation in addition to this manual, the documentation set for the am186cc/ch/cu microcontrollers includes the following documents: n the am186?cc communications controller data sheet , order #21915, the am186?ch hdlc microcontroller data sheet , order #22024, and the am186?cu usb microcontroller data sheet , order #22025, include complete pin lists, pin state tables, timing and thermal characteristics, and package dimensions for their particular microcontroller. n the am186?cc/ch/cu microcontrollers register set manual , order #21916, fully describes all the registers required to program the microcontrollers. n the am186 and am188 family instruction set manual , order #21267, provides a detailed description and examples for each instruction included in the am186 and am188 family instruction set. n interfacing an am186?cc communications controller to an amd slac? device using the enhanced ssi , order #21921, application note describes how to connect these two devices. the same techniques can be used to connect the am186cc microcontroller to any slac device. n am186?cc/ch/cu communications controller customer development platform board manual , order #22002, which describes a platform for silicon evaluation and software development, as well as a router/isdn terminal adapter module. other information of interest includes: n e86? family products and development tools cd , order #21058, provides a single- source multimedia tool for customer evaluation of amd products, as well as fusione86 sm partner tools and technologies that support the e86 and comm86 families. technical documentation is included on the cd in pdf format. n iom-2 interface reference guide , order #12576, describes the terminal version of the iom-2/gci interface. to order literature, contact the nearest amd sales office or call the literature center at one of the numbers on the back cover of this manual. in addition, many documents are available in pdf form on the amd web site. to access the amd home page, go to www.amd.com . then follow the embedded processors link for information about e86 and comm86 products. introduction xxii am186?cc/ch/cu microcontrollers users manual additional information the following non-amd documents and sources provide additional information that may be of interest to am186cc and am186cu microcontroller users: n universal serial bus specification, revision 1.0 , available from the usb web site at http://www.usb.org . n universal serial bus system architecture , by don anderson, mindshare, inc., addison wesley developers press, 1997. documentation conventions table 0-1 lists the documentation conventions used throughout this manual. . table 0-1 documentation conventions notation meaning general bit a single bit in a register bit field two or more consecutive and related bits set the en bit write a 1 to the en bit clear the en bit write a 0 to the en bit external reset a reset caused by asserting the res input signal internal reset a reset initiated by the watchdog timer (see chapter 11, watchdog timer) system reset assertion of the resout signal to reset external peripherals. an external reset always causes a system reset; an internal reset can optionally cause a system reset. offset 000h a register offset, relative to the base of the current pcb space defined in the relocation (reloc) register pin naming { } pin function during hardware reset (pinstrap) [ ] alternative pin function pin refers to the physical wire. signal refers to the electrical signal that flows across a pin. signal a line over a signal name indicates that the signal is active low; a signal name without a line is active high. mcs3 Cmcs0 all four signals (or registers, or fields) mcsx any of the four signals (or registers, or fields) numbers b binary number d decimal number decimal is the default radix h hexadecimal number x in a number any of several values is legal; for example, 0x01b can be either 0001b or 0101b [xCy] the bit field that consists of bits x through y cu cc introduction am186?cc/ch/cu microcontrollers users manual xxiii microcontroller-specific information this manual provides information that applies to all three of the am186cc/ch/cu microcontrollers as well as information that is specific to each controller. to help identify controller-specific information, this manual uses icons in the margin and within tables and figures. table 0-1 illustrates these icons. some chapters apply only to one or two of the controllers. these chapters have a note at the beginning of the chapter with the relevant icons next to the note. one or more icons immediately following a heading indicates that the information under that heading (up to the next heading) applies only to the indicated controllers. icons that appear other than at the beginning of the chapter or immediately following a heading apply to the specific paragraph, list, figure, portion of figure, table, or table cell indicated by the icon. if a paragraph, list, figure, or table does not have any accompanying icons, the information applies to all of the microcontrollers covered by the chapter. microcontroller-specific information icons information specific to the am 186cc communications controller information specific to the am 186ch hdlc microcontroller information specific to the am 186cu usb microcontroller table 0-1 documentation conventions (continued) notation meaning cc ch cu introduction xxiv am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 1-1 chapter 1 architectural overview 1.1 features the am186cc, am186ch, and am186cu microcontrollers, the first members of the amd comm86? family, are cost-effective, high-performance microcontroller solutions for communications applications. these highly integrated microcontrollers enable customers to save system costs and increase performance over 8-bit microcontrollers and other 16-bit microcontrollers. these microcontrollers offer the advantages of the x86 development environments widely available native development tools, applications, and system software. additionally, these microcontrollers use the industry-standard 186 instruction set that is part of the amd e86 family, which continually offers instruction-set-compatible upgrades. use of this instruction set ensures both backward and upward software compatibility. amd offers complete solutions with these microcontrollers. a customer development platform board for silicon evaluation and software development is available. reference designs under development include a low-end router with integrated services digital network (isdn), ethernet, usb, and plain old telephone service (pots), as well as an isdn terminal adapter featuring usb. amd and its fusione86 sm partners offer boards, schematics, drivers, protocol stacks, and routing software for these reference designs to enable fast time to market. 1.2 am186cc communications controller built into the am186cc microcontroller is a wide range of communications features required in many communications applications, including high-level data link control (hdlc) and the universal serial bus (usb). it includes the following distinctive characteristics: n serial communications peripherals C four high-level data link control (hdlc) channels C usb peripheral controller C eight smartdma? channels to support hdlc and usb C four independent time slot assigners (tsas) C physical interface for hdlc channels can be raw dce, pcm highway, or gci (iom-2) C high-speed uart with autobaud C uart C synchronous serial interface (ssi) cc architectural overview 1-2 am186?cc/ch/cu microcontrollers users manual n system peripherals C interrupt controller (36 maskable interrupts) C four general-purpose dma channels C 48 programmable i/o signals C three programmable 16-bit timers C hardware watchdog timer n memory and peripheral interface C integrated dram controller C glueless interface to ram/rom/flash memory (40-ns flash memory required for zero-wait-state operation at 50 mhz) C fourteen chip selects (6 memory, 8 peripheral) C external bus mastering support C multiplexed and nonmultiplexed address/data bus C programmable bus sizing C 8-bit boot option 1.2.1 am186ch hdlc microcontroller the am186ch hdlc microcontroller is a cost-reduced derivative of the am186cc microcontroller that is targeted towards cost-sensitive applications such as linecards and digital phones. the am186ch hdlc microcontroller is pin-compatible with the am186cc microcontroller and offers many of the same features, yet the am186ch hdlc microcontroller provides a cost-effective solution for communications devices that require fewer hdlc channels and do not need gci or usb. it includes the following distinctive characteristics: n serial communications peripherals C two high-level data link control (hdlc) channels C four smartdma channels to support hdlc C two independent time slot assigners (tsas) C physical interface for hdlc channels can be raw dce or pcm highway C high-speed uart with autobaud C uart C synchronous serial interface (ssi) n system peripherals C interrupt controller (31 maskable interrupts) C four general-purpose dma channels C 48 programmable i/o signals C three programmable 16-bit timers C hardware watchdog timer ch architectural overview am186?cc/ch/cu microcontrollers users manual 1-3 n memory and peripheral interface C integrated dram controller C glueless interface to ram/rom/flash memory (40-ns flash memory required for zero-wait-state operation at 50 mhz) C fourteen chip selects (6 memory, 8 peripheral) C external bus mastering support C multiplexed and nonmultiplexed address/data bus C programmable bus sizing C 8-bit boot option 1.2.2 am186cu usb microcontroller the am186cu usb microcontroller is a cost-reduced derivative of the am186cc microcontroller that is targeted towards cost-sensitive applications such as usb peripherals and digital-subscriber- line (dsl) modems. the am186cu usb microcontroller is pin- compatible with the am186cc microcontroller and offers many of the same features, yet the am186cu usb microcontroller provides a cost-effective solution for usb devices that do not need gci or hdlc. it includes the following distinctive characteristics: n serial communications peripherals C usb peripheral controller C four smartdma channels to support usb C high-speed uart with autobaud C uart C synchronous serial interface (ssi) n system peripherals C interrupt controller (30 maskable interrupts) C four general-purpose dma channels C 48 programmable i/o signals C three programmable 16-bit timers C hardware watchdog timer n memory and peripheral interface C integrated dram controller C glueless interface to ram/rom/flash memory (40-ns flash memory required for zero-wait-state operation at 50 mhz) C fourteen chip selects (6 memory, 8 peripheral) C external bus mastering support C multiplexed and nonmultiplexed address/data bus C programmable bus sizing C 8-bit boot option cu architectural overview 1-4 am186?cc/ch/cu microcontrollers users manual 1.2.3 feature comparison table 1-1 summarizes and compares the features of each of the microcontrollers. 1.3 block diagrams figure 1-1, figure 1-2, and figure 1-3 show the block diagrams for the am186cc/ch/cu microcontrollers, respectively. table 1-1 feature comparison feature hdlc channels 4 2 C time slot assigners (tsas) 4 2 C raw dce interface 44 C pcm highway interface 44 C gci (iom-2) interface 4 CC usb peripheral controller 4 C 4 smartdma channels 8 (4 pair) 4 (2 pair) 4 (2 pair) general-purpose dma channels 4 4 4 high-speed uart 444 uart 444 synchronous serial interface (ssi) 444 internal maskable interrupts 19 14 13 external maskable interrupts 17 17 17 programmable i/o signals (pios) 48 48 48 16-bit timers 333 hardware watchdog timer 444 integrated dram controller 444 glueless interface to ram/rom/flash memory 444 memory chip selects 6 6 6 peripheral chip selects 8 8 8 external bus mastering support 444 multiplexed and nonmultiplexed address/data bus 444 programmable bus sizing 444 8-bit boot option 444 cc ch cu architectural overview am186?cc/ch/cu microcontrollers users manual 1-5 figure 1-1 am186cc communications controller block diagram figure 1-2 am186ch hdlc microcontroller block diagram figure 1-3 am186cu usb microcontroller block diagram smart dma (8) general- purpose dma (4) physical interface raw dce pcm serial communications peripherals tsa tsa tsa tsa muxing glueless interface to ram/rom dram controller am186 cpu chip selects (48) watchdog timer interrupt controller uart high-speed uart with autobaud usb synchronous hdlc hdlc hdlc hdlc (14) highway gci (iom-2) (17 ext. sources) pios serial interface (ssi) timers (3) system peripherals memory peripherals cc smart dma (4) general- purpose dma (4) physical interface raw dce pcm serial communications peripherals tsa tsa glueless interface to ram/rom dram controller am186 cpu chip selects (48) watchdog timer interrupt controller uart high-speed uart with autobaud synchronous hdlc hdlc (14) highway (17 ext. sources) pios serial interface (ssi) timers (3) system peripherals memory peripherals muxing ch smart dma (4) general- purpose dma (4) serial communications peripherals glueless interface to ram/rom dram controller am186 cpu chip selects (48) watchdog timer interrupt controller uart high-speed uart with autobaud usb synchronous (14) (17 ext. sources) pios serial interface (ssi) timers (3) system peripherals memory peripherals cu architectural overview 1-6 am186?cc/ch/cu microcontrollers users manual 1.4 architectural overview the architectural goal of the am186cc/ch/cu microcontrollers is to provide comprehensive communications features on a processor running the widely-known x86 instruction set. these microcontrollers combine communications peripherals with the am186 embedded cpu, resulting in highly integrated microcontrollers that provide system- cost and performance advantages for a wide range of communications applications. the following sections provide an overview of the features of the microcontrollers. the chapter number in parenthesis indicates where that feature is discussed in detail. 1.4.1 am186 embedded cpu (chapter 2) all members of the am186 family, including the am186cc/ch/cu microcontrollers, are compatible with the original industry-standard 186 parts, and build on the same core set of internal processor registers, instructions, and addressing modes. this chapter also describes the memory organization, address generation, i/o space, peripheral control block, segments, and data types. 1.4.2 serial communications support (chapter 12) the am186cc microcontroller supports eight serial interfaces: a usb peripheral controller, four hdlc channels, two uarts, and an ssi. in addition, it supports the use of gci and smartdma with the serial interfaces. the am186ch hdlc microcontroller supports five serial interfaces: two hdlc channels, two uarts, and an ssi. in addition, it supports the use of smartdma with the serial interfaces. the am186cu usb microcontroller supports four serial interfaces: a usb peripheral controller, two uarts, and an ssi. in addition, it supports the use of smartdma with the serial interfaces. for an overview of the serial communications features, see chapter 12, serial communications overview. 1.4.2.1 universal serial bus (chapter 18) the am186cc and am186cu microcontrollers each include a highly flexible integrated usb peripheral controller that lets designers implement a variety of microcontroller-based usb peripheral devices for telephony, audio, and other high-end applications. this integrated usb peripheral controller can provide a significant system-cost reduction compared to platforms that require a separate usb peripheral controller. the am186cc and am186cu microcontrollers act as usb peripheral devices. the usb is a half-duplex, master/slave, polled bus. in other words, the microcontroller speaks on the usb only in response to a request from the usb host, usually a personal computer. there can be only one speaker on the usb at a time. the usb controller does not support usb host or hub functions. however, the am186cc and am186cu microcontrollers can be used to implement usb peripheral functions in a device that also contains separate usb hub circuitry. use these microcontrollers in self-powered usb peripherals that use the full-speed signalling rate of 12 mbit/s; they do not support the usb low-speed rate of 1.5 mbit/s. each microcontroller includes an integrated usb transceiver to minimize system device count and cost, but an external transceiver can be used instead, if necessary. cc ch cu cu cc architectural overview am186?cc/ch/cu microcontrollers users manual 1-7 in addition, the usb peripheral controller supports the following: n an unlimited number of device descriptors. n a total of six endpoints: one control endpoint; one interrupt endpoint; and four data endpoints that can be configured as control, interrupt, bulk, or isochronous. the interrupt, bulk, and isochronous endpoints can be configured for the in or out direction. n two of the data endpoints have 16-byte fifos and two have 64-byte fifos. n fully integrated differential driver, which directly supports the usb interface. n specialized hardware, which supports adaptive isochronous data streams and automatically synchronizes with hdlc data streams. n general-purpose dma and smartdma channels. 1.4.2.2 hdlc channels (chapter 15) and tsas (chapter 16) the am186cc microcontroller provides four hdlc channels and the am186ch hdlc microcontroller provides two hdlc channels. these channels support the hdlc, sdlc, lap-b, lap-d, ppp, and v.120 protocols. the hdlc channels can also be used in transparent mode to support v.110. each hdlc channel can connect to an external serial interface directly (non-multiplexed mode), or can pass through a tsa (multiplexed mode). the flexible interface multiplexing arrangement allows each hdlc channel to have its own external interface, to share a common pcm highway or other time division multiplexed (tdm) bus with the other channels, or to work in some combination. the am186cc microcontroller supports raw dce, pcm highway, and gci interfaces. the am186ch hdlc microcontroller supports raw dce and pcm highway interfaces. each hdlc channels independent tsa allows it to extract a subset of data from a tdm bus. it can isolate the entire frame or as little as one bit per frame. the channels 12-bit counter defines the start/stop bit times as the number of bits after frame synchronization. the time slot can be an arbitrary number of bits up to 4096 bits. start bit and stop bit times identify the isolated portion of the tdm frame. support of less than eight bits per time slot, or bit slotting , allows isolation of from one to eight bits in a single time slot, providing a convenient way to work with d-channel data. each tdm bus can have up to 512 8-bit time slots. support of these features allows interoperation with pcm highway, e1, iom-2, t1, and other tdm buses. to make the am186cc and am186ch microcontrollers attractive devices for use where general hdlc capability is required, the hdlc channels support the following features: n clear-to-send (cts) and ready-to-receive (rtr) hardware handshaking and auto- enable operation n collision detection for multidrop applications n transparency mode n address comparison on receive n flag or mark idle operation n two dedicated buffer descriptor ring smartdma channels per hdlc channel n transmit and receive fifos n full-duplex data transfer ch cc cc ch architectural overview 1-8 am186?cc/ch/cu microcontrollers users manual each tsa channel can support a burst data rate to or from the hdlc of up to 10 mbit/s in both raw dce and pcm highway modes. in addition to raw dce and pcm highway, the am186cc microcontroller can share its gci interface with up to two other channels. in gci mode, the am 186cc microcontrollers tsa channels can support a burst data rate to or from the hdlc of up to 768 kbit/s. total system data throughput is highly dependent on the amount of per-packet and per- byte cpu processing, the rate at which packets are being sent, and other cpu activity. when combined with the tsas, the hdlc channels are suitable for use in a wide variety of applications such as isdn basic rate interface (bri) and primary rate interface (pri) b and d channels, pcm highway, x.25, frame relay, and other proprietary wide area network (wan) connections. 1.4.2.3 general circuit interface (chapter 17) the gci is an interface specification developed jointly by alcatel, italtel, gpt, and siemens. this specification defines an industry-standard serial bus for interconnecting telecommunications integrated circuits. the standard covers linecard, nt1, and terminal architectures for isdn applications. the am186cc microcontroller supports the terminal version of gci. the gci interface provides a glueless connection between the am186cc microcontroller and gci/iom-2 based isdn transceiver devices, such as the amd am79c30 or am79c32. the gci interface provides a 4-pin connection to the transceiver device. the am186cc microcontroller also allows conversion of the gci clock and gci frame sync into a format usable by pcm codecs, allowing the use of pcm codecs directly with gci/iom-2 transceivers. additional gci features include slave mode with pin reversal, terminal interchip communication (tic) bus support for d channel arbitration and collision detection, and support for one monitor and two command/indicate channels. 1.4.2.4 smartdma channels (chapter 8) each of the am186cc/ch/cu microcontrollers contain both smartdma channels and general-purpose dma channels (see general-purpose dma channels (chapter 8) on page 1-10). the smartdma channels provide a faster method for moving data between peripherals and memory with lower cpu utilization. smartdma transmits and receives data across multiple memory buffers and a sophisticated buffer-chaining mechanism. these channels work in pairs: transmitter and receiver. the transmit channels can transfer data only from memory to a peripheral; the receive channels can transfer data only from a peripheral to memory. the am186cc microcontroller provides a total of 12 dma channels: eight smartdma channels and four general-purpose dma channels. four of the smartdma channels (two pairs) are dedicated for use with two of the on-board hdlc channels. the remaining four smartdma channels (two pairs) can support either the third or fourth hdlc channel or universal serial bus (usb) endpoints a, b, c, or d. the am186ch hdlc microcontroller provides a total of eight dma channels: four smartdma channels to support the two hdlc channels and four general-purpose dma channels. the am186cu usb microcontroller provides a total of eight dma channels: four smartdma channels to support usb endpoints aCd and four general-purpose dma channels. ch cc cc cc cc ch cu architectural overview am186?cc/ch/cu microcontrollers users manual 1-9 1.4.2.5 asynchronous serial ports (chapter 13) the am186cc/ch/cu microcontrollers each have two asynchronous serial ports that provide full-duplex, bidirectional data transfer with speeds up to 460 kbaud. one port is a high-speed uart with transmit and receive fifos, special character matching, and automatic baud rate detection, suitable for implementation of a hayes-compatible modem interface to a host pc. there is also a lower speed uart, which typically is used for a low baud rate system configuration port or debug port. each of these uarts can derive its baud rate from the cpu clock or from a separate baud rate generator clock input. both uarts support 7-, 8-, or 9-bit data transfers; address bit generation and detection in 7- or 8-bit frames; one or two stop bits; even, odd, or no parity; break generation and detection; hardware flow control; and dma to and from the serial ports using the general-purpose dma channels (see general-purpose dma channels (chapter 8) on page 1-10). 1.4.2.6 synchronous serial port (chapter 14) the am186cc/ch/cu microcontrollers each include one ssi port, which provides a half- duplex, bidirectional communications interface between the microcontroller and other system components. typical applications use this interface to monitor the status of other system devices and to configure these devices under software control. in a communications application, these devices could be system components such as audio coder-decoders (codecs), line interface units, and transceivers. the ssi supports data transfer speeds of up to 25 mbit/s with a 50-mhz cpu clock. the ssi port operates as an interface master with the other attached devices acting as slave devices. using this protocol, the microcontroller sends a command byte to the attached device, and then follows that byte with either a read or write of a byte of data. the ssi port consists of three i/o pins: an enable (sden), a clock (sclk), and a bidirectional data pin (sdata). sden can be used directly as an enable for a single attached device. when more than one device requires control through the ssi, use pios to provide enable pins for those devices. the ssi port is, in general, software compatible with the am186em ssi port. some additional features have been added to the am186cc/ch/cu microcontrollers ssi implementation. in addition, the microcontroller can select the polarity of the sclk and sden pins, as well as the shift order of bits on the sdata pin (least-significant-bit first versus most-significant-bit first). the ssi port also offers a programmable clock divisor (dividing the clock from 2 to 256 in power of 2 increments), a bidirectional transmit/receive shift register, and direct connection to amd subscriber line audio-processing circuit (slac?) devices. 1.4.3 system peripherals the am186cc/ch/cu microcontrollers provide several additional system peripherals to simplify incorporation of the microcontroller into an embedded application. 1.4.3.1 interrupt controller (chapter 7) the am186cc/ch/cu microcontrollers each feature an interrupt controller, which arranges up to 36 maskable interrupt requests by priority and presents them one at a time to the cpu. the interrupt controller supports the maskable interrupt sources through the use of 15 channels. to make this possible, most interrupt channels support multiple interrupt sources. these channels are programmable to support the external interrupt pins or various peripheral devices that can be configured to generate interrupts. the maskable interrupt sources include 17 external sources plus a number of internal sources. the am186cc microcontroller has 19 internal maskable interrupt sources. cc architectural overview 1-10 am186?cc/ch/cu microcontrollers users manual the am186ch hdlc microcontroller has 14 internal maskable interrupt sources. the am186cu usb microcontroller has 13 internal maskable interrupt sources. in addition to interrupts managed by the interrupt controller, each microcontroller supports eight nonmaskable interruptsan external or internal nonmaskable interrupt (nmi), a trace interrupt, and software interrupts and exceptions. 1.4.3.2 general-purpose dma channels (chapter 8) four of the dma channels in each of the am186cc/ch/cu microcontrollers are general purpose. the general-purpose dma channels support data transfer between memory and i/o spaces (i.e., memory-to-i/o or i/o-to-memory) or within the same space (i.e., memory- to-memory or i/o-to-i/o). in addition, the microcontrollers support data transfer between peripherals and memory or i/o. internal peripherals that support general-purpose dma are timer 2, which can provide a periodic internal dma request, and the two asynchronous serial ports (uart and high-speed uart). external peripherals support dma transfers through the external dma request pins (drq1C drq0). each general-purpose channel accepts a dma request from one of three sources: the dma request signals (drq1Cdrq0), timer 2, or the uarts. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) in addition to the general-purpose channels, the microcontrollers provide smartdma channels (see smartdma channels (chapter 8) on page 1-8). the usb peripheral controller in the am186cc and am186cu microcontrollers can also request a general-purpose dma transfer. 1.4.3.3 programmable i/o signals (chapter 9) each of the am186cc/ch/cu microcontrollers provides 48 user-programmable input/ output signals (pios). in the am186cc microcontroller, each of these signals shares a pin with at least one alternate function. in the am186ch and am186cu microcontrollers, most but not all of the pios share a pin with alternate functions. if an application does not need the alternate function, the associated pio can be used by programming the pio registers. if a pin is enabled to function as a pio signal, the alternate function is disabled and does not affect the pin. a pio signal can operate as an input or output, with or without internal pullup or pulldown resistors (whether the resistors are pullup or pulldown depends on the pin configuration and is not user-configurable), or as an open-drain output. in addition to the three pios multiplexed with interrupt signals, eight other pios can be configured as external interrupt sources. for more information about pios as interrupt sources, see chapter 7, interrupts. 1.4.3.4 programmable timers (chapter 10) each of the am186cc/ch/cu microcontrollers has three 16-bit programmable timers. timers 0 and 1 are highly versatile and are each connected to two external pins (each one has an input and an output). these two timers can count or time external events that drive the timer input pins. timers 0 and 1 can also generate nonrepetitive or variable-duty-cycle waveforms on the timer output pins. timer 2 is not connected to any external pins. software can use it to generate interrupts, or poll it for real-time coding and time-delay applications. software can also use timer 2 as a prescaler to timer 0 and timer 1, or as a dma request source (see chapter 8, dma controller). the source clock for timer 2 is one-fourth of the cpu clock frequency. timers 0 and 1 can use every fourth cycle of the cpu clock as a source, or they can be driven from the timer ch cu cc cu architectural overview am186?cc/ch/cu microcontrollers users manual 1-11 input pins. when driven from a timer input pin, the timer is counting the event of an input transition. the microcontroller also provides a pulse width demodulation (pwd) option so that a toggling input signals low state and high state durations can be measured. 1.4.3.5 hardware watchdog timer (chapter 11) each of the am186cc/ch/cu microcontrollers provides a full-featured watchdog timer, which includes the ability to generate nmis, reset the microcontroller (except for pinstraps), and reset the system (assert resout ) when the time-out value is reached. the time-out value is programmable and ranges from 2 10 to 2 26 processor clocks. the watchdog timer is used to regain control when a system has failed due to a software error or the failure of an external device to respond in the expected way. software errors can sometimes be resolved by recapturing control of the execution sequence through a watchdog-timer-generated nmi. when an external device fails to respond, or responds incorrectly, it may be necessary to reset the microcontroller or the entire system, including external devices. the watchdog timer provides the flexibility to support both nmi and reset generation. 1.4.4 memory and peripheral interface each of the am186cc/ch/cu microcontrollers includes the following memory and peripheral interfaces. 1.4.4.1 system interfaces and clock control (chapter 3) the microcontroller includes a bus interface to control all accesses to the peripheral control block (pcb), memory-mapped and i/o-mapped external peripherals, and memory devices. the bus interface accesses the internal peripherals through the pcb. the bus interface features programmable bus sizing, separate byte/write enables, and the option to boot from an 8-bit or 16-bit device. the industry-standard 80c186 and 80c188 microcontrollers use a multiplexed address and data (ad) bus. the address is present on the ad bus only during the t 1 clock phase. the microcontrollers also provide the multiplexed ad bus and in addition, provide a nonmultiplexed address (a) bus. the a bus provides an address to the system for the complete bus cycle (t 1 Ct 4 ). the microcontroller operates with a v cc of 3.3 0.3 v. all the digital signals are capable of 5-v-tolerant i/o operation. the processor supports clock rates from 25 mhz to 50 mhz. commercial and industrial temperature ratings are available. the cpu can run in 1x, 2x, or 4x mode. the am186cc and am186cu microcontrollers provide separate crystal oscillator inputs for the usb peripheral controller and the cpu. flexibility is provided to run the entire device from a 12- or 24-mhz crystal when the usb is in use. the cpu can run in 1x, 2x, or 4x mode; the usb can run in 2x or 4x mode. 1.4.4.2 dynamic random access memory support (chapter 6) to support dram, the microcontroller has a fully integrated dram controller that provides a glueless interface to 25-ns to 70-ns extended data out (edo) dram (edo dram is sometimes called hyper-page mode dram). the microcontroller can access up to two banks of 4-mbit (256 kbit x 16 bit) dram. the microcontroller does not support page mode dram, fast page mode dram, asymmetrical dram, or 8-bit wide dram. the microcontroller provides zero-wait state operation at up to 50 mhz with 40-ns dram. this cc cu architectural overview 1-12 am186?cc/ch/cu microcontrollers users manual capability allows designs requiring larger amounts of memory to save system cost over sram designs by taking advantage of low dram costs. the dram interface uses various chip select pins to implement the ras /cas interface required by drams. the microcontrollers dram controller drives the ras /cas interface appropriately during both normal memory accesses and refresh. the microcontroller generates all required signals and does not require external logic. the dram multiplexed address pins connect to the microcontrollers odd address pins, starting with a1 on the microcontroller connecting to ma0 on the dram. the correct row and column address are generated on these odd address pins during a dram access. the ras pins are multiplexed with lcs or mcs3 , allowing a dram bank to be present in either high or low memory space. mcs2 and mcs1 function as the lower and upper cas pins, respectively, and define which byte of data in a 16-bit dram is being accessed. the microcontroller supports the most common dram refresh option, cas-before-ras. all refresh cycles contain three wait states to support the drams at various frequencies. the dram controller never performs a burst access. all accesses are single accesses to dram. if the pcs chip selects are decoded to be in the dram address range, pcs accesses take precedence over the dram. 1.4.4.3 chip selects (chapter 5) the microcontroller provides six chip select outputs for use with memory devices and eight more chip selects for use with peripherals in either memory or i/o space. the six memory chip selects can address three memory ranges. each peripheral chip select addresses a 256-byte block offset from a programmable base address. the microcontroller can be programmed to sense a ready signal for each of the peripheral or memory chip select lines. a bit in each chip select control register determines whether the external ready signal is required or ignored. in addition, the chip selects can control the number of wait states inserted in the bus cycle. although most memory and peripheral devices can be accessed with three or less wait states, some slower devices cannot. this feature allows devices to use wait states to slow down the bus. the chip select lines are active for all memory and i/o cycles in their programmed areas, whether the cycles are generated by the cpu or by the integrated dma unit. general enhancements over the original 80c186 include bus mastering (three-state) support for all chip selects, and activation only when the associated register is written (not when it is read). 1.4.5 in-circuit emulator support (chapter 4) because pins are an expensive resource, many play a dual role, and the programmer selects pio operation or an alternate function. however, a pin configured to be a pio may also be required for emulation support. therefore, it is important that before a design is committed to hardware, a user contact potential emulator suppliers for a list of emulator pin requirements. the am186cc/ch/cu microcontrollers are designed to minimize conflicts. in most cases, pin conflict is avoided. for example, if the ale signal is required for multiplex bus support, then it would not be programmed as pio33. if the multiplexed ad bus is not used for address determination, then ale can be programmed as a pio pin. architectural overview am186?cc/ch/cu microcontrollers users manual 1-13 1.5 applications the am186cc/ch/cu microcontrollers, with their integrated communications features, provide highly integrated, cost-effective solutions for a wide range of telecommunications and networking applications. n isdn modems and terminal adapters: next-generation isdn equipment requires usb (or high-speed uart capability), in addition to three channels of hdlc. n low-end routers: isdn to ethernet-based personal routers, often used for connections in small office/home office (soho) environments, require three channels of hdlc, as well as the high performance of a 16-bit controller. n linecard applications: typically, linecards used in central offices (cos), pabx equipment, and other telephony applications require one or two channels of hdlc. linecard manufacturers are moving to more lines per card for analog pots as a means of cost reduction. this, and digital linecards for support of isdn, often requires higher performance than existing 8-bit devices can offer. the am186cc and am186ch microcontrollers are ideal solutions for these applications because they integrate much of the necessary glue logic while providing higher performance. n xdsl applications: todays xdsl applications, such as high-speed adsl modems, require data handling of 2 mbit/s or greater and can take advantage of the usb interface for easy connectivity to the pc. n digital corded phones: typical digital telephone applications use up to three channels of hdlc and may use usb for merged pc telephony applications. n industrial control: embedded x86 processors have long been used in the industrial control market. these applications often require a robust, high-performance processor solution with the capability to easily communicate with other parts of a system. the am186cc and am186ch microcontrollers provide numerous interfaces to achieve this communication, including the ssi interface, high-speed uart, and the hdlc channels, which also can be used to create a multidrop backplane. n usb peripheral devices: these devices will become more common as the pc market embraces the usb protocol specified by the microsoft? windows 98 operating system. in addition to implementing communications device class systems such as an isdn terminal adapter, the usb peripheral controller makes the am186cc and am186cu usb microcontrollers suitable for certain pc desktop applications such as a usb camera interface, ink-jet printers, and scanners. n general communications applications: the am186cc/ch/cu microcontrollers will also find a home in general embedded applications, because many devices will incorporate communications capability in the future. these microcontrollers are especially attractive for 186 designs adding hdlc, usb, or both. the block diagrams beginning on page 1-5 show some typical designs. figure 1-4 shows an isdn terminal adapter. figure 1-5 shows a low-end router. figure 1-6 shows a 32- channel linecard. the isdn terminal adapter features an s/t or u interface and either a high-speed uart or usb connection for attaching the modem to the pc. the isdn-to-ethernet low-end router features an s/t or u interface, two pots lines, and a 10-mbit/s connection to the pc. the 32-channel linecard design demonstrates a linecard application where 32 lines terminate on the linecard. cc cc cc ch cc cu cc cc ch cc cu architectural overview 1-14 am186?cc/ch/cu microcontrollers users manual figure 1-4 isdn terminal adapter figure 1-5 isdn-to-ethernet low-end router cc cc architectural overview am186?cc/ch/cu microcontrollers users manual 1-15 figure 1-6 32-channel linecard ch cc architectural overview 1-16 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 2-1 chapter 2 configuration basics 2.1 overview all members of the am186 family, including the am186cc/ch/cu microcontrollers, build on the same core set of internal processor registers, instructions, and addressing modes. all members are compatible with the original industry-standard 186 parts. this chapter provides basic information about configuring the microcontrollers, including discussions of the registers, memory organization, address generation, i/o space, peripheral control block, instruction set, segments, data types, and addressing modes. 2.2 register set the microcontroller contains hundreds of configuration and control registers, both internal and external to the processor. the instruction set contains instructions to access the internal processor registers directly. peripheral registers are external to the processor. however, because the processor treats these peripheral registers either like memory or like i/o, instructions with memory or i/o operands can access peripheral registers. this section briefly describes these processor and peripheral registers. for detailed information on the microcontroller peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. 2.2.1 processor registers the base architecture of the am186cc/ch/cu microcontrollers has 14 registers, like all members of the am186 family. table 2-1 lists these registers. table 2-1 internal processor registers register name register mnemonic function general-purpose arithmetic and logical operand ax accumulator bx base cx count dx data base pointer bp stack segment, points to bottom of the stack frame source index si data movement and string instructions destination index di stack pointer sp stack segment, points to top of stack code segment cs points to the current code segment, which contains instructions to be fetched data segment ds selects memory segment addressable for data stack segment ss selects memory segment addressable for the stack extra segment es selects memory segment addressable for data processor status flags flags contains status and control flag bits instruction pointer ip contains offset address of next instruction to be executed configuration basics 2-2 am186?cc/ch/cu microcontrollers users manual these registers are grouped into the following categories: n general-purpose registers: eight 16-bit general-purpose registers support arithmetic and logical operands. four of these (ax, bx, cx, and dx) also operate as pairs of separate 8-bit registers (ah, al, bh, bl, ch, cl, dh, and dl). the destination index (di) and source index (si) general-purpose registers support data movement and string instructions. the base pointer (bp) and stack pointer (sp) general-purpose registers point to the bottom and to the top of the stack frame (in the stack segment), respectively. C base and index registers: four of the general-purpose registers (bp, bx, di, and si) also support the determination offset addresses of operands in memory. these registers can contain base addresses or indexes to particular locations within a segment. the addressing mode selects the specific registers for operand and address calculations. C stack pointer register: all stack operations (pop, popa, popf, push, pusha, pushf) utilize the stack pointer. the stack pointer (sp) register is always offset from the stack segment (ss) register, and no segment override is allowed. n segment registers: four 16-bit special-purpose registers (cs, ds, es, and ss) select, at any given time, the segments of memory that are immediately addressable for code (cs), data (ds and es), and stack (ss) memory. n status and control registers: two 16-bit special-purpose registers record or alter certain aspects of the processor statethe instruction pointer (ip) register contains the offset address of the next sequential instruction to be executed, and the processor status flags (flags) register contains status and control flag bits (see figure 2-1 and figure 2-2). figure 2-1 register set 2.2.2 processor status flags register the 16-bit processor status flags register, illustrated in figure 2-2, records specific characteristics of the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and controls the operation of the microcontroller within a given operating mode (bits 8, 9, and 10). ah byte addressable (8-bit register names shown) loop/shift/repeat/count base registers code segment data segment stack segment extra segment processor status flags instruction pointer general registers status and control registers segment registers 15 0 15 0 7 0 7 0 15 0 cs flags ip 16-bit register name special register functions ds ss es ax dx cx bx bp si di sp dh ch bh al dl cl bl index registers stack pointer multiply/divide i/o instructions base pointer source index destination index 16-bit register name configuration basics am186?cc/ch/cu microcontrollers users manual 2-3 after the processor executes an instruction, the value of the flags can be set to 1, cleared or reset to 0, unchanged, or undefined. the term undefined means that the flag value prior to the execution of the instruction is not preserved, and that after the instruction is executed, the value of the flag cannot be predicted. figure 2-2 processor status flags register bits 15C12, reserved bit 11, overflow flag (of): set if the signed result cannot be expressed within the number of bits in the destination operand; otherwise cleared. bit 10, direction flag (df): when set, causes string instructions to auto-decrement the appropriate index registers. when cleared, causes auto-increment. bit 9, interrupt-enable flag (if): when set, enables maskable interrupts to cause the cpu to transfer control to a location specified by an interrupt vector. this flag is cleared when the processor takes a hardware interrupt, or a trace interrupt, by using the cli instruction. for more information about hardware and software interrupts, see chapter 7, interrupts. bit 8, trace flag (tf): when set, a trace interrupt occurs after instructions execute. tf is cleared by the trace interrupt after the processor status flags are pushed onto the stack. the trace service routine can continue tracing by popping the flags back with an interrupt return (iret) instruction. bit 7, sign flag (sf): set equal to high-order bit of result (0 if 0 or positive, 1 if negative). bit 6, zero flag (zf): set if result is 0; otherwise cleared. bit 5, reserved bit 4, auxiliary carry (af): set on carry from or borrow to the low-order four bits of the al general-purpose register; otherwise cleared. bit 3, reserved bit 2, parity flag (pf): set if low-order eight bits of result contain an even number of bits set to 1; otherwise cleared. bit 1, reserved bit 0, carry flag (cf): set on high-order bit carry or borrow; otherwise cleared. 15 70 if tf sf zf res cf pf reserved res af res of df configuration basics 2-4 am186?cc/ch/cu microcontrollers users manual 2.2.3 peripheral registers while the 186-legacy registers can be accessed directly through the 186 instructions, the peripheral registers must be accessed by using instruction operands that access memory or i/o space. the address of each 16-bit read/write peripheral register is in the internal 1-kbyte peripheral control block (pcb). registers physically reside in the peripheral devices they control, but they are addressed through the pcb. this block resides either in memory or i/o space, at the location pointed to by the peripheral control block relocation (reloc) register (see table 2-2). because the base address of the block can change, the address of each register is specified as an offset from the location pointed to by the reloc register, rather than as an absolute address. to determine the absolute address of the register in memory or i/o space, add the offset to the base address. for a discussion of memory versus i/o space, see memory organization and address generation on page 2-5. note: accesses to the pcb should be performed by direct processor actions. the use of dma to write or read from the pcb results in unpredictable behavior, except where explicit exception is made to support a peripheral function, such as the high-speed uart transmit and receive data registers. the pcb base address can be set to any even 1-kbyte boundary in memory or i/o space (i.e., the lower 10 bits of the base address must be 0). reloc resides in the last register address of the pcb, at offset 03feh. on an external or watchdog timer reset, the reloc register value is set to 20fch, which maps the pcb to start at fc00h in i/o space. this places the reloc register at fffeh. appendix a, register summary, provides a summary of pcb registers in offset order, including default address locations. for a complete description of the reloc register, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. a legacy feature on the am186cc/ch/cu microcontrollers allows logical word writes to the pcb registers to be performed as byte writes on the external bus. these writes transfer 16 bits of data to the pcb register even if an 8-bit register is named in the instruction. for example, out dx, al writes the value of ax to the port address in dx. reads to the pcb registers should always be done as word reads. this feature eliminates the need for an additional bus cycle when the same code is executed on an 8-bit am188 device or when the pcb overlaps an 8-bit address space. unaligned reads and writes to the pcb result in unpredictable behavior on the am186cc/ch/cu microcontrollers. internal logic recognizes control block addresses and responds to bus cycles. during bus cycles to internal registers, the bus controller signals the operation externally (i.e., the rd , wr , status, address, and data lines are driven as in a normal bus cycle), but the data bus, srdy, and ardy are ignored. table 2-3 lists the peripheral registers by functional groupings, along with the address offset where the group begins. for detailed information about the peripheral registers, refer to the am186?cc/ch/cu microcontrollers register set manual , order #21916. table 2-2 configuration register summary offset register mnemonic register name description 3feh reloc peripheral control block relocation allows software to relocate the peripheral control block to start at any even 1024-byte location in either memory or i/o space. configuration basics am186?cc/ch/cu microcontrollers users manual 2-5 2.3 memory organization and address generation memory is organized in sets of segments. each segment is a linear contiguous sequence of 64k (2 16 ) 8-bit bytes and must begin on a 16-byte boundary. memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. the offset is the number of bytes from the beginning of the segment (the segment address) to the data or instruction that is being accessed. this segment value and offset form the logical address, which is used by code. the processor forms the physical address of the target location by taking the segment address, shifting it to the left 4 bits (multiplying by 16), and adding the result to the 16-bit offset. the resulting sum is the 20-bit address of the target data or instruction. this technique allows for a 1-mbyte physical address size. table 2-3 peripheral register summary offset range functional block users manual chapter 1 notes: 1. for a list of registers with their bit field names and offset addresses, see appendix a, register summary. the am186?cc/ch/cu microcontrollers register set manual, order #21916, de- scribes these registers in detail. that manual presents the registers in order of offset, from lowest to highest. 000hC0f0h 2 2. reserved in the am186cu usb microcontroller. high-level data link control (hdlc) chapter 15 100hC13ch general-purpose dma chapter 8 140hC198h smartdma 1e0hC25eh 3 3. reserved in the am186ch hdlc microcontroller. universal serial bus (usb) chapter 18 260hC27ch high-speed asynchronous serial port (high-speed uart) chapter 13 280hC28eh asynchronous serial port (uart) 2a0hC2beh 4 4. reserved in the am186ch and am186cu microcontrollers. general circuit interface (gci) chapter 17 2c0hC2dch 2 time slot assigner (tsa) chapter 16 2f0hC2f8h synchronous serial interface (ssi) chapter 14 300hC338h interrupt controller chapter 7 340hC354h programmable timers chapter 10 3a0hC3a8h chip selects chapter 5 3aahC3ach dram chapter 6 3c0hC3dch programmable i/o (pio) chapter 9 3deh reset configuration chapter 3 3e0h watchdog timer chapter 11 3f0h system configuration chapter 3 3f4h processor release level 3feh relocation chapter 2 cc ch cc cu cc cc ch configuration basics 2-6 am186?cc/ch/cu microcontrollers users manual for example, if the segment register is loaded with 12a4h and the offset is 0022h, the resultant address is 12a62h, as illustrated in figure 2-3. to find the result: 1. the segment register contains 12a4h. 2. shift the segment register left 4 places to produce 12a40h. 3. the offset is 0022h. 4. add the shifted segment address (12a40h) to the offset (00022h). the result is 12a62h. 5. this address is placed on the pins of the microcontroller. all instructions that address operands in memory must specify (implicitly or explicitly) a 16-bit segment value and a 16-bit offset value. the 16-bit segment values are contained in one of the four internal segment registers (cs, ds, es, and ss). for more information about calculating the offset value, see addressing modes on page 2-9. for more information about cs, ds, es, and ss, see segments on page 2-7. in addition to 1 mbyte of memory space, the am186cc microcontroller provides 64k of i/o space (see figure 2-4). note that the processor reserves 00000h to 003ffh in memory for the interrupt vector table. figure 2-3 physical address generation 2.4 i/o space the i/o space consists of 64k 8-bit or 32k 16-bit ports. the in, ins, out, and outs instructions address the i/o space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the dx register. eight-bit port addresses are zero- extended so that a15Ca8 are low. note the processor reserves i/o port addresses 00f8h through 00ffh. the microcontroller provides specific instructions for addressing i/o space. 1 2 a 4 0 0 0 0 2 2 1 2 a 6 2 1 2 a 4 0 0 2 2 segment base logical address shift left 4 bits physical address to me m or y offset 0 15 15 15 19 19 0 0 0 0 configuration basics am186?cc/ch/cu microcontrollers users manual 2-7 figure 2-4 memory and i/o space 2.5 instruction set the instruction set for the am186cc/ch/cu microcontrollers is identical to the 80c186/188 instruction set. an instruction can reference from zero to several operands. an operand can reside in a register, in the instruction itself, or in memory. specific operand addressing modes are discussed on page 2-9. for instruction set details, see the am186 and am188 family instruction set manual , order #21267. 2.6 segments the microcontroller uses four segment registers: 1. data segment (ds): the processor assumes that all accesses to the programs variables are from the 64k space pointed to by the ds register. the data segment holds data, operands, and so on. 2. code segment (cs): this 64k space is the default location for all instructions. all code must be executed from the code segment. 3. stack segment (ss): the processor uses the ss register to perform operations that involve the stack, such as pushes and pops. the stack segment provides temporary storage space. 4. extra segment (es): typically, this segment supports large string operations and large data structures. certain string instructions assume the extra segment as the segment portion of the address. by using a segment override, the extra segment can also support a spare data segment. when a data movement instruction does not define a segment, the processor assumes a data segment. an instruction prefix can override the segment register. for speed and compact instruction encoding, the addressing mode implies the segment register used for physical address generation (see table 2-4). memory space 1 i/o space 2 1 mbyte 64 kbyte ffffh 0000h fffffh 00000h notes: 1. 00000hC003ffh are reserved for the interrupt vector table. 2. 00f8hC00ffh are reserved. configuration basics 2-8 am186?cc/ch/cu microcontrollers users manual 2.7 data types the am186cc/ch/cu microcontrollers directly support the following data types: n integer: a signed binary numeric value contained in an 8-bit byte or a 16-bit word. all operations assume a twos complement representation. n ordinal: an unsigned binary numeric value contained in an 8-bit byte or a 16-bit word. n double word: a signed binary numeric value contained in two sequential 16-bit addresses, or in a dx::ax register pair. n quad word: a signed binary numeric value contained in four sequential 16-bit addresses. n bcd: an unpacked byte representation of the decimal digits 0C9. n ascii: a byte representation of alphanumeric and control characters using the ascii standard of character representation. n packed bcd: a packed byte representation of two decimal digits (0C9). each nibble (four bits) of the byte contains one digit. n pointer: a 16-bit or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component in addition to a 16-bit offset component. n string: a contiguous sequence of bytes or words. a string can contain from 1 byte up to 64 kbytes. in general, individual data elements must fit within defined segment limits. figure 2-5 graphically represents the data types supported by the am186cc/ch/cu microcontrollers. table 2-4 segment register selection rules memory reference needed segment register used implicit segment selection rule local data data (ds) all data references instructions code (cs) instructions (including immediate data) stack stack (ss) all stack pushes and pops any memory references that use the bp register external data (global) extra (es) all string instruction references that use the di register as an index configuration basics am186?cc/ch/cu microcontrollers users manual 2-9 figure 2-5 supported data types 2.8 addressing modes the am186cc/ch/cu microcontrollers use eight categories of addressing modes to specify operands: two addressing modes for instructions that operate on register or immediate operands, and six modes that specify the location of an operand in a memory segment. 2.8.1 register and immediate operands n register operand mode: the operand is in one of the 8-bit or 16-bit registers. n immediate operand mode: the operand is constant data included in the instruction. 2.8.2 memory operands a memory-operand address consists of two 16-bit components: a segment value and an offset. the segment value is supplied by a 16-bit segment register either implicitly chosen by the addressing mode or explicitly chosen by a segment override prefix. the offset, also called the effective address , is calculated by summing any combination of the following three address elements: n displacement: an 8-bit or 16-bit immediate value contained in the instruction. n base: the contents of either the bx or bp base register. n index: the contents of either the si or di index register. any carry from the 16-bit addition is ignored. eight-bit displacements are sign-extended to 16-bit values. 7 0 signed byte magnitude magnitude 7 0 msb unsigned byte signed word magnitude msb +1 0 magnitude msb +3 +2 +1 0 signed quad word magnitude msb 63 48 47 32 31 16 15 0 unsigned word magnitude msb +1 0 7 0 7 0 7 0 +n +1 0 . . . 7 0 7 0 7 0 +n +1 0 . . . 7 0 7 0 7 0 +n +1 0 . . . binary coded decimal (bcd) bcd digit n bcd digit 1 bcd digit 0 ascii character n ascii character 1 ascii character 0 ascii most significant digit least significant digit packed bcd 7 0 7 0 +n +1 0 . . . byte/wordn byte/word1 byte/word0 string +3 +2 +1 0 segment base offset pointer 31 1615 0 0 15 +3 +2 +1 +6 +5 +4 +0 +7 15 14 8 7 0 70 signed double word sign bit sign bit sign bit sign bit configuration basics 2-10 am186?cc/ch/cu microcontrollers users manual combinations of the above three address elements define the following six memory addressing modes (see table 2-5 for examples). n direct mode: the instruction contains the operand offset as an 8-bit or 16-bit displacement element. n register indirect mode: the operand offset is in one of the following registers: si, di, bx, or bp. n based mode: the operand offset is the sum of an 8-bit or 16-bit displacement and the contents of a base register (bx or bp). n indexed mode: the operand offset is the sum of an 8-bit or 16-bit displacement and the contents of an index register (si or di). n based indexed mode: the operand offset is the sum of the contents of a base register and an index register. n based indexed mode with displacement: the operand offset is the sum of a base registers contents, an index registers contents, and an 8-bit or 16-bit displacement. table 2-5 memory addressing mode examples addressing mode example direct mov ax, ds:4 register indirect mov ax, [si] based mov ax, [bx]4 indexed mov ax, [si]4 based indexed mov ax, [si][bx] based indexed with displacement mov ax, [si][bx]4 am186?cc/ch/cu microcontrollers users manual 3-1 chapter 3 system overview 3.1 overview this chapter contains descriptions of the am 186cc/ch/cu microcontrollers system configuration registers, initialization and processor reset, signals, bus interface, and clock control. 3.2 system design table 3-1 shows the multiplexed signals and the trade-offs when selecting various functions. table 3-2 on page 3-3 shows the multiplexed signal information ordered by pio signal. table 3-1 multiplexed signal trade-offs desired function unavailable functions inter- face signal pin inter- face signal inter- face signal inter- face signal inter- face signal memory sram lcs 131 dram ras0 pio mcs1 127 cas1 mcs2 128 cas0 mcs3 129 ras1 pio5 dram cas0 128 sram mcs2 pio cas1 127 mcs1 ras0 131 lcs ras1 129 mcs3 pio5 synchronous communications interfaces dce channel a dce_rxd_a 118 pcm channel a pcm_rxd_a gci channel a gci_dd_a pio dce_txd_a 119 pcm_txd_a gci_du_a dce_rclk_a 117 pcm_clk_a gci_dcl_a dce_tclk_a 116 pcm_fsc_a gci_fsc_a dce_cts_a 123 pcm_tsc_a pio17 dce_rtr_a 122 pio18 dce channel b dce_rxd_b 138 pcm channel b pcm_rxd_b pio pio36 dce_txd_b 139 pcm_txd_b pio37 dce_rclk_b 135 pcm_clk_b pio40 dce_tclk_b 134 pcm_fsc_b pio41 dce_cts_b 137 pcm_tsc_b pio38 dce_rtr_b 136 pio39 dce channel c dce_rxd_c 153 pcm channel c pcm_rxd_c gci to pcm con- version pio pio42 dce_txd_c 154 pcm_txd_c pio43 dce_rclk_c 150 pcm_clk_c pcm_clk_c pio22 dce_tclk_c 149 pcm_fsc_c pcm_fsc_c pio23 dce_cts_c 152 pcm_tsc_c pio44 dce_rtr_c 151 pio45 cc ch cc ch cc cc ch cc ch cc cc cc system overview 3-2 am186?cc/ch/cu microcontrollers users manual dce channel d dce_rxd_d 158 pcm channel d pcm_rxd_d low- speed uart rxd_u high- speed uart (flow control) pio pio26 dce_txd_d 159 pcm_txd_d txd_u pio20 dce_rclk_d 156 pcm_clk_d rtr_u pio25 dce_tclk_d 157 pcm_fsc_d cts_u pio24 dce_cts_d 24 pcm_tsc_d cts_hu pio46 dce_rtr_d 23 rtr_hu pio47 pcm channel a pcm_rxd_a 118 dce channel a dce_rxd_a gci channel a gci_dd_a pio pcm_txd_a 119 dce_txd_a gci_du_a pcm_clk_a 117 dce_rclk_a gci_dcl_a pcm_fsc_a 116 dce_tclk_a gci_fsc_a pcm_tsc_a 123 dce_cts_a pio17 pcm channel b pcm_rxd_b 138 dce channel b dce_rxd_b pio pio36 pcm_txd_b 139 dce_txd_b pio37 pcm_clk_b 135 dce_rclk_b pio40 pcm_fsc_b 134 dce_tclk_b pio41 pcm_tsc_b 137 dce_cts_b pio38 pcm channel c pcm_rxd_c 153 dce channel c dce_rxd_c gci to pcm con- version pio pio42 pcm_txd_c 154 dce_txd_c pio43 pcm_clk_c 150 dce_rclk_c pcm_clk_c pio22 pcm_fsc_c 149 dce_tclk_c pcm_fsc_c pio23 pcm_tsc_c 152 dce_cts_c pio44 pcm channel d pcm_rxd_d 158 dce channel d dce_rxd_d low- speed uart rxd_u high- speed uart pio pio26 pcm_txd_d 159 dce_txd_d txd_u pio20 pcm_clk_d 156 dce_rclk_d rtr_u pio25 pcm_fsc_d 157 dce_tclk_d cts_u pio24 pcm_tsc_d 24 dce_cts_d cts_hu pio46 low- speed uart rxd_u 158 dce channel d dce_rxd_d pcm channel d pcm_rxd_d pio pio26 txd_u 159 dce_txd_d pcm_txd_d pio20 rtr_u 156 dce_rclk_d pcm_clk_d pio25 cts_u 157 dce_tclk_d pcm_fsc_d pio24 high- speed uart rxd_hu 25 dce channel d pcm channel d pio pio16 txd_hu 26 rtr_hu 23 dce_rtr_d pio47 cts_hu 24 dce_cts_d pcm_tsc_d pio46 gci channel a gci_dd_a 118 dce channel a dce_rxd_a pcm channel a pcm_rxd_a pio gci_du_a 119 dce_txd_a pcm_txd_a gci_dcl_a 117 dce_rclk_a pcm_clk_a gci_fsc_a 116 dce_tclk_a pcm_fsc_a gci to pcm con- version pcm_clk_c 150 dce channel c dce_rclk_c pcm channel c pcm_clk_c pio pio22 pcm_fsc_c 149 dce_tclk_c pcm_fsc_c pio23 table 3-1 multiplexed signal trade-offs (continued) desired function unavailable functions inter- face signal pin inter- face signal inter- face signal inter- face signal inter- face signal cc cc cc ch cc ch cc cc ch cc ch cc cc cc cc cc cc cc cc cc cc cc ch cc ch cc cc cc system overview am186?cc/ch/cu microcontrollers users manual 3-3 miscellaneous bus interfac e den 18 bus interfac e ds pio pio30 ds 18 den pio30 clocks uclk 22 clocks usbsof clocks usbsci pio pio21 usbsof 22 uclk usbsci pio21 usbsci 22 uclk usbsof pio21 table 3-2 multiplexed signal trade-offs ordered by pio desired function unavailable functions signal pin signal signal signal pio0 144 tmrin1 pio1 143 tmrout1 pio2 10 pcs5 pio3 9 pcs4 pio4 126 mcs0 pio5 129 mcs3 ras1 pio6 147 int8 pwd pio7 146 int7 pio8 14 ardy pio9 124 drq0 pio10 2 sden pio11 3 sclk pio12 4 sdata pio13 5 pcs0 pio14 6 pcs1 pio15 16 wr pio16 25 rxd_hu pio17 123 dce_cts_a pcm_tsc_a pio18 122 dce_rtr_a pio19 145 int6 pio20 159 txd_u dce_txd_d pcm_txd_d pio21 22 uclk usbsof usbsci pio22 150 dce_rclk_c pcm_clk_c pio23 149 dce_tclk_c pcm_fsc_c pio24 157 cts_u dce_tclk_d pcm_fsc_d pio25 156 rtr_u dce_rclk_d pcm_clk_d pio26 158 rxd_u dce_rxd_d pcm_rxd_d pio27 142 tmrin0 pio28 141 tmrout0 pio29 17 dt/r table 3-1 multiplexed signal trade-offs (continued) desired function unavailable functions inter- face signal pin inter- face signal inter- face signal inter- face signal inter- face signal cc cu cc cu cc cu cc cu cc cu cc cu cc ch cc ch cc ch cc cc cc cu cc cu cc cc cc cc cc cc cc cc cc cc system overview 3-4 am186?cc/ch/cu microcontrollers users manual 3.3 system configuration table 3-3 lists the registers used by the am186cc/ch/cu microcontrollers for system configuration. appendix a summarizes the bits in all of the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. when res is asserted, the reset configuration (rescon) register is set to the value found on ad15Cad0. there is a one-to-one correspondence between address/data bus signals and the rescon registers bits during reset (ad15 corresponds to bit 15 of the rescon register, and so on). when res is deasserted, the rescon register holds its value. software can read this value to determine the configuration information. for more information, see initialization and reset on page 3-5. pio30 18 den ds pio31 13 pcs7 pio32 11 pcs6 pio33 19 ale pio34 20 bhe pio35 15 srdy pio36 138 dce_rxd_b pcm_rxd_b pio37 139 dce_txd_b pcm_txd_b pio38 137 dce_cts_b pcm_tsc_b pio39 136 dce_rtr_b pio40 135 dce_rclk_b pcm_clk_b pio41 134 dce_tclk_b pcm_fsc_b pio42 153 dce_rxd_c pcm_rxd_c pio43 154 dce_txd_c pcm_txd_c pio44 152 dce_cts_c pcm_tsc_c pio45 151 dce_rtr_c pio46 24 cts_hu dce_cts_d pcm_tsc_d pio47 23 rtr_hu dce_rtr_d table 3-3 system configuration register summary offset register mnemonic register name description 3deh rescon reset configuration provides a way to make design-specific hardware configuration information available to software. 3f0h syscon system configuration contains system-wide configuration bits which affect the operation on a global basis. 3f4h prl processor revision level contains the specific release level of the processor. table 3-2 multiplexed signal trade-offs ordered by pio (continued) desired function unavailable functions signal pin signal signal signal cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc cc cc cc cc cc cc cc cc cc system overview am186?cc/ch/cu microcontrollers users manual 3-5 the system configuration (syscon) register is typically written once to establish the proper modes of operation based on the system in which the part is operating. this register performs the following functions: n enables the data strobe timings on the den pin. when the dsden bit (bit 13) is set to 1, data strobe bus mode is enabled, and the ds timing for reads and writes is identical to the normal read cycle den timing. when the dsden bit is cleared to 0, the den timing for both reads and writes is normal (i.e., like the original 80c186). the den pin is renamed ds in data strobe bus mode. for more information, see bus interface on page 3-28. n enables pulse width demodulation (pwd) mode. for more information about pwd mode, see chapter 10, programmable timers. n disables memory and i/o addresses on the ad15Cad0 bus. for more information, see bus interface on page 3-28. n configures hdlc channel c and d external interfaces. for more information, see chapter 15, high-level data link control (hdlc). n disables clkout and forces the pin to drive a zero externally. for more information, see clock control on page 3-32. the processor revision level (prl) register contains the processor revision level for the device. use this information when requesting support. 3.4 initialization and reset this document uses the following terms throughout: n external or power-on reset: a reset caused by asserting res . n internal reset: a reset initiated by the watchdog timer. n system reset: resets the microcontroller (the cpu plus the internal peripherals) as well as any external peripherals connected to resout. an external reset always causes a system reset; an internal reset can optionally cause a system reset. processor initialization or startup is accomplished by either an external reset or by an internal reset initiated by the watchdog timer. resets force the microcontroller to terminate all execution and local bus activity. no instruction or bus activity occurs as long as the processor is in reset. in all resets, the multiplexed pins default to the signal as shown in table 3-7 on page 3-10 (the signal name without brackets). pins are latched on the deassertion of res , and therefore are not affected by an internal watchdog-timer-generated reset. these latched pins include the reset configuration pins (pinstraps) shown in table 3-5 on page 3-7 and the rescon register inputs. after an external or internal reset has completed and an internal processing interval elapses, the microcontroller begins execution with the instruction at physical location ffff0h and the watchdog timer starts counting (reset enables the watchdog timer). res must be asserted for at least 1 ms during power-up to allow the internal circuits to stabilize. if the res signal is asserted while the watchdog timer is performing a watchdog timer reset, the external reset takes precedence. the am186cc/ch/cu microcontrollers also feature a reset out (resout) signal, which indicates that the microcontroller is being reset (either externally or internally) and can be used as a system reset to reset any external peripherals connected to resout. system overview 3-6 am186?cc/ch/cu microcontrollers users manual during an external reset, resout remains active (high) for two clocks after res is deasserted. the microcontroller exits reset and begins the first valid bus cycle approximately 4.5 clocks after res is deasserted. with an internal reset, the watchdog timer reset duration, and therefore the duration of the resout signal, is 2 16 processor clocks. this duration allows sufficient time for external devices to reach their reset state. for more information about internal resets, see chapter 11, watchdog timer. both external and internal resets set the registers to predefined values as shown in appendix a, register summary, with the exception of the rescon and wdtcon registers whose default values depend on the type of reset. the reset configuration (rescon) register latches system-configuration information that is presented to the processor on the address/data bus (ad15Cad0) at the deassertion of res . the interpretation of this information is system-specific. the processor does not impose any predetermined interpretation, but simply provides a means for communicating this information to software. when the res input is asserted, the contents of the ad bus are written into the rescon register. note that the rescon value is only sampled on an external reset. the system can place configuration information on the ad bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. the processor does not drive the ad bus during reset. for example, the rescon register could be used to provide the software with the position of a configuration switch in the system. by using weak external pullup and pulldown resistors on the ad bus, the system could provide the microcontroller with a value corresponding to the position of a jumper during reset. for compatibility with future devices, always write reserved bits in registers with their reset default values. the am186?cc/ch/cu microcontrollers register set manual , order #21916, defines the bits for all the registers. table 3-4 cpu and internal peripheral states immediately following power-on reset cpu/peripheral state am186 cpu enabled, executes at address ffff0h chip selects ucs active, all other chip selects inactive dram controller disabled interrupt controller disabledonly nonmaskable interrupts and traps can be taken general-purpose dma and smartdma channels disabled programmable i/os see chapter 9, programmable i/o signals programmable timers disabled watchdog timer enabled with maximum time-out value (2 16 clocks) uart and high-speed uart disabled synchronous serial interface (ssi) disabled high-level data link control (hdlc) channels disabled time slot assigners (tsas) disabled general circuit interface (gci) disabled universal serial bus (usb) peripheral controller disabled cc ch cc ch cc cc cu system overview am186?cc/ch/cu microcontrollers users manual 3-7 table 3-5 reset configuration pins (pinstraps) 1 notes: 1. a pinstrap is used to enable or disable features based on the state of the pin during an external reset. the pinstrap must b e held in its desired state for at least 4.5 clock cycles after the deassertion of res . the pinstraps are sampled in an external reset only (when res is asserted), not during an internal watchdog timer-generated reset. signal name multiplexed signal(s) description {aden} bhe pio34 address enable : if {aden} is held high or left floating during power-on reset, the address portion of the ad bus (ad15Cad0) is enabled or disabled during lcs , ucs , or other memory bus cycles based on how the software configures the da bit in the umcs or lmcs registers. in this case, the memory address is accessed on the a19C a0 pins. there is a weak internal pullup resistor on {aden} so no external pullup is required. this mode of operation reduces power consumption. if {aden } is held low on power-on reset, the ad bus drives both addresses and data, regardless of how software configures the da bit in the umcs or lmcs registers. {clksel1} {clksel2} hlda [pcs4] pio3 cpu pll mode select 1 determines the pll mode for the cpu clock source. cpu pll mode select 2 is sampled on the rising edge of reset and determines the pll mode for the cpu clock source. this pin has an internal pullup resistor that is active only during reset. there are four cpu pll modes that are selected by the values of {clksel1} and {clksel2} as shown below. {once } ucs once mode request asserted low places the am186cc/ch/cu microcontroller into once mode. otherwise, the controller operates normally. in once mode, all pins are three-stated and remain in that state until a subsequent reset occurs. to guarantee that the controller does not inadvertently enter once mode, {once } has a weak internal pullup resistor that is active only during a reset. a reset ending once mode should be as long as a power-on reset for the pll to stabilize. {ucsx8 } [mcs0] pio4 upper memory chip select, 8-bit bus asserted low configures the upper chip select region for an 8-bit bus size. this pin has a pullup resistor that is active only during reset, so no external pullup is required to set the bus to 16-bit mode. {usbsel2} {usbsel1} pcs1 pio14 pcs0 pio13 usb clock mode selects 1C2 select the usb pll operating mode. the pins have internal pullups that are active only during reset. the usb pll can operate in one of three modes. with a crystal and the internal usb oscillator or an external oscillator, the usb pll can output 4x or 2x the input frequency. the usb pll can also be disabled and the usb peripheral controller can receive its clock from the cpu pll, which is the default mode. the pins are encoded as shown below. {usbxcvr } s0 usb external transceiver enable asserted low disables the internal usb trans- ceiver and enables the pins needed to hook up an external transceiver. this pin has a pullup resistor that is active only during reset, so no external pullup is required as long as the user ensures that this input is not driven low during a power-on reset. cpu pll modes {clksel1} {clksel2} cpu pll mode 1 1 2x, cpu pll enabled (default) 1 0 4x, cpu pll enabled 0 1 1x, cpu pll enabled 00pll bypass cc cu cc cu usb pll modes {usbsel1} {usbsel2} usb pll mode 11 use cpu clock (after cpu pll mode select), usb pll disabled (default) 1 0 4x, usb pll enabled 0 1 2x, usb pll enabled 00reserved cc cu system overview 3-8 am186?cc/ch/cu microcontrollers users manual 3.5 signal descriptions table 3-7 contains a description of the am186cc/ch/cu microcontroller signals. table 3-6 describes the terms used in table 3-7. the signals are organized alphabetically within the following functional groups: n bus interface/general-purpose dma request (page 3-10) n clocks/reset/watchdog timer (page 3-14) n reserved (page 3-16) n power and ground (page 3-16) n debug support (page 3-17) n chip selects (page 3-17) n dram (page 3-19) n interrupts (page 3-19) n programmable i/o (pios) (page 3-21) n programmable timers (page 3-21) n asynchronous serial ports (uart and high-speed uart) (page 3-22) n synchronous serial interface (ssi) (page 3-23) n hdlc synchronous communications: channels aCd for data communications equipment (dce), pulse code modulation (pcm), and general circuit interface (gci) interfaces (page 3-23) n universal serial bus (usb) (page 3-27) for pinstraps refer to table 3-5 on page 3-7. system overview am186?cc/ch/cu microcontrollers users manual 3-9 table 3-6 signal descriptions table definitions term definition general terms [ ] indicates the pin alternate function; a pin defaults to the signal named without the brackets. { } indicates the reset configuration pin (pinstrap). pin refers to the physical wire. reset an external or power-on reset is caused by asserting res . an internal reset is initiated by the watchdog timer. a system reset is one that resets the microcontroller (the cpu plus the internal peripherals) as well as any external peripherals connected to resout. an external reset always causes a system reset; an internal reset can optionally cause a system reset. signal refers to the electrical signal that flows across a pin. signal a line over a signal name indicates that the signal is active low; a signal name without a line is active high. signal types b bidirectional hhigh ls programmable to hold last state of pin o totem pole output od open drain output od-o open drain output or totem pole output pd internal pulldown resistor pu internal pullup resistor sti schmitt trigger input sti-od schmitt trigger input or open drain output ts three-state output system overview 3-10 am186?cc/ch/cu microcontrollers users manual table 3-7 signal descriptions signal name 1 multiplexed signal(s) type description bus interface/general-purpose dma request a19Ca0 o address bus supplies nonmultiplexed memory or i/o addresses to the system one half of a clkout period earlier than the multiplexed address and data bus (ad15Cad0). during bus-hold or reset conditions, the address bus is three-stated with pulldowns. when the lower or upper chip-select regions are configured for dram mode, the a19Ca0 bus provides the row and column addresses at the appropriate times. the upper and lower memory chip-select ranges can be individually configured for dram mode. ad15Cad0 b address and data bus time-multiplexed pins supply memory or i/o addresses and data to the system. this bus can supply an address to the system during the first period of a bus cycle (t 1 ). it transmits (write cycle) or receives (read cycle) data to or from the system during the remaining periods of that cycle (t2, t3, and t4). the address phase of these pins can be disabled see the {aden } pin description in table 3-5 on page 3-7. during a reset condition, the address and data bus is three- stated with pulldowns, and during a bus hold it is three-stated. in addition, during a reset the state of the address and data bus pins (ad15Cad0) is latched into the reset configuration (rescon) register. this feature can be used to provide software with information about the external system at reset time. ale [pio33] o address latch enable indicates to the system that an address appears on the address and data bus (ad15Cad0). the address is guaranteed valid on the falling edge of ale. ale is three-stated and has a pulldown resistor during bus-hold or reset conditions. ardy [pio8] sti asynchronous ready is a true asynchronous ready that indicates to the microcontroller that the addressed memory space or i/o device will complete a data transfer. the ardy pin is asynchronous to clkout and is active high. to guarantee the number of wait states inserted, ardy or srdy must be synchronized to clkout. if the falling edge of ardy is not synchronized to clkout as specified, an additional clock period can be added. to always assert the ready condition to the microcontroller, tie ardy and srdy high. if the system does not use ardy, tie the pin low to yield control to srdy. system overview am186?cc/ch/cu microcontrollers users manual 3-11 bhe [pio34] {aden } o bus high enable: during a memory access, bhe and the least- significant address bit (ad0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. the bhe and ad0 pins are encoded as follows: bhe is asserted during t 1 and remains asserted through t 3 and t w . bhe does not require latching. bhe is three-stated with a pullup during bus-hold and reset conditions. wlb and whb implement the functionality of bhe and ad0 for high and low byte write enables, and they have timing appropriate for use with the nonmultiplexed bus interface. bhe also signals dram refresh cycles when using the multiplexed address and data (ad) bus. a refresh cycle is indicated when both bhe and ad0 are high. during refresh cycles, the ad bus is driven during the t 1 phase and three-stated during the t 2 , t 3 , and t 4 phases. the value driven on the a bus is undefined during a refresh cycle. for this reason, the a0 signal cannot be used in place of the ad0 signal to determine refresh cycles. bsize8 o bus size 8 is asserted during t 1 Ct 4 to indicate an 8-bit cycle, or is deasserted to indicate a 16-bit cycle. den [ds ] [pio30] o data enable supplies an output enable to an external data-bus transceiver. den is asserted during memory and i/o cycles. den is deasserted when dt/r changes state. den is three- stated with a pullup during bus-hold or reset conditions. [drq0] drq1 pio9 sti sti dma requests 0 and 1 indicate to the microcontroller that an external device is ready for a dma channel to perform a transfer. drq1C[drq0] are level-triggered and internally synchronized. drq1C[drq0] are not latched and must remain active until serviced. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description data byte encoding bhe ad0 type of bus cycle 0 0 word transfer 01 high byte transfer (bits 15C8) 10 low byte transfer (bits 7C0) 11refresh system overview 3-12 am186?cc/ch/cu microcontrollers users manual [ds ] den [pio30] o data strobe provides a signal where the write cycle timing is identical to the read cycle timing. when used with other control signals, [ds ] provides an interface for 68k-type peripherals without the need for additional system interface logic. when [ds ] is asserted, addresses are valid. when [ds ] is asserted on writes, data is valid. when [ds ] is asserted on reads, data can be driven on the ad bus. following a reset, this pin is configured as den . the pin is then configured by software to operate as [ds ]. dt/r [pio29] o data transmit or receive indicates which direction data should flow through an external data-bus transceiver. when dt/r is asserted high, the microcontroller transmits data. when this pin is deasserted low, the microcontroller receives data. dt/r is three-stated with a pullup during a bus-hold or reset condition. hlda {clksel1} o bus-hold acknowledge is asserted to indicate to an external bus master that the microcontroller has relinquished control of the local bus. when an external bus master requests control of the local bus (by asserting hold), the microcontroller completes the bus cycle in progress, then relinquishes control of the bus to the external bus master by asserting hlda and three-stating a19Ca0, ad15Cad0, s 2 Cs 0 , and s6. the following are also three-stated and have pullups: bhe , den , dt/r , lcs , mcs 3 C mcs 0 , pcs 7 Cpcs 0 , rd , ucs , whb , wlb , and wr . ale is three-stated and has a pulldown. when the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting hold. the microcontroller responds by deasserting hlda. if the microcontroller requires access to the bus (for example, for refresh), the microcontroller deasserts hlda before the external bus master deasserts hold. the external bus master must be able to deassert hold and allow the microcontroller access to the bus. see the timing diagrams for bus hold in the microcontroller data sheet. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description system overview am186?cc/ch/cu microcontrollers users manual 3-13 hold sti bus-hold request indicates to the microcontroller that an external bus master needs control of the local bus. the microcontroller hold latency timethe time between hold request and hold acknowledgeis a function of the activity occurring in the processor when the hold request is received. a hold request is second only to dram refresh requests in priority of activity requests received by the processor. this implies that if a hold request is received just as a dma transfer begins, the hold latency can be as great as four bus cycles. this occurs if a dma word transfer operation is taking place from an odd address to an odd address. this is a total of 16 clock cycles or more if wait states are required. in addition, if locked transfers are performed, the hold latency time is increased by the length of the locked transfer. hold latency is also potentially increased by dram refreshes. the board designer is responsible for properly terminating the hold input. for more information, see the hlda pin description above. rd o read strobe indicates to the system that the microcontroller is performing a memory or i/o read cycle. rd is guaranteed not to be asserted before the address and data bus is three-stated during the address-to-data transition. rd is three-stated with a pullup during bus-hold or reset conditions. s2 s1 s0 {usbxcvr } o bus cycle status 2C0 indicate to the system the type of bus cycle in progress. s 2 can be used as a logical memory or i/o indicator, and s 1 can be used as a data transmit or receive indicator. s 2 Cs 0 are three-stated during bus hold and three- stated with a pullup during reset. the s 2 Cs 0 pins are encoded as follows: s6 o bus cycle status bit 6: this signal is asserted during t 1 Ct 4 to indicate a dma-initiated bus cycle or a refresh cycle. s6 is three- stated during bus hold and three-stated with a pulldown during reset. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description bus status pins s2 s1 s0 bus cycle 0 0 0 reserved 0 0 1 read data from i/o 0 1 0 write data to i/o 011halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 none (passive) system overview 3-14 am186?cc/ch/cu microcontrollers users manual srdy [pio35] sti synchronous ready indicates to the microcontroller that the addressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active high input synchronized to clkout. using srdy instead of ardy allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ardy. to always assert the ready condition to the microcontroller, tie srdy high. if the system does not use srdy, tie the pin low to yield control to ardy. whb wlb o o write high byte and write low byte indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 microcontroller designs, this information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are eliminated. whb is asserted with ad15Cad8. whb is the logical and of bhe and wr . this pin is three-stated with a pullup during bus- hold or reset conditions. wlb is asserted with ad7Cad0. wlb is the logical and of ad0 and wr . this pin is three-stated with a pullup during bus-hold or reset conditions. wr [pio15] o write strobe indicates to the system that the data on the bus is to be written to a memory or i/o device. wr is three-stated with a pullup during bus-hold or reset conditions. clocks/reset/watchdog timer clkout o clock output supplies the clock to the system. depending on the values of the cpu mode select pinstraps, {clksel1} and {clksel2}, clkout operates at either the pll frequency or the source input frequency during pll bypass mode. (see table 3-5 on page 3-7.) clkout remains active during bus-hold or reset conditions. the disclk bit in the syscon register can be set to disable the clkout signal. refer to the am186?cc/ch/cu microcontrollers register set manual , order #21916. all synchronous ac timing specifications not associated with ssi, hdlcs, uarts, and the usb are synchronous to clkout. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description system overview am186?cc/ch/cu microcontrollers users manual 3-15 res sti reset requires the microcontroller to perform a reset. when res is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and on the deassertion of res , transfers cpu control to the reset address ffff0h. res must be asserted for at least 1 ms to allow the internal circuits to stabilize. res can be asserted asynchronously to clkout because res is synchronized internally. for proper initialization, v cc must be within specifications, and clkout must be stable for more than four clkout periods during which res is asserted. if res is asserted while the watchdog timer is performing a watchdog-timer reset, the external reset takes precedence over the watchdog-timer reset. this means that the resout signal asserts as with any external reset and the wdtcon register will not have the rstflag bit set. in addition, the microcontroller will exit reset based on the external reset timing, i.e., 4.5 clocks after the deassertion of res rather than 2 16 clocks after the watchdog timer timeout occurred. the microcontroller begins fetching instructions approximately 6.5 clkout periods after res is deasserted. this input is provided with a schmitt trigger to facilitate power-on res generation via a resistor-capacitor (rc) network. resout o reset out indicates that the microcontroller is being reset (either externally or internally), and the signal can be used as a system reset to reset any external peripherals connected to resout. during an external reset, resout remains active (high) for two clocks after res is deasserted. the microcontroller exits reset and begins the first valid bus cycle approximately 4.5 clocks after res is deasserted. [uclk] [usbsof] [usbsci] pio21 sti uart clock can be used instead of the processor clock as the source clock for either the uart or the high-speed uart. the source clock for the uart and the high-speed uart are selected independently and both can use the same source. usbx1 usbx2 sti o usb controller crystal input (usbx1) and usb controller crystal output (usbx2) provide connections for a fundamental mode, parallel-resonant crystal used by the internal usb oscillator circuit. if the cpu crystal is used to generate the usb clock, usbx1 must be pulled down. x1 x2 o sti cpu crystal input (x1) and cpu crystal output (x2) provide connections for a fundamental mode, parallel-resonant crystal used by the internal oscillator circuit. if an external oscillator is used, inject the signal directly into x1 and leave x2 floating. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description cc cu cc cu system overview 3-16 am186?cc/ch/cu microcontrollers users manual pinstraps (see table 3-5 on page 3-7 .) reserved rsvd_75 on the am186ch hdlc microcontroller, the rsvd_75 pin should be tied externally to v ss . on the am186ch hdlc microcontroller, pins rsvd_75, rsvd_76, rsvd_80, rsvd_81, and rsvd_101Crsvd_104 and are reserved. on the am186cc and am186cu microcontrollers, pins rsvd_101Crsvd_104 are reserved unless pinstrap {usbxcvr } is sampled low on the rising edge of reset. on the am186cu usb microcontroller, pins rsvd_119C rsvd_116 are reserved. all other reserved pins should not be connected. rsvd_76 rsvd_80 rsvd_81 rsvd_101 utxdpls rsvd_102 utxdmns rsvd_103 uxvoe rsvd_104 uxvrcv rsvd_116 rsvd_117 rsvd_118 rsvd_119 power and ground v cc (15) (16) sti digital power supply pins supply power (+3.3 0.3 v) to the microcontroller logic. v cc _a (1) sti analog power supply pin supplies power (+3.3 0.3 v) to the oscillators and plls. v cc _usb (1) sti usb power supply pin supplies power (+3.3 0.3 v) to the usb block. v ss (15) (16) sti digital ground pins connect the microcontroller logic to the system ground. v ss _a (1) sti analog ground pin connects the oscillators and plls to the system ground. v ss _usb (1) sti usb ground pin connects the usb block to the system ground. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description ch ch ch ch cu cu cu cu cc cu ch cc cu cc cu ch cc cu system overview am186?cc/ch/cu microcontrollers users manual 3-17 debug support qs1Cqs0 o queue status 1C0 values provide information to the system concerning the interaction of the cpu and the instruction queue. the pins have the following meanings: the following signals are also used by emulators: a19Ca0, ad15Cad0, {aden }, ale, ardy, bhe , bsize8 , cas1 C cas0 , clkout, {clksel2 }C{clksel1 }, hlda, hold, lcs , mcs3 Cmcs0 , nmi, {once }, qs1Cqs0, ras1 C ras0 , rd , res , resout, s2 Cs0 , s6, srdy, ucs , {ucsx8 }, whb , wlb , wr . for more information, see chapter 4, emulator support. chip selects lcs [ras0 ]o lower memory chip select indicates to the system that a memory access is in progress to the lower memory block. the base address and size of the lower memory block are programmable up to 512 kbyte. lcs can be configured for 8-bit or 16-bit bus size. lcs is three-stated with a pullup resistor during bus-hold or reset conditions. [mcs0 ] mcs1 mcs2 [mcs3 ] {ucsx8 } pio4 [cas1 ] [cas0 ] [ras1 ] pio5 o midrange memory chip selects 0C3 indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. the midrange chip selects can be configured for 8-bit or 16-bit bus size. the midrange chip selects are three-stated with pullup resistors during bus-hold or reset conditions. [mcs0 ] can be programmed as the chip select for the entire middle chip select address range. unlike the ucs and lcs chip selects that operate relative to the earlier timing of the nonmultiplexed a address bus, the mcs outputs assert with the multiplexed ad address and data bus timing. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description queue status pins qs1 qs0 queue operation 0 0 none 01 first opcode byte fetched from queue 1 0 queue was initialized 11 subsequent byte fetched from queue system overview 3-18 am186?cc/ch/cu microcontrollers users manual pcs0 [pio13] {usbsel1} o peripheral chip selects 0C7 indicate to the system that an access is in progress to the corresponding region of the peripheral address block (either i/o or memory address space). the base address of the peripheral address block is programmable. pcs7 Cpcs0 are three-stated with pullup resistors during bus-hold or reset conditions. unlike the ucs and lcs chip selects that operate relative to the earlier timing of the nonmultiplexed a address bus, the pcs outputs assert with the multiplexed ad address and data bus timing. pcs1 [pio14] {usbsel2} pcs2 pcs3 [pcs4 ]pio3 [clksel2] [pcs5 ]pio2 [pcs6 ]pio32 [pcs7 ]pio31 ucs {once }o upper memory chip select indicates to the system that a memory access is in progress to the upper memory block. the base address and size of the upper memory block are programmable up to 512 kbytes. ucs is three-stated with a weak pullup during bus-hold or reset conditions. the ucs can be configured for an 8-bit or 16-bit bus size out of reset. for additional information, see the {ucsx8 } pin description in table 3-5 on page 3-7. after reset, ucs is active for the 64-kbyte memory range from f0000h to fffffh, including the reset address of ffff0h. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description system overview am186?cc/ch/cu microcontrollers users manual 3-19 dram [cas0 ] [cas1 ] mcs2 mcs1 o column address strobes 0C1 : when either the upper or lower chip select regions are configured for dram, these pins provide the column address strobe signals to the dram. the cas signals can be used to perform byte writes in a manner similar to wlb and whb , respectively, i.e., [cas0 ] corresponds to the low byte (wlb ) and [cas1 ] corresponds to the high byte (whb ). [ras0 ]lcs o row address strobe 0 : when the lower chip select region is configured to dram, this pin provides the row address strobe signal to the lower dram bank. [ras1 ] [mcs3 ] pio5 o row address strobe 1 : when the upper chip select region is configured to dram, this pin provides the row address strobe signal to the upper dram bank. interrupts int5Cint0 sti maskable interrupt requests 0C8 indicate to the microcontroller that an external interrupt request has occurred. if the individual pin is not masked, the microcontroller transfers program execution to the location specified by the associated interrupt vector in the microcontrollers interrupt vector table. interrupt requests are synchronized internally and can be edge- triggered or level-triggered. the interrupt polarity is programmable.to guarantee interrupt recognition for edge- triggered interrupts, the user should hold the interrupt source for a minimum of five system clocks. a second interrupt from the same source is not recognized until after an acknowledge of the first. the board designer is responsible for properly terminating the int8Cint0 inputs. [int6] pio19 [int7] pio7 [int8] [pwd] pio6 table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description system overview 3-20 am186?cc/ch/cu microcontrollers users manual nmi sti nonmaskable interrupt indicates to the microcontroller that an interrupt request has occurred. the nmi signal is the highest priority hardware interrupt and cannot be masked. the microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontrollers interrupt vector table when nmi is asserted. although nmi is the highest priority hardware interrupt source, it does not participate in the priority resolution process of the maskable interrupts. there is no bit associated with nmi in the interrupt in-service or interrupt request registers. this means that a new nmi request can interrupt an executing nmi interrupt service routine. as with all hardware interrupts, the interrupt flag (if) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. however, if maskable interrupts are re-enabled by software in the nmi interrupt service routine (for example, via the sti instruction), the fact that an nmi is currently in service does not have any effect on the priority resolution of maskable interrupt requests. for this reason, it is strongly advised that the interrupt service routine for nmi should not enable the maskable interrupts. an nmi transition from low to high is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. to guarantee that the interrupt is recognized, the nmi pin must be asserted for at least one clkout period. the board designer is responsible for properly terminating the nmi input. also configurable as interrupts are pio5, pio15, pio27, pio29, pio30, pio33, pio34, and pio35. for more information, see chapter 9, programmable i/o signals. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description system overview am186?cc/ch/cu microcontrollers users manual 3-21 programmable i/o (pios) pio47Cpio0 (for a list of the multiplexed signals ordered by pio number, see table 3-2.) b shared programmable i/o pins can be programmed with the following attributes: pio function (enabled/disabled), direction (input/output), and weak pullup or pulldown. after a reset, the pio pins default to various configurations. most of the pio pins are configured as pio inputs with pullup after reset. the system initialization code must reconfigure any pio pins as required. pio5, pio15, pio27, pio29, pio30, and pio33Cpio35 are capable of generating an interrupt on the shared interrupt channel 14. the multiplexed signals pio8/ardy, pio13/pcs0 , pio14/pcs1 , pio15/wr , pio29/dt/r , pio30/den , pio33/ale, pio34/bhe , and pio35/srdy default to non-pio operation at reset. the following pio signals are multiplexed with alternate signals that can be used by emulators: pio8, pio15, pio33, pio34, and pio35. consider any emulator requirements for the alternate signals before using these pins as pios. programmable timers [pwd] [int8] pio6 sti pulse-width demodulator: if pulse-width demodulation is enabled, [pwd] processes a signal through the schmitt trigger input. [pwd] is used internally to drive [tmrin0] and [int8], and [pwd] is inverted internally to drive [tmrin1] and an additional internal interrupt. if interrupts are enabled and timer 0 and timer 1 are properly configured, the pulse width of the alternating [pwd] signal can be calculated by comparing the values in timer 0 and timer 1. in pwd mode, the signals [tmrin0]/pio27 and [tmrin1]/pio0 can be used as pios. if they are not used as pios they are ignored internally. the additional internal interrupt used in pwd mode uses the same interrupt channel as [int7]. if [int7] is used, it must be assigned to the shared interrupt channel. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description system overview 3-22 am186?cc/ch/cu microcontrollers users manual [tmrin0] [tmrin1] pio27 pio0 sti sti timer inputs 0C1 supply a clock or control signal to the internal microcontroller timers. after internally synchronizing a low-to- high transition on [tmrin1]C[tmrin0], the microcontroller increments the timer. [tmrin1]C[tmrin0] must be tied high if not being used. when pio is enabled for one or both, the pin is pulled high internally. [tmrin1]C[tmrin0] are driven internally by [int8]/[pwd] when pulse-width demodulation functionality is enabled. the [tmrin1]C[tmrin0] pins can be used as pios when pulse- width demodulation is enabled. [tmrout0] [tmrout1] pio28 pio1 o o timer outputs 0C1 supply the system with either a single pulse or a continuous waveform with a programmable duty cycle. [tmrout1]C[tmrout0] are three-stated during bus-hold or reset conditions. asynchronous serial ports (uart and high-speed uart) uart [rxd_u] dce_rxd_d [pcm_rxd_d] pio26 sti receive data uart is the asynchronous serial receive data signal that supplies data from the asynchronous serial port to the microcontroller. [txd_u] [dce_txd_d] [pcm_txd_d] pio20 o transmit data uart is the asynchronous serial transmit data signal that supplies data to the asynchronous serial port from the microcontroller. [cts_u ] [dce_tclk_d] [pcm_fsc_d] pio24 sti clear-to-send uart provides the clear-to-send signal from the asynchronous serial port when hardware flow control is enabled for the port. the [cts_u ] signal gates the transmission of data from the serial port transmit shift register. when [cts_u ] is asserted, the transmitter begins transmission of a frame of data, if any is available. if [cts_u ] is deasserted, the transmitter holds the data in the serial port transmit shift register. the value of [cts_u ] is checked only at the beginning of the transmission of the frame. [cts_u ] and [rtr_u ] form the hardware handshaking interface for the uart. [rtr_u ] dce_rclk_d [pcm_clk_d] pio25 o ready-to-receive uart provides the ready-to-receive signal for the asynchronous serial port when hardware flow control is enabled for the port. the [rtr_u ] signal is asserted when the associated serial port receive data register does not contain valid, unread data. [cts_u ] and [rtr_u ] form the hardware handshaking interface for the uart. high-speed uart [rxd_hu] pio16 sti receive data high-speed uart is the asynchronous serial receive data signal that supplies data from the high-speed serial port to the microcontroller. txd_hu o transmit data high-speed uart is the asynchronous serial transmit data signal that supplies data to the high-speed serial port from the microcontroller. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description system overview am186?cc/ch/cu microcontrollers users manual 3-23 [cts_hu ] [dce_cts_d ] [pcm_tsc_d ] pio46 sti clear-to-send high-speed uart provides the clear-to-send signal from the high-speed asynchronous serial port when hardware flow control is enabled for the port. the [cts_hu ] signal gates the transmission of data from the serial port transmit shift register. when [cts_hu ] is asserted, the transmitter begins transmission of a frame of data, if any is available. if [cts_hu ] is deasserted, the transmitter holds the data in the serial port transmit shift register. the value of [cts_hu ] is checked only at the beginning of the transmission of the frame. [cts_hu ] and [rtr_hu ] form the hardware handshaking interface for the high-speed uart. [rtr_hu ] [dce_rtr_d ] pio47 o ready-to-receive high-speed uart provides the ready-to- receive signal to the high-speed asynchronous serial port when hardware flow control is enabled for the port. the [rtr_hu ] signal is asserted when the associated serial port receive data register does not contain valid, unread data. [cts_hu ] and [rtr_hu ] form the hardware handshaking interface for the high-speed uart. synchronous serial interface (ssi) [sclk] pio11 o serial clock provides the clock for the synchronous serial interface to allow synchronous transfers between the microcontroller and a slave device. [sdata] pio12 b serial data is used to transmit and receive data between the microcontroller and a slave device on the synchronous serial interface. [sden] pio10 o serial data enable enables data transfers on the synchronous serial interface. high-level data link control synchronous communication interfaces hdlc channel a (dce) dce_rxd_a [gci_dd_a] [pcm_rxd_a] sti dce receive data channel a is the serial data input pin for the channel a dce interface. dce_txd_a [gci_du_a] [pcm_txd_a] od- o dce transmit data channel a is the serial data output pin for the channel a dce interface. dce_rclk_a [gci_dcl_a] [pcm_clk_a] sti dce receive clock channel a provides the receive clock to the channel a dce interface. if the same clock is to be used for both transmit and receive, then this pin should be tied to the dce_tclk_a pin externally. the dce function is the default at reset, so the board designer is responsible for properly terminating the dce_rclk_a input. dce_tclk_a [gci_fsc_a] [pcm_fsc_a] sti dce transmit clock channel a provides the transmit clock to the channel a dce interface. if the same clock is to be used for both transmit and receive, then this pin should be tied to the dce_rclk_a pin externally. the dce function is the default at reset, so the board designer is responsible for properly terminating the dce_tclk_a input. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description cc ch cc ch cc ch cc ch cc ch system overview 3-24 am186?cc/ch/cu microcontrollers users manual [dce_cts_a ] [pcm_tsc_a ] pio17 sti dce clear-to-send channel a indicates to the channel a dce interface that an external serial interface is ready to receive data. [dce_cts_a ] and [dce_rtr_a ] provide the handshaking for the channel a dce interface. [dce_rtr_a ] pio18 o dce ready-to-receive channel a indicates to an external serial interface that the internal channel a dce interface is ready to accept data. [dce_cts_a ] and [dce_rtr_a ] provide the handshaking for the channel a dce interface. hdlc channel b (dce) [dce_rxd_b] [pcm_rxd_b] pio36 sti dce receive data channel b is the serial data input pin for the channel b dce interface. [dce_txd_b] [pcm_txd_b] pio37 od- o dce transmit data channel b is the serial data output pin for the channel b dce interface. [dce_rclk_b] [pcm_clk_b] pio40 sti dce receive clock channel b provides the receive clock to the channel b dce interface. if the same clock is to be used for both transmit and receive, this pin should be tied to the [dce_tclk_b] pin externally. [dce_tclk_b] [pcm_fsc_b] pio41 sti dce transmit clock channel b provides the transmit clock to the channel b dce interface. if the same clock is to be used for both transmit and receive, this pin should be tied to the [dce_rclk_b] pin externally. [dce_cts_b ] [pcm_tsc_b ] pio38 sti dce clear-to-send channel b indicates to the channel b dce interface that an external serial interface is ready to receive data. [dce_cts_b ] and [dce_rtr_b ] provide the handshaking for the channel b dce interface. [dce_rtr_b ] pio39 o dce ready-to-receive channel b indicates to an external serial interface that the internal channel b dce interface is ready to accept data. [dce_cts_b ] and [dce_rtr_b ] provide the handshaking for the channel b dce interface. hdlc channel c (dce) [dce_rxd_c] [pcm_rxd_c] pio42 sti dce receive data channel c is the serial data input pin for the channel c dce interface. [dce_txd_c] [pcm_txd_c] pio43 od- o dce transmit data channel c is the serial data output pin for the channel c dce interface. [dce_rclk_c] [pcm_clk_c] pio22 sti dce receive clock channel c provides the receive clock to the channel c dce interface. if the same clock is to be used for both transmit and receive, this pin should be tied to the [dce_tclk_c] pin externally. [dce_tclk_c] [pcm_fsc_c] pio23 sti dce transmit clock channel c provides the transmit clock to the channel c dce interface. if the same clock is to be used for both transmit and receive, this pin should be tied to the [dce_rclk_c] pin externally. [dce_cts_c ] [pcm_tsc_c ] pio44 sti dce clear-to-send channel c indicates to the channel c dce interface that an external serial interface is ready to receive data. [dce_cts_c ] and [dce_rtr_c ] provide the handshaking for the channel c dce interface. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc cc cc cc cc cc system overview am186?cc/ch/cu microcontrollers users manual 3-25 [dce_rtr_c ] pio45 o dce ready-to-receive channel c indicates to an external serial interface that the internal channel c dce is ready to accept data. [dce_cts_c ] and [dce_rtr_c ] provide the handshaking for the channel c dce interface. hdlc channel d (dce) dce_rxd_d [rxd_u] (uart) [pcm_rxd_d] pio26 sti dce receive data channel d is the serial data input pin for the channel d dce interface. [dce_txd_d] [txd_u] (uart) [pcm_txd_d] pio20 od- o dce transmit data channel d is the serial data output pin for the channel d dce interface. dce_rclk_d [rtr_u ] (uart) [pcm_clk_d] pio25 sti dce receive clock channel d provides the receive clock to the channel d dce interface. if the same clock is to be used for both transmit and receive, then this pin should be tied to the [dce_tclk_d] pin externally. [dce_tclk_d] [cts_u ] (uart) [pcm_fsc_d] pio24 sti dce transmit clock channel d provides the transmit clock to the channel d dce interface. if the same clock is to be used for both transmit and receive, then this pin should be tied to the dce_rclk_d pin externally. [dce_cts_d ] [cts_hu ] (high- speed uart) [pcm_tsc_d ] pio46 sti dce clear-to-send channel d indicates to the channel d dce interface that an external serial interface is ready to receive data. [dce_cts_d ] and [dce_rtr_d ] provide the handshaking for dce channel d. [dce_rtr_d ] [rtr_hu ] (high- speed uart) pio47 o dce ready-to-receive channel d indicates to an external serial interface that the internal channel d dce interface is ready to accept data. [dce_cts_d ] and [dce_rtr_d ] provide the handshaking for the channel d dce interface. hdlc channel a (pcm) [pcm_rxd_a] dce_rxd_a [gci_dd_a] sti pcm receive data channel a is the serial data input pin for the channel a pcm highway interface. [pcm_txd_a] dce_txd_a [gci_du_a] o- ls- od pcm transmit data channel a is the serial data output pin for the channel a pcm highway interface. [pcm_clk_a] dce_rclk_a [gci_dcl_a] sti pcm clock is the single transmit and receive data clock pin for the channel a pcm highway interface. [pcm_fsc_a] dce_tclk_a [gci_fsc_a] sti pcm frame synchronization clock provides the frame synchronization clock input (usually 8 khz) for the channel a pcm highway interface. [pcm_tsc_a ] [dce_cts_a ] pio17 od pcm time slot control a enables an external buffer device when channel a pcm highway data is present on the [pcm_txd_a] output pin in pcm highway mode. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description cc cc cc cc cc cc cc cc cc ch cc ch cc ch cc ch cc ch cc ch system overview 3-26 am186?cc/ch/cu microcontrollers users manual hdlc channel b (pcm) [pcm_rxd_b] [dce_rxd_b] pio36 sti pcm receive data channel b is the serial data input pin for the channel b pcm highway interface. [pcm_txd_b] [dce_txd_b] pio37 o- ls- od pcm transmit data channel b is the serial data output pin for the channel b pcm highway interface. [pcm_clk_b] [dce_rclk_b] pio40 sti pcm clock is the single transmit and receive data clock pin for the channel b pcm highway interface. [pcm_fsc_b] [dce_tclk_b] pio41 sti pcm frame synchronization clock provides the frame synchronization clock input (usually 8 khz) for the channel b pcm highway interface. [pcm_tsc_b ] [dce_cts_b ] pio38 od pcm time slot control b enables an external buffer device when channel b pcm highway data is present on the [pcm_txd_b] output pin in pcm highway mode. hdlc channel c (pcm) [pcm_rxd_c] [dce_rxd_c] pio42 sti pcm receive data channel c is the serial data input pin for the channel c pcm highway interface. [pcm_txd_c] [dce_txd_c] pio43 o- ls- od pcm transmit data channel c is the serial data output pin for the channel c pcm highway interface. [pcm_clk_c] [dce_rclk_c] pio22 b pcm clock: for pcm highway operation, [pcm_clk_c] is the single transmit and receive data clock input pin for the channel c pcm highway interface. [pcm_clk_c] becomes a clock source output when the gci to pcm highway clock and frame synchronization conversion are enabled. [pcm_fsc_c] [dce_tclk_c] pio23 b pcm frame synchronization clock: for pcm highway operation, [pcm_fsc_c] provides the frame synchronization clock input (usually 8 khz) for the channel c pcm highway interface. [pcm_fsc_c] becomes a frame synchronization source output when the gci to pcm highway clock and frame synchronization conversion are enabled. [pcm_tsc_c ] [dce_cts_c ] pio44 od pcm time slot control c enables an external buffer device when channel c pcm highway data is present on the [pcm_txd_c] output pin in pcm highway mode. hdlc channel d (pcm) [pcm_rxd_d] [rxd_u] (uart) dce_rxd_d pio26 sti pcm receive data channel d is the serial data input pin for the channel d pcm highway interface. [pcm_txd_d] [txd_u] (uart) [dce_txd_d] pio20 o- ls- od pcm transmit data channel d is the serial data output pin for the channel d pcm highway interface. [pcm_clk_d] [rtr_u ] (uart) dce_rclk_d pio25 sti pcm clock is the single transmit and receive data clock pin for the channel d pcm highway interface. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description cc ch cc ch cc ch cc ch cc ch cc ch cc cc cc cc cc cc cc cc cc cc system overview am186?cc/ch/cu microcontrollers users manual 3-27 [pcm_fsc_d] [cts_u ] (uart) [dce_tclk_d] pio24 sti pcm frame synchronization clock provides the frame synchronization clock input (usually 8 khz) for the channel d pcm highway interface. [pcm_tsc_d ] [cts_hu ] (high- speed uart) [dce_cts_d ] pio46 od pcm time slot control d enables an external buffer device when channel d pcm highway data is present on the [pcm_txd_d] output pin in pcm highway mode. hdlc channel a (gci) [gci_dd_a] dce_rxd_a [pcm_rxd_a] bo d gci data downstream is the serial data input pin for the channel a gci interface. [gci_du_a] dce_txd_a [pcm_txd_a] bo d gci data upstream is the serial data output pin for the channel a gci interface. [gci_dcl_a] dce_rclk_a [pcm_clk_a] sti gci data clock is the single transmit and receive channel a gci data clock input generated by an upstream device. the data clock frequency must be twice the data rate. [gci_fsc_a] dce_tclk_a [pcm_fsc_a] sti gci frame synchronization clock provides the 8-khz frame synchronization clock input for the channel a gci interface generated by an upstream device. universal serial bus (usb) [udmns] [udpls] usbdC usbd+ sti sti usb external transceiver gated differential plus and usb external transceiver gated differential minus are inputs from the external usb transceiver used to detect single-ended zero and error conditions. the signals have the following meanings: usbd+ usbdC [udpls] [udmns] b b usb differential plus and usb differential minus form the bidirectional electrical data interface for the usb port. the pins form a differential pair that can be connected to a physical usb connector without an external transceiver. [usbsci] [uclk] [usbsof] pio21 sti usb sample clock input is used to synchronize an external clock to the internal usb peripheral controller for isochronous transfers. [usbsof] [uclk] [usbsci] pio21 o usb start of frame is a 1-khz frame pulse used to synchronize usb isochronous transfers to an external device on a frame-by- frame basis. utxdmns rsvd_102 o usb external transceiver differential minus is an output that drives the external transceiver differential driver minus input. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description cc cc cc cc cc cc cc cc cu cc cu cc cu usb external transceiver signals udpls udmns status 00 single-ended zero (se0) 0 1 full speed 10reserved 1 1 error cc cu cc cu cc cu cc cu cc cu system overview 3-28 am186?cc/ch/cu microcontrollers users manual 3.6 bus interface 3.6.1 overview the am186cc/ch/cu bus interface controls all accesses to the peripheral control block (pcb), memory-mapped and i/o-mapped external peripherals, and memory devices. the bus interface accesses internal peripherals through the pcb. the microcontroller provides an enhanced bus interface with the following features: n multiplexed address and data bus n nonmultiplexed address bus n option to disable the address phase of the address/data bus for accesses to the upper (ucs ) and/or lower (lcs ) memory regions n option to globally disable the address phase of the address/data bus for all memory or i/o accesses n programmable bus sizing, individually selectable for the upper (ucs ) memory space, lower (lcs ) memory space, all non-ucs and non-lcs memory space, and all i/o space n option to boot from an 8-bit device n separate byte write enables for high and low bytes n rd signal can act as output enable n bus-mastering support of a pcnet-isa interface by three-stating additional pins (ucs , lcs , mcs3 Cmcs0 , pcs7 Cpcs0 , and ale ) during bus-hold n integrated dram controller n data enable/data strobe (den /ds ) and data transmit/receive signal (dt/r ) provided to support an external data bus transceiver and to support a bus interface to 68xxx- style peripherals n support for the reset configuration (rescon) register used to latch system configuration information from the ad bus during a power-on reset n peripheral control block relocation (reloc) register configurable to perform a dual decode of pcb addresses; one address is locked at the default reset location and the other address depends on how the reloc register is programmed (default) utxdpls rsvd_101 o usb external transceiver differential plus is an output that drives the external transceiver differential driver plus input. uxvoe rsvd_103 o usb external transceiver transmit output enable is an output that enables the external transceiver. uxvoe signals the external transceiver that usb data is being output by the microcontroller. when low this pin enables the transceiver output, and when high this pin enables the receiver. uxvrcv rsvd_104 sti usb external transceiver differential receiver is a data input received from the external transceiver differential receiver. notes: 1. icons indicating microcontroller specific signals are used only in the signal name column. table 3-7 signal descriptions (continued) signal name 1 multiplexed signal(s) type description cc cu cc cu cc cu system overview am186?cc/ch/cu microcontrollers users manual 3-29 3.6.2 block diagrams figure 3-1 shows an am186cc/ch/cu microcontroller system with dram; figure 3-2, with sram. figure 3-1 typical microcontroller memory system with dram figure 3-2 typical microcontroller memory system with sram cas0 cas1 ras0 flash memory 4-mbit dram ma8Cma0 we oe data cas0 cas1 ras0 wr a19Ca0 ucs ad15Cad0 rd we address cs data oe (x8 or x16) am186cc/ch/cu microcontroller flash memory (x8 or x16) 8-bit sram x16 sram we cs oe address data data address oe cs we cs oe we address d7Cd0 we wr ucs rd a19Ca0 ad15Cad0 mcs0 lcs wlb whb am186cc/ch/cu microcontroller system overview 3-30 am186?cc/ch/cu microcontrollers users manual 3.6.3 operation 3.6.3.1 address and data buses the 80c186 and 80c188 microcontrollers use a multiplexed address and data (ad) bus. the address is present on the ad bus only during the t 1 clock phase. the am186cc/ch/cu microcontrollers provide the multiplexed ad bus and, in addition, provide a nonmultiplexed address (a) bus. the a bus provides an address to the system for the complete bus cycle. during refresh cycles, the ad bus is driven during the t 1 phase and the values are three- stated during the t 2 , t 3 , and t 4 phases. the value driven on the a bus is undefined during a refresh cycle. the nonmultiplexed address bus (a19Ca0) is valid one-half clkout cycle in advance of the address on the ad bus. when used with the modified ucs and lcs outputs and the byte write enable signals, the a19Ca0 bus provides a seamless interface to external sram, dram, and flash/eprom memory systems. for systems where power consumption is a concern, it is possible to disable the address from being driven on the ad bus on the microcontroller during the normal address portion of the bus cycle for accesses to ras0 , ras1 , upper (ucs ), and lower (lcs ) address spaces. in this mode, the affected bus is placed in a high-impedance state during the address portion of the bus cycle. this feature is enabled through the da bits (bit 7) in the upper memory chip select (umcs) and lower memory chip select (lmcs) registers. in addition, the dismem bit (bit 11, for memory addresses) and the disio bit (bit 10, for i/o addresses) in the syscon register serve as global address disables to prevent address bits from appearing on the ad15Cad0 bus. setting the dismem bit overrides clearing the da bits. when address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, thus decreasing power consumption, reducing processor switching noise, and preventing bus contention with memory devices and peripherals when operating at high clock rates. for more information about chip selects, see chapter 5, chip selects. if the aden pin is asserted during processor reset, the values of the da, dismem, and disio bits are ignored and the address is driven on the ad bus for all accesses, thus preserving the industry-standard 80c186 and 80c188 microcontrollers multiplexed address bus and providing support for existing emulation tools. for timing diagrams, see the data sheets for the am186cc/ch/cu microcontrollers. for more information about the registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. 3.6.3.2 programmable bus sizing the 80c186 microcontroller provided a 16-bit wide data bus over its entire memory and i/o address ranges, but did not allow accesses to an 8-bit wide bus. however, the data bus width on the am186cc/ch/cu microcontrollers is programmable through the upper memory chip select (umcs), lower memory chip select (lmcs), and pcs and mcs auxiliary (mpcs) registers. the usiz bit (bit 5) in the umcs register determines the width of the data bus for memory accesses to the upper memory region and the lsiz bit (bit 5) in the lmcs register determines the width for the lower memory region. the omsiz bit (bit 5) in the mpcs register specifies the width of the data bus for memory accesses to all non-upper and non-lower memory regions (i.e., mcs space, pcs space in memory, and the remaining memory space that does not reside in one of the enabled chip-select memory regions). the iosiz bit (bit 5) in the mpcs register specifies the width of the data bus for all i/o accesses. table 3-8 shows how the bit settings affect bus size. system overview am186?cc/ch/cu microcontrollers users manual 3-31 the width of the data access should not be modified while the processor is fetching instructions from the associated address space or while the peripheral control block is overlaid on the affected address space. 3.6.3.3 byte write enables the am 186cc/ch/cu microcontrollers provide two signals that act as byte write enables whb (write high byte, ad15Cad8) and wlb (write low byte, ad7Cad0). whb is the logical or of bhe and wr (whb is low when both bhe and wr are low). wlb is the logical or of a0 and wr (wlb is low when both a0 and wr are low). the byte write enables are driven with the nonmultiplexed address bus as required for the write timing requirements of common srams. 3.6.3.4 output enable the am186cc/ch/cu microcontrollers provide the rd (read) signal, which can act as an output enable for memory or peripheral devices. the rd signal is low when the microcontroller reads a word or byte. 3.6.3.5 bus mastering when an external bus master requests control of the local bus (by asserting hold), the microcontroller completes the bus cycle in progress. it then relinquishes control of the bus to the external bus master by asserting hlda and floating s2 Cs0 , ad15Cad0, s6, tmrout1, and tmrout0. during hold, internal pullups are active for bhe , den , dt/r , lcs , mcs1 /cas1 , mcs2 /cas0 , mcs3 /ras1 , pcs7 Cpcs0 , pio4/mcs0 , rd , ucs , whb , wlb , and wr and an internal pulldown is active for a19Ca0 and ale. table 3-8 programming am186cc/ch/cu microcontrollers bus width space register bit value bus width comments ucs umcs usiz n/a n/a dependent on boot option 1 notes: 1. ucs width on reset is determined by the {ucsx8} pin. if {ucsx8} is low, the bus width is x8; if {ucsx8} is high, the bus is x16. if ucs boots as 8-bit space, it can be overridden by clearing the usiz bit. if ucs boots as 16-bit space, it is not reconfigurable to 8-bit. lcs lmcs lsiz n/a n/a mcs mpcs omsiz 0 16 bits default 1 8 bits pcs 2 2. pcs space configured for memory only; not i/o. mpcs omsiz 0 16 bits default 1 8 bits i/o 3 3. if pcb space is mapped to i/o, its functions are not affected by this bit. mpcs iosiz 0 16 bits default 1 8 bits other memory 4 4. the remaining memory space that does not reside in one of the enabled, memory, chip-select regions. if pcb space is mapped to memory, its functions are not affected by this bit. mpcs omsiz 0 16 bits default 1 8 bits system overview 3-32 am186?cc/ch/cu microcontrollers users manual 3.6.3.6 dram controller the microcontroller has a fully integrated dram controller that provides a glueliss interface to 25-nsC70-ns edo dram. the microcontroller provides zero-wait state operation at up to 50 mhz with 40-ns dram. the dram controller includes the following features: n multiplexed addresses for dram row and column accesses n 8-bit and 16-bit boot mode for ucs accesses n two ras signals that support two banks of dram n two byte cas signals n direct support for 4-mbit (256kx16) extended data out (edo) drams n prioritized pcs over dram space accesses the various cycles in the microcontroller follow this priority ranking: refresh (highest priority), hold, dma, and cpu (lowest). for more information about dram, see chapter 6, dram controller. 3.7 clock control the microcontroller clocks include the general system clock (clkout), and the baud rate generator clock for the two universal asynchronous receiver transmitters (uart and high- speed uart). the synchronous serial interface (ssi) and the timers (timers 0, 1, and 2) derive their clocks from the system clock. 3.7.1 clock features the microcontroller includes the following clock features and characteristics. figure 3-3 illustrates the clocks. for detailed information on the clocks, see the data sheets for am186cc/ch/cu microcontrollers. n one crystal-controlled oscillator that uses an external fundamental mode crystal or oscillator to generate the system input clock. n one internal pll that generates a system clock (clkout) that is 1x, 2x, or 4x the system input clock. n ssi clock (sclk) is derived from the system clock, divided by 2, 4, 8, 16, 32, 64, 128, or 256. n timers 0 and 1 can be configured to be driven by the timer input pins (tmrin1, tmrin0) or at one-fourth of the system clock. timer 2 is driven at one-fourth of the cpu clock. n uart clock can be derived from the internal system clock frequency or from the uart clock (uclk) input. the am186cc and am186cu microcontrollers also include the universal serial bus (usb) clock with the following features: n one independent crystal-controlled oscillator that uses an external fundamental mode crystal or oscillator to generate the usb input clock. n one internal pll that generates the 48-mhz clock required for the usb from either a 24-mhz or 12-mhz input. n single clock source operation possible by sharing the clock source between the system and the usb. cu cc system overview am186?cc/ch/cu microcontrollers users manual 3-33 the am186cc and am186ch microcontrollers also include the transmitter/receiver clocks for each high-level data link control (hdlc) channel. in the am186cc microcontroller, each hdlc channel receives its clock inputs directly from the external communication clock pins (tclk _x and rclk_x) in all modes except in gci mode. in gci mode the external gci communication clocks (tclk_a and rclk_a) are first converted to an internal clocking format (analogous to pcm highway) before presentation to the hdlc. the system clock must be at least the same frequency as any hdlc clock. the am186cc microcontroller supports the following clock frequencies: n hdlc dce mode supports clocks up to 10 mhz. n hdlc pcm mode supports clocks up to 10 mhz. n hdlc gci mode supports a 1.536-mhz clock input. (system clock must be at least twice the gci clock.) in the am186ch hdlc microcontroller, each hdlc channel receives its clock inputs directly from the external communication clock pins (tclk _x and rclk_x) in all modes. the system clock must be at least the same frequency as any hdlc clock. the am186ch hdlc microcontroller supports the following clock frequencies: n hdlc dce mode supports clocks up to 10 mhz. n hdlc pcm mode supports clocks up to 10 mhz. figure 3-3 am186cc/ch/cu microcontroller clocks ch cc cc ch {clksel2}C{clksel1} clkout pll bypass mode 48-mhz usb clock {usbsel2}C{usbsel1} 1x 2x 4x 2x 4x x1 x2 am186cc/ch/cc microcontroller pll pll usbx1 uxbx2 cpu clock cc cu system overview 3-34 am186?cc/ch/cu microcontrollers users manual 3.7.2 pll bypass mode the am186cc/ch/cu microcontrollers provide a pll bypass mode that allows the x1 input frequency to be anything from 0 to 24 mhz. select pll bypass by asserting clksel1 and clksel2. when the microcontroller is in pll bypass mode, the clkout frequency equals the x1 input frequency. when changing frequency in pll bypass mode, the x1 input must not have any short or runt pulses. at 24 mhz, the nominal high/low time is 21 ns. the actual high times and low times must not fall below 16 ns. these values allow a 60%/40% duty cycle at x1. in the am186cc and am186cu microcontrollers, the usb pll and usbx1 determine the usb clock. usb requires the cpu clock to be 24 mhz or greater. therefore, disable the usb peripheral controller before slowing the cpu clock to less than 24 mhz. if usb is not used, you can pull down usbx1. in the am186cc and am186ch microcontrollers, the system clock must be at the same or a greater frequency than the hdlc clock and uclk (if using uclk). therefore, if reducing the system clock frequency, disable these interfaces or run them at a lower frequency. in the am186cc microcontroller, the system clock must be the same or twice the frequency of the gci clock. therefore, if reducing the system clock frequency, disable the gci interface or run it at a lower frequency. 3.8 hardware-related considerations n pins latched on reset (pinstraps) are not resampled during a watchdog-timer reset. n if the external reset (res ) signal is asserted while the watchdog timer is performing a watchdog-timer reset, the external reset takes precedence over the watchdog-timer reset. this means that the resout signal asserts as with any external reset and the wdtcon register does not have the rstflag bit set. in addition, the microcontroller exits reset based on the external reset timing (i.e., 4.5 clocks after the deassertion of res rather than 2 16 clocks after the watchdog timer time-out occurred). 3.9 comparison to other devices n the 80c186 microcontroller provided a 16-bit wide data bus over its entire address range, memory, and i/o, but did not allow accesses to an 8-bit wide bus. however, the data bus width on the am186cc/ch/cu microcontrollers is programmable to be 8 bits or 16 bits. n earlier am186 microcontrollers included a power save clock mode. the am186cc/ch/cu microcontrollers are not designed for low-power applications and therefore do not incorporate the power save clock mode. however, the am186cc/ch/cu microcontrollers do have a pll bypass mode that allows the x1 clock input frequency to be anything from 0 to 24 mhz. 3.10 initialization on both an external and internal reset, the following occurs: n the syscon register defaults to 00h, which has the following effects: sets normal timing on den for read and writes, disables pwd mode, enables memory and i/o addresses on the ad15Cad0 bus, and enables clkout. n the prl register defaults to the processor revision level. n multiplexed signals default as shown in table 3-7 on page 3-10. cu cc ch cc cc system overview am186?cc/ch/cu microcontrollers users manual 3-35 n on the am186cc microcontroller, both an external and an internal reset selects full hdlc with flow control for external interface d and sets hdlc channel c for raw dce or pcm highway mode. on an external reset, the following also occurs: n pinstraps are sampled (see table 3-5 on page 3-7). n the rescon register defaults to the value on ad15Cad0. cc system overview 3-36 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 4-1 chapter 4 emulator support 4.1 overview this chapter describes the various features available in the am186cc/ch/cu microcontrollers to facilitate the design and operation of an in-circuit emulator (ice). most of the discussion centers around the operation of pins. because different debug tool manufacturers take different approaches to emulator implementation, restrictions imposed by the use of one type of emulator may not apply to another. however, there are a number of common concerns shared among ice developers. this chapter discusses those concerns. 4.2 system design the main issues to consider are multiplexed pin use and emulator connection. 4.2.1 multiplexed pins because pins are an expensive resource, many of the pins on the am186cc/ch/cu microcontrollers serve more than one purpose. these multiplexed pins enable the system designer to select, by hardware or software means, the required operation of the pin. it can often be difficult for an emulator to know the function of such multiplexed pins, particularly if the system modifies pin operation on-the-fly. therefore, before committing a design to hardware, the system designer should contact potential emulator suppliers for a list of emulator pin requirements. certain pins are critical for successful emulator operation; these are address pins, chip selects, and memory access timing signals. it is important that these pins not be multiplexed in such a way as to compromise the emulator operation. fortunately, several pin functions can be successfully multiplexed. emulators generally do not monitor pins relating to input/ output (pio) operation and on-chip peripherals. the am186cc/ch/cu microcontrollers were designed to minimize conflicts. in most cases, pin conflict is avoided. for example, if the address latch enable (ale) signal is required for multiplex bus support, then it is not programmed as pio33. if the multiplexed ad bus is used for data only (not addresses), then ale can be programmed as a pio pin and the emulator will not require the ale signal. however, an emulator is likely to always use the de-multiplexed address, regardless of how the ad bus is programmed. the following pio signals are multiplexed with alternate signals that may be used by emulators: pio8, pio15, pio33, pio34, and pio35. consider any emulator requirements for the alternate signals before using these pins as pios. 4.2.2 emulator connection several package types present emulation problems. at the time of publication, the am186cc/ch/cu microcontrollers ship in 160-pin pqfp packages. when a pqfp device is soldered to a board, it cannot be removed and replaced with an emulator. in this situation, the cpu must be disabled somehow, and the emulator must be connected to the cpu to duplicate its functionality. the am186cc/ch/cu microcontrollers do this with the on-circuit emulation (once) mode. placing the microcontroller in once mode causes the output pins to become three-state and inactive. this feature allows a emulator support 4-2 am186?cc/ch/cu microcontrollers users manual designer to clip an emulator pod over the target cpu, then use once mode to disable the target cpu and provide a connection to each of the pqfp processor pins. be aware of any horizontal and vertical areas required by the emulators physical attachment method, and plan the board layout accordingly. one common mistake is to place connectors, switches, or other board controls under an area that will be partially covered by the emulator target board. also consider the arrangement of pin 1 versus the emulator attachment and plan accordingly. 4.3 operation 4.3.1 usage to use an emulator, the microcontroller must be put into once mode. to enter once mode, use the once reset configuration pin (pinstrap). once is sampled on the rising edge of res . if the once pin is asserted, the microcontroller enters once mode. otherwise, it operates normally. in once mode, all pins are three-stated and remain that way until a subsequent reset occurs. to ensure the microcontroller does not inadvertently enter once mode, once has a weak internal pullup resistor that is active only during an external reset. note: before using an emulator, ensure multiplexed pins are configured to reflect the use of the emulator and not other functionality. 4.3.2 emulator-related signals 4.3.2.1 a19Ca0 to facilitate emulation, the am186cc/ch/cu microcontrollers do not multiplex any of the a19Ca0 address pins. therefore, these pins are always available for emulation. 4.3.2.2 ad15Cad0 the am 186cc/ch/cu microcontrollers do not multiplex any ad15Cad0 address/data pins with other functionality, except that the value present on ad15Cad0 as the device comes out of external reset is latched and saved internally to the reset configuration (rescon) register. using this mechanism, a set of weak pullups and pulldowns can be put on the bus to allow hardware to communicate configuration information to the software. because this is an input function, it should not interfere with the operation of the emulator. however, the emulator should not interfere with the value present at reset, as software may be relying on the value for proper operation. 4.3.2.3 {aden } / bhe deasserting aden on reset can prevent the multiplexed ad bus from providing address information for lower (lcs ) and upper (ucs ) memory regions. some older ice designs force aden active to force address information on the ad bus. system designers should be aware if their emulator uses this operation and any conflicts this can cause with their hardware. 186 processors use bhe along with a0 to determine the type and width of external bus accesses. 188s do not have bhe , because all data on a 188 is 8 bits wide and routed through ad7Cad0. the am186cc/ch/cu microcontrollers do not support a 188 version, but do allow defining memory regions as 8-bit memory. when making accesses to 8-bit wide memory regions, bhe cannot be used to derive any information about the access. use the bsize8 signal to determine the width of a memory region unambiguously. emulator support am186?cc/ch/cu microcontrollers users manual 4-3 186 processors also use bhe with a0 to denote refresh cycles to 16-bit dram (both inactive). the am186cc/ch/cu microcontrollers do not support 8-bit wide dram designs, so using this mechanism to determine refresh cycles is reliable under all allowed dram designs. 4.3.2.4 ale in multiplexed bus mode, ale indicates that a valid address is on the ad bus. some emulators may require this signal. in most instances, an active chip select signal can also be used to indicate a valid address. 4.3.2.5 ardy and srdy if the target requires ready signals to operate, ardy and srdy cannot be used as pios. some emulators give the user control over the external ready target requirement. for instance, ready may be required by the emulator to match overlay memory speeds to faster target wait-state setups. 4.3.2.6 bhe see {aden }/bhe on page 4-2. 4.3.2.7 bsize8 the absence of bhe for 8-bit memory regions when an emulator design uses 16-bit overlay memory for a memory region defined as 8 bits wide poses problems for an emulator. the emulator must know when memory accesses are targeted at 8-bit regions to correctly steer the data between the low half of the data bus and the high half of the data bus. although it is possible to snoop all events that determine the memory width (chip select pulldowns during reset, and umcs, lmcs and mpcs register accesses), these methods can be unreliable. the am186cc/ch/cu microcontrollers bsize8 pin unambiguously signals the intended size of the memory region during external bus cycles. 4.3.2.8 [cas1 Ccas0 ] and [ras1 Cras0 ] the on-chip dram controller can be configured to work with dram in the lower (lcs ) or upper (ucs ) memory regions. the emulator needs to reconstruct the address used during an access. the cas signal can come too late for fast address generation. however, the complete address appears on the a19Ca0 bus during the ras cycle. additionally, because the full address bus is nonmultiplexed, it is a simple task to identify an access to the dram region. cas -before-ras cycles could also be used to determine if an access is a refresh, but the late arrival of the ras signal makes this problematic. the dram can only be accessed in 16-bit mode. this eliminates the problem of determining object size due to dynamic bus sizing. 4.3.2.9 clkout the internal processor clock can be sent out on the clkout pin. emulators generally require this. 4.3.2.10 lcs the system uses lcs as a ram chip select. emulators use this to determine when ram accesses occur, and can intercept it for overlay memory purposes. emulator support 4-4 am186?cc/ch/cu microcontrollers users manual 4.3.2.11 mcs3 Cmcs0 the system uses mcs1 and mcs2 as dram cas strobes. mcs0 and mcs3 can be used as extra memory chip selects. emulators can use these to determine when accesses occur to these memory spaces, and can intercept it for overlay memory purposes. 4.3.2.12 {once } once is not a dedicated pin but rather a pinstrap option that allows an external emulator to place a target device into on-circuit emulation mode. on reset of the microcontroller, if the once pinstrap is held low, all am186cc/ch/cu pins enter a high-impedance state. there is an internal pullup to prevent inadvertent assertion of once . 4.3.2.13 qs1Cqs0 the am186cc/ch/cu microcontrollers provide information about the execution queue on the queue status bus, qs1Cqs0. these signals assist in disassembling trace buffer information. 4.3.2.14 [ras1 Cras0 ] see [cas1Ccas0] and [ras1Cras0] on page 4-3. 4.3.2.15 rd the rd strobe can be intercepted by the emulator for use with overlay memory. 4.3.2.16 res the am186 processor family provides a schmitt trigger on the res input to enable the system designer to use an inexpensive rc circuit to provide system reset. the only restriction on power-up is for res to stay active (low) for at least 1 ms. systems that use this feature introduced a problem for in-circuit emulators because emulators need to know when the target processor comes out of reset. this can be difficult to determine when the target is being placed in once mode and the reset signal has a very slow rise time. emulator vendors solve this problem by providing a reset signal with a fast rise time. the hardware designer must use this emulator-supplied reset instead of the standard rc reset circuit. the am186cc/ch/cu microcontrollers provide a resout signal that unambiguously indicates when the device has come out of reset, eliminating this problem. however, many emulators still generate a target reset (in response to a user console command, for instance), and therefore need a means to connect the emulator-supplied reset to the target hardware. therefore, if ice usage is required, be aware of the emulators reset requirements and take them into consideration when designing the target hardware, typically by providing a convenient means to allow the emulator-supplied reset to be the main system reset. 4.3.2.17 resout resout is activated by the am186cc/ch/cu microcontrollers in response to either res being held active, or a system reset being generated by the internal watchdog timer. during reset, this pin is actively driven, regardless of the state of the once mode pinstrap (in contrast, all other output pins go to three-state if both res and once are active). when res is deasserted, resout is driven inactive. this high-to-low edge on resout is the signal that latches the value of all pinstrap options. when once is active and res is inactive, resout is driven inactive (all other outputs are three-stated), and held low for one clock cycle. after this one-clock period, resout is three-stated. this sequence of events allows an attached emulator to determine with certainty that the device has entered once mode. emulator supp o rt am186 ? cc/ch / cu m i crocontrol l ers use r s manual 4-5 4 .3 . 2. 1 8 s2 Cs0 the s2 Cs0 bus in d ic a tes t h e type of mem o ry cy c le i n progr e ss. 4 .3 . 2. 1 9 s6 the s6 si g nal is a c tive fro m t 1 Ct 4 o n the microcontroller and signal s a r e fresh or dma access. 4.3 . 2.20 srdy see ardy an d srdy on pag e 4- 3 . 4 .3 . 2. 2 1 ucs the system typically uses ucs as a flash or ro m chip select. emulators us e this to determine when rom accesses occu r , and can i n tercept it for overlay memory purposes. 4 .3 . 2. 2 2 {u c s x 8 } a n d w l b durin g processo r reset, the ucsx8 pin configures th e upper memory region fo r 8-bit operatio n . th e bsize8 signal unambiguously indicates the widt h of a memory r e gio n for a given acc e ss. 4 .3 . 2. 2 3 whb a n d wr th e emulator can interc e p t whb an d wr for us e with overla y memor y . although most emulat o rs us e s2 Cs0 to determin e cycle type, som e may u se the wr s ign a l to det e rmi n e when write s o ccu r . thi s prevents the use of wr a s a pio wh e n usin g t h e emulat o r . 4 .3 . 2. 2 4 wlb see ?{ ucsx 8} an d wlb? . 4 . 3 . 2. 2 5 wr se e whb a n d wr . 4.3.3 ha r dwa r e- r e lated considerations n b e sure to a llow room for puck s and emulato r head s o n your target board. n th e following pio signal s ar e multiplexe d with alternat e signals that ma y be u se d by emulat o rs: pio8 , pio15, pio33 , pio34, a n d pio 3 5 . conside r an y emulator requirement s for th e alter n at e signals b efore u sin g thes e pins as pios. 4 . 3 . 4 comparison to o t her dev i ces n previous am186 watc h dog timer im p lementations require d the application to disabl e the watchdo g time r t o prevent watchdo g time-out s whil e emulator code was executing. th e am186cc/ch/cu watchdo g time r doe s not have this limitation. a fe a ture of the watchdo g time r all o ws ice co d e to inhibi t th e cou n t o f th e watchdo g time r . 4.4 initialization on both exter n al and internal reset, the f o llowin g occurs: n multiplexe d pins used in emulation d e fault to signal s show n in chapte r 3, system overvie w . emulator support 4-6 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 5-1 chapter 5 chip selects 5.1 overview signals that allow the cpu to select specific memory or peripheral devices are called chip selects . the microcontroller provides six chip select outputs for use with memory devices (ucs , lcs , and mcs3 Cmcs0 ) and eight chip selects for use with peripherals (pcs7 Cpcs0 ) in either memory or i/o space. the six memory chip selects can be used to address three memory ranges. each peripheral chip select addresses a 256-byte block offset from a programmable base address in memory or i/o. the microcontroller can sense a ready signal for each of the memory or peripheral chip select lines. the r2 bit in each of the memory chip select control registers determines whether the external ready signal is required or ignored. in addition, the r1Cr0 bits in each of the memory chip select control registers control the number of wait states inserted in the bus cycle. although most memory and peripheral devices can be accessed with three or fewer wait states, some slower devices cannot. this feature allows devices to use externally generated wait states to slow down the bus. address and data bus size options and enabling or disabling the address bus during the address phase of a bus cycle are configured on a chip select basis. ucs and lcs can also be configured for dram support. the chip select lines are active for all memory and i/o cycles in their programmed areas, whether they are generated by the cpu or by the integrated dma unit. the ucs and lcs chip selects assert relative to the timing of the nonmultiplexed address (a) bus; the mcs and pcs chip selects assert relative to the multiplexed address and data (ad) bus. the timing for chip selects is shown in the data sheets for each of the am186cc/ ch/cu microcontrollers. the cas0 and cas1 signals can be used to perform byte writes in a manner similar to wlb and whb , respectively. that is, cas0 corresponds to the low byte (wlb ) and cas1 corresponds to the high byte (whb ). chip selects 5-2 am186?cc/ch/cu microcontrollers users manual 5.2 block diagram figure 5-1 shows the block diagram for the chip selects. figure 5-1 chip selects and dram block diagram 5.3 system design table 5-1 lists the chip select signals that are multiplexed with other am186cc/ch/cu functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. for diagrams of some example applications, see chapter 3, system overview. internal ucs cs/dram registers pcb_ad write data read data rd wr boot_width (cdram) refresh value refresh enable current value (edram) internal chip selects decode lcs_dram ucs_dram internal pcs 7 Cpcs 0 dram address internal ras 0 (from pads) internal a19-a11 control to 186 control from 186 (to pads) internal mcs0 pcs 7 Cpcs 0 mcs0 internal ras 1 internal cas 0 internal cas 1 control nmcs umcs lmcs pacs mpcs ucs mcs3Cmcs 1 lcs control to/from 186 refresh control chip select generation dram control pads chip selects am186?cc/ch/cu microcontrollers users manual 5-3 . 5.4 registers program the chip selects through the five 16-bit peripheral registers (see table 5-2). appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. table 5-1 chip selects multiplexed signals signal multiplexed signal(s) default signal function lcs ras0 lcs lower memory chip select mcs0 pio4 pio4 midrange memory chip selects mcs1 cas1 mcs1 mcs2 cas0 mcs2 mcs3 ras1 pio5 pio5 pcs0 pio13 pcs0 peripheral chip selects pcs1 pio14 pcs1 pcs2 pcs2 pcs3 pcs3 pcs4 pio3 pio3 pcs5 pio2 pio2 pcs6 pio32 pio32 pcs7 pio31 pio31 ucs ucs upper memory chip select table 5-2 chip select register summary offset register mnemonic register name description 3a0h umcs upper memory chip select programs the lower boundary of the upper memory chip select, ucs . also supports dram. 3a2h lmcs lower memory chip select programs the upper boundary of the lower memory chip select, lcs . also supports dram. 3a4h pacs peripheral chip select partially configures the peripheral chip selects, pcs7 C pcs0 (along with the mpcs register). sets the base address of the memory block selected by pcs . 3a6h mmcs midrange memory chip select partially configures the midrange memory chip selects, mcs3 Cmcs0 (along with the mpcs register). sets the base address of the memory block selected by mcs . 3a8h mpcs pcs and mcs auxiliary partially configures pcs7 Cpcs0 (along with the pacs register). determines whether pcs chip selects are mapped to memory or i/o space. also partially configures mcs3 Cmcs0 (along with the mmcs register). sets the block size of the memory block selected by mcs . chip selects 5-4 am186?cc/ch/cu microcontrollers users manual 5.5 operation 5.5.1 usage note: before using the chip selects, ensure multiplexed pins are configured to reflect the use of the chip selects and not other functionality (see table 5-1 on page 5-3). except for the ucs chip select, which is active on reset, chip selects are not activated until the associated register is written (not when it is read). all these signals are three-stated during a bus-hold condition and during reset to allow an external bus master to drive these signals directly. n to use the upper memory chip select (ucs ), configure the following umcs register options: C lower boundary of ucs (lb bit field) C ad bus disable (da bit) C dram enable (uden bit) C data bus width (usiz bit) C external ready mode (r2 bit) C wait state value (r1 and r0 bits) ucs is active on reset. n to use the lower memory chip select (lcs ), configure the following lmcs register options: C upper boundary of lcs (ub bit field) C ad bus disable (da bit) C dram enable (uden bit) C data bus width (lsiz bit) C external ready mode (r2 bit) C wait state value (r1 and r0 bits) lcs is activated when the lmcs register is written. n to use the peripheral chip select (pcs ), configure the following options in the pacs and mpcs registers: C base address (ba bit field in pacs) C external ready mode (r2 bit in pacs) C wait state value (r0, r1, and r3 bits in pacs) C pcs mapped to memory or i/o (ms bit in mpcs) C memory data bus width for all non-ucs and non-lcs memory (omsiz bit in mpcs) C i/o data bus width (iosiz bit in mpcs) the pcs chip selects are activated after both the pacs and mpcs registers are written. chip selects am186?cc/ch/cu microcontrollers users manual 5-5 n to use the midrange memory chip select (mcs ), configure the following options in the mmcs and mpcs registers: C base address (ba[19C13] bit field in mmcs) C mcs0-only mode (mcs0_only bit in mmcs) C external ready mode (r2 bit in mmcs) C wait state value (r1 and r0 bits in mmcs) Cmcs block size (m[6C0] bits in mpcs) C memory data bus width for all non-ucs and non-lcs memory (omsiz bit in mpcs) the mcs chip selects are activated after both the mmcs and mpcs registers are written. note: to configure the bus width for memory that does not reside in the lcs or ucs chip- select memory regions, program the omsiz bit in the mpcs register. to configure the bus width for i/o space, program the iosiz bit in the mpcs register. 5.5.2 selecting memory and i/o space all the chip selects can refer to addresses in memory. only the pcs chip selects can reference i/o space. figure 5-2 on page 5-6 shows which part of memory each chip select can address. the mcs chip selects should not be configured to overlap with memory space used by ucs , lcs , or pcs . figure 5-3 on page 5-7 shows the i/o space pcs7 Cpcs0 can select. 5.5.2.1 ucs the am186cc/ch/cu microcontrollers provide the ucs chip select for the top of the 1-mbyte memory address space. the upper boundary is fffffh; the lower boundary is programmable with the lb bit field in the umcs register. the block size must be a multiple of 64 kbyte. 5.5.2.2 lcs the lcs chip select is for the bottom of the 1-mbyte memory address space. the lower boundary is 00000h; the upper boundary is programmable with the ub bit field in the lmcs register. the block size must be a multiple of 64 kbyte. 5.5.2.3 mcs3 Cmcs0 mcs3 Cmcs0 provide for a user-locatable memory block. the base address can reside anywhere in the 1-mbyte memory address space as long as the base is an integer multiple of the block size (0 is a valid multiple), and memory space is not already mapped to by ucs , lcs (unless they are mapped to dram), or pcs . the am186cc/ch/cu microcontrollers also offer mcs0 only mode. when the mcs0- only bit in the mmcs register is cleared (the default) and the mcs chip selects are enabled, mcs3 Cmcs0 are each asserted over one fourth of the total block size. when this bit is set and the mcs chip selects are enabled, mcs0 is asserted over the entire mcs address range, and mcs3 Cmcs1 are still asserted over their individual address ranges. this means the entire middle chip select range is selectable through mcs0 ; the remaining mcs pins are available for other functions. this mode is useful if only one chip select is required or if dram is selected. for more information, see selecting dram using the chip selects on page 5-7. the ba bit field in the mmcs register programs the base address; the m[6C0] bits in the mpcs register program the total block size; the mcs0_only bit in the mmcs register enables mcs0 only mode. chip selects 5-6 am186?cc/ch/cu microcontrollers users manual 5.5.2.4 pcs7 Cpcs0 the am186cc/ch/cu microcontrollers each provide eight chip selects for eight contiguous, user-locatable, 256-byte address ranges within memory or i/o space. the base address can reside anywhere in the 1-mbyte memory address space as long as it is a multiple of 2 kbytes (0 is a valid multiple), and the memory space is not already mapped to by ucs , lcs , or mcs . (the pcs address range can overlap the ucs or lcs address ranges if they are mapped to dram.) the pcs chip selects can also access the 64-kbyte i/o space, as long as the base address is a multiple of 2 kbytes. the pcs chip selects are programmable with two registers. the ba bit field of the pacs register sets the base address (0 is a valid address). if the chip selects are programmed to reside in the cpus i/o space, bits ba[19C16] are forced to 0 by hardware, as the upper bound of the cpus i/o space is 64 kbytes. the ms bit in the mpcs register determines whether pcs chip selects are mapped to memory or i/o space. figure 5-2 chip selectable memory space 8-, 16-, 32-, 64-, 128-, 256-, or 512-kbyte block 1-mbyte memory space fffffh 00000h 80000h 7ffffh ucs selectable 64-, 128-, 256-, or 512-kbyte block lcs selectable mcs3 Cmcs0 selectable c0000h e0000h 64-, 128-, 256-, or 512-kbyte block 0ffffh 1ffffh 3ffffh base 1 base + 8k base + 16k base + 32k base + 64k base + 128k base + 256k base + 512k notes: 1. base must be an integer multiple of the block size and can be anywhere in memory space from 00000h to fdfffh, as long as memory space is not already mapped to by ucs , lcs , or pcs . 2. base must be a multiple of 2 kbytes and pcs memory region must not be configured to overlap with mcs space or non-dram lcs or ucs space. fffffh fffffh 00000h 00000h pcs7 Cpcs0 selectable base 2 base + 2047 bytes fffffh 00000h 8 contiguous 256-byte address regions f0000h chip selects am186?cc/ch/cu microcontrollers users manual 5-7 figure 5-3 chip selectable i/o space 5.5.3 selecting dram using the chip selects ucs and lcs can be configured for dram support with the uden bit in the umcs register and the lden bit in the lmcs register, respectively. psram is not supported. if both ucs and lcs are configured for dram, up to two banks of 256 kbit x 16 dram can be accessed. neither, either, or both dram banks can be activated. table 5-3 shows how the signals are configured when either ucs or lcs is configured for dram. table 5-3 signal function when ucs or lcs is configured for dram signal function ucs configured for dram mcs1 1 notes: 1. even if mcs3 Cmcs1 can no longer be used as chip selects, the mcs0 signal can select the en- tire middle chip select range when mcs only mode is enabled. also, the mcs3 Cmcs1 pins are multiplexed with programmable i/o pins. to enable their dram functionality, the pio mode and di- rection registers must be cleared. for more information, see chapter 9, programmable i/o sig- nals. acts as upper column address strobe signal (cas1 ) mcs2 acts as lower column address strobe signal (cas0 ) mcs3 acts as upper row address strobe signal (ras1 ) ucs ucs is held high. this means any memory device that uses ucs is disabled. this permits the user to disable a nonvolatile memory device providing boot- up code and replace it with dram memory. lcs configured for dram lcs acts as lower row address strobe signal (ras0 ) mcs1 acts as upper column address strobe signal (cas1 ) mcs2 acts as lower column address strobe signal (cas0 ) pcs7 Cpcs0 selectable base base + 2047 bytes ffffh 0000h 64-kbyte i/o space 8 contiguous 256-byte address regions chip selects 5-8 am186?cc/ch/cu microcontrollers users manual pcs7 Cpcs0 can overlap any ucs or lcs space which has been configured for dram. (overlap of the pcs signals with ucs or lcs in non-dram mode is not recommended.) overlapping pcs with dram is fully supported as long as the pcs chip selects are programmed for a greater or equal number of wait states than that of the dram. note: because of how the dram access is terminated, it is illegal to allocate a pcs space with fewer wait states than the dram it is overlapping. if pcs overlaps lcs or ucs configured for dram, pcs access takes precedence over the lcs or ucs access. the dram controller asserts ras and stops the cas signal from asserting. this does not modify the contents of the dram, and the access continues as a normal pcs access. overlapping the pcs chip selects with dram makes a 2-kbyte block of the dram inaccessible. in its place, the peripherals associated with the pcs can be accessed. this is especially useful when the entire memory space is used with two banks of dram or a bank of dram and a 512-kbyte flash memory. 5.5.4 overlapping chip selects although programming the various chip selects on the am186cc/ch/cu microcontrollers so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some systems. note that configuring pcs in i/o space with lcs or any other chip select configured for memory address 0 is not considered overlapping of the chip selects. overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. pcs overlaps are allowed when ucs or lcs are configured for dram. for more information about this overlapping, see selecting dram using the chip selects on page 5-7. in systems where the chip selects must overlap, the chip selects whose assertions overlap must have the same configuration for ready (external ready required or not required) and for the number of wait states to be inserted into the cycle by the processor. the peripheral control block (pcb) is accessed using internal signals. these internal signals function as chip selects configured with zero wait states and no external ready. therefore, the pcb can reside at addresses that overlap external chip select signals if those external chip selects are programmed to zero wait states with no external ready required. when overlapping an additional chip select with either the lcs or ucs chip selects, note that setting the disable address (da) bit in the lmcs or umcs register disables the address from being driven on the ad bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. the mcs and pcs chip select pins can be configured as either chip selects or as pio inputs or outputs. however, the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip selects or pios. this means that if these chip selects are enabled (by a write to the mmcs and mpcs registers for the mcs chip selects, or by a write to the pacs and mpcs registers for the pcs chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting for a ready signal. this behavior can occur even in a system in which ready is always asserted (ardy or srdy tied high). chip selects am186?cc/ch/cu microcontrollers users manual 5-9 5.5.5 configuring address and data buses 5.5.5.1 ucs and lcs when ucs or lcs are asserted, the da bit in the umcs or lmcs register selects whether the ad15Cad0 bus is driven during the address phase of a bus cycle. the da bit is still valid when ucs or lcs supports dram (either uden or lden is 1). that is, even though the ucs signal is held high and the lcs signal becomes ras0 in dram mode, the address phase on ad15Cad0 is still disabled during dram accesses to ucs /lcs space if da is set to 1. in addition, the dismem (for memory addresses) and disio (for i/o addresses) bits in the syscon register can act as global address disables to prevent address bits from appearing on the ad15Cad0 bus. setting the dismem bit overrides clearing the da bits. the block size programmed should match the size of the dram being used, otherwise the full capacity of the dram is not utilized. the ucsx8 signal is sampled during every external reset. if ucsx8 is 0, the lsiz/usiz bit is set in the lmcs/umcs register, which defines memory as an 8-bit space. this allows the microcontroller to boot from an 8-bit wide device. it is possible to later clear this bit, thus redefining the space to be 16 bits wide. only a hard system reset can cause this bit to be set; therefore, it is only possible to go from an 8-bit to a 16-bit space through software and not the reverse. if the system does a watchdog timer reset, this bit reverts to the value sampled on ucsx8 during the last external reset. the ucsx8 signal has a weak pullup that defaults the part into 16-bit operation. if dram is enabled for ucs or lcs , the bus size is forced to 16 bits. for more information about controlling the bus width, see table 3-8 on page 3-31. 5.5.5.2 non-ucs and non-lcs the omsiz bit determines the width of the data bus (i.e., x8 or x16) for memory accesses between the lcs and ucs memory regions (i.e., accesses above the lcs region and below the ucs region). an mcs space cannot overlap lcs or ucs memory, so it always lies in the space affected by the omsiz bit. a pcs space is only affected by the omsiz bit if the pcs space is in memory and does not overlap an lcs or ucs region. if a pcs space overlaps an lcs or ucs region, the pcs space is accessed as x16 memory. if the pcb space resides in an x8 memory region, each word-wide pcb register access generates two external bus cycles, but all 16 register bits are accessed internally on the first cycle. for more information, see peripheral registers on page 2-4. 5.5.5.3 pcs i/o space the iosiz bit in the mpcs register determines the width of the data bus (x8 or x16) for all i/o accesses. if the pcb space is mapped to i/o and the i/o bus width is x8, each word-wide pcb register access generates two external bus cycles, but all 16 register bits are accessed internally on the first cycle. for more information, see peripheral registers on page 2-4. chip selects 5-10 am186?cc/ch/cu microcontrollers users manual 5.5.6 programming ready signals and wait states the am186cc/ch/cu microcontrollers can sense a ready signal for each of the peripheral or memory chip select lines. the ready signal can be either the ardy or srdy signal. each chip select control register (umcs, lmcs, pacs, mmcs, and mpcs) contains a single-bit field, r2, that determines whether the external ready signal is required or ignored. when r2 is set to 1, external ready is ignored. when r2 is cleared to 0, external ready is required. the number of wait states to be inserted for each access to a peripheral or memory region is programmable. 0C3, 5, 7, 9, or 15 wait states can be inserted for the pcs7 Cpcs4 peripheral chip selects. note: because of how the dram access is terminated, it is illegal to allocate a pcs space with fewer wait states than the dram it is overlapping. zero to three wait states can be inserted for all other chip selects. two bits, r1 and r0, in each of the chip select control registers program the wait states. the pacs register also has the r3 bit for the additional pcs wait states. when external ready is required (r2 is 0), internally programmed wait states always complete before external ready terminates or extends a bus cycle. for example, if the internal wait states are set to insert two wait states (r1Cr0 = 10b), the processor samples the external ready signal during the first wait cycle. if external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). if external ready is not asserted during the first wait cycle, the access is extended until ready is asserted, which is followed by one more wait state followed by t 4 . when external readys are ignored (r2 is 1), the r1 and r0 bits alone configure the number of wait states. if dram is enabled for ucs or lcs , external readys are ignored regardless of the setting of r2. the ardy signal on the am186cc/ch/cu microcontrollers is a true asynchronous ready signal. the ardy signal accepts a rising edge that is asynchronous to clkout and is active high. if the falling edge of ardy is not synchronized to clkout as specified, an additional clock period may be added. 5.5.7 chip select timing the timing for the ucs and lcs outputs has been modified from the original 80c186 microcontroller. these outputs now assert with the nonmultiplexed address bus (a19Ca0) for normal memory timing. to allow these outputs to be available earlier in the bus cycle, the number of programmable memory size selections has been reduced. the mcs and pcs chip selects assert with the ad bus. for more information about chip select timing, see the data sheets for the am186cc/ch/ cu microcontrollers. 5.5.8 hardware-related considerations n the lcs memory space supports use of either the dram interface or the sram interface, not both. 5.5.9 software-related considerations n the chip selects are activated only by a write to a register. chip selects on previous am186 devices activated with a read or a write. n the umcs, lmcs, and mpcs registers contain a new data bus width bit; therefore, legacy code may accidentally change the bus width when writing to these registers. chip selects am186?cc/ch/cu microcontrollers users manual 5-11 5.5.10 comparison to other devices n general enhancements over the original 80c186 include bus mastering (three-state) support for all chip selects, and activation only when the associated register is written, not when it is read. in addition, each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186. n the chip selects for the am186cc/ch/cu microcontrollers are similar to the am186em and am186es microcontroller implementations except that the ucs and lcs space is now capable of gluelessly supporting dram. n the chip selects are activated by a write to a register. chip selects on previous am186 devices activated with a read or a write. n the am186cc/ch/cu microcontrollers offer eight peripheral chip selects rather than the six in other am186 implementations. n unlike previous am186 designs, pcs5 and pcs6 cannot be modified to provide latched address bits a1 and a2. n unlike previous am186 products, no refresh information is ever provided on mcs3 . n unlike the am186em and am186es products, the am186cc/ch/cu microcontrollers do not support psram mode. n data bus width is programmable to x8 or x16. this feature was not previously available on am186 devices. 5.6 initialization on both an external and internal reset, the following occurs: n the microcontroller begins fetching and executing instructions starting at memory location ffff0h, so upper memory is typically used as instruction memory. to facilitate this usage, ucs defaults to active on reset. n the lcs , msc3 Cmcs0 , and pcs7 Cpcs0 signals are not active on reset; activation requires a write access to the applicable memory chip select control register. n the mcs0 , mcs3 , and pcs7Cpcs4 signals default to pios. see table 5-1 on page 5-3 for the multiplexed pin defaults. n the value of the umcs register defaults to f0 x bh, where x is 00 y 1b and y is the inverted state of ucsx8 that was latched upon exiting reset. this defaults ucs to a 64-kbyte memory block starting at f0000h, with the ad bus enabled, ucs dram disabled, external ready, and three wait states. this action allows the ucs memory region to function as a non-dram bank so a system can boot from a nonvolatile memory device before software switches this memory region to a dram bank. n the value of the lmcs register is set to 0f1bh, which defaults lcs to a 64-kbyte memory block ending at 0ffffh, with the ad bus enabled, lcs dram disabled, external ready, and three wait states. however, the lcs chip select is not enabled until software writes to the lmcs register. n the value of the pacs register is set to 0073h, and the mpcs register is set to 8183h, which defaults pcs to a 256-byte block in i/o space starting at 0h, with external ready and three wait states. however, the pcs chip select is not enabled until software writes to both the pacs and mpcs registers. chip selects 5-12 am186?cc/ch/cu microcontrollers users manual n the value of the mmcs register is set to 7fdbh and the mpcs register is set to 8183h, which defaults mcs3 Cmcs0 each to 2 kbytes with a total mcs block size of 8 kbytes at a base address of 3fh, with external ready, and three wait states. however, the mcs chip selects are not enabled until software writes to both the mmcs and mpcs registers. n data bus widths are set as follows: Clcs is 16 bits wide. C non-ucs and non-lcs memory (mcs , pcs , and the remaining memory that does not reside in one of the enabled, memory chip-select regions) accesses are 16 bits wide. C all i/o accesses are 16 bits wide. n ucs is the inverse of the state of the ucsx8 that was latched on exiting external reset. if ucsx8 is 0, ucs is 8 bits wide; if ucsx8 is 1, ucs is 16 bits wide. in either case, ucs defaults to non-dram. am186?cc/ch/cu microcontrollers users manual 6-1 chapter 6 dram controller 6.1 overview dynamic random access memory (dram) offers memory at moderate speed and low cost. dram memory cells consist of one transistor and one capacitor. dram also uses a multiplexed address bus in a row/column format, which results in a lower pin count and smaller device package. dram is volatile; that is, if the capacitors for the memory cells are not periodically recharged, the contents of memory is lost. the process of periodically recharging the capacitors is called refresh. the dram controllers purpose is to use the processors address, status, and control lines to generate the multiplexed address strobes. the row address strobe (ras ) and column address strobe (cas ) signals latch the row and column addresses inside the dram. to support dram, the am186cc/ch/cu microcontrollers each have a fully integrated dram controller that provides a glueless interface to 40-ns, 50-ns, 60-ns, and 70-ns extended data out (edo) dram (edo dram is sometimes called hyper-page mode dram). up to two banks of 4-mbit (256 kbit x 16 bit) dram can be accessed. page mode, fast page mode (fpm), asymmetrical, and 8-bit wide dram are not supported. the am186cc/ch/cu microcontrollers support the most common dram refresh option, cas-before-ras. all refresh cycles contain three wait states to support the drams at various frequencies. the dram controller never performs a burst access. all accesses are single accesses to dram. if the pcs chip selects are decoded to be in the dram address range, pcs accesses take precedence over the dram. dram controller 6-2 am186?cc/ch/cu microcontrollers users manual 6.2 block diagram figure 6-1 shows the block diagram for the dram controller. figure 6-1 chip selects and dram block diagram (same as figure 5-1) 6.3 system design table 6-1 lists the dram signals that are multiplexed with other functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. for diagrams of some example applications, see chapter 3, system overview. . table 6-1 dram multiplexed signals signal multiplexed signal(s) default signal function cas0 mcs2 mcs2 column address strobes cas1 mcs1 mcs1 ras0 lcs lcs row address strobes ras1 mcs3 pio5 pio5 internal ucs cs/dram registers pcb_ad write data read data rd wr boot_width (cdram) refresh value refresh enable current value (edram) internal chip selects decode lcs_dram ucs_dram internal pcs 7 Cpcs 0 dram address internal ras 0 (from pads) internal a19-a11 control to 186 control from 186 (to pads) internal mcs0 pcs 7 Cpcs 0 mcs0 internal ras 1 internal cas 0 internal cas 1 control nmcs umcs lmcs pacs mpcs ucs mcs3Cmcs 1 lcs control to/from 186 refresh control chip select generation dram control pads dram controller am186?cc/ch/cu microcontrollers users manual 6-3 6.4 registers table 6-2 lists the 16-bit peripheral registers that determine the operation of the dram controller. you must also program the lden bit of the lmcs register and the uden bit of the umcs register for dram operation. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. 6.5 operation 6.5.1 usage note: before using the dram controller, ensure the multiplexed pins listed in table 6-1 on page 6-2 (pios, chip selects, and dram) are configured to reflect the use of the dram controller and not other functionality. to enable dram support for the am186cc/ch/cu microcontrollers, use the following process: 1. configure the ucs or lcs chip selects for dram. for information, see selecting dram using the chip selects on page 5-7. 2. set the rc bit field in the cdram register to the dram refresh rate. this is the number of cpu clocks between refresh cycles. all refresh cycles contain three wait states to accommodate the various drams supported. note that changing the value of this field after dram refresh has been enabled does not load the new value into the refresh counter until the current counter value has reached 0. 3. set the en bit of the edram register to 1 to enable dram refresh. 6.5.2 dram supported the am186cc/ch/cu microcontrollers support one or two banks of 40-ns, 50-ns, 60-ns, or 70-ns, 4-mbit (256 kbit x 16 bit), symmetrical extended data out (edo) dram (edo dram is sometimes called hyper-page mode dram). eight-bit (byte-wide) dram is not supported, and the dram does not operate properly if configured as an 8-bit area. however, it is still possible to perform byte accesses to 16-bit dram. simply perform a 16-bit read and choose the upper or lower byte as needed. the am186cc/ch/cu microcontrollers can boot from a nonvolatile memory device in ucs space and later switch the ucs space to a dram. the microcontrollers also support an 8-bit ucs boot mode, which allows the user to boot from an 8-bit device and later switch to 16-bit operation. it is not possible to boot from a 16-bit memory device and later switch to an 8-bit device. see chapter 5, chip selects, for details. table 6-3 shows the wait states used to support dram. table 6-2 dram controller register summary offset register mnemonic register name description 3aah cdram refresh clock prescaler used to configure the dram refresh rate. 3ach edram enable refresh control used to enable the refresh counter. it can also be used to sample the present value of the refresh down counter. dram controller 6-4 am186?cc/ch/cu microcontrollers users manual 6.5.3 dram interface the microcontroller provides zero-wait state operation at up to 50 mhz with 40-ns dram. internal wait states can be inserted to support slower dram; however, external ready detection is not supported. all signals required by the dram are generated on the microcontroller and no external logic is required. the dram multiplexed address pins are connected to the odd address pins starting with a1 on the microcontroller to ma0 on the dram (see table 6-4). the correct row and column addresses are generated on these pins during a dram access. table 6-4 shows how the physical address bits are mapped to row and column addresses on external pins. the cas0 and cas1 signals select which byte of the dram is accessed during a read or write. the ras0 signal controls the lower bank of dram, which starts at 00000h in the address map and is bounded by the ending address selected with the ub bit field in the lmcs register. the ras1 signal controls the upper bank of dram, which ends at fffffh and is bounded by the starting address selected in the lb bit field in the umcs register. when ras1 is asserted, ucs is automatically deasserted. neither, either, or both dram banks can be activated. table 6-3 dram supported by the am186cc/ch/cu microcontrollers cpu clock speed dram speed wait states refresh cycles 25 mhz 50 ns 0 7 clocks 60 ns 7 clocks 70 ns 7 clocks 40 mhz 50 ns 0 7 clocks 60 ns 1 7 clocks 70 ns 2 7 clocks 50 mhz 40 ns 0 7 clocks 50 ns 1 7 clocks 60 ns 2 7 clocks 70 ns 3 7 clocks table 6-4 address multiplexing reference am186cc/ch/cu address pin dram address pin row column a1 ma0 pa1 pa2 a3 ma1 pa3 pa4 a5 ma2 pa5 pa6 a7 ma3 pa7 pa8 a9 ma4 pa9 pa10 a11 ma5 pa11 pa12 a13 ma6 pa13 pa14 a15 ma7 pa15 pa16 a17 ma8 pa17 pa18 dram controller am186?cc/ch/cu microcontrollers users manual 6-5 the user can re-enable ucs by clearing the uden bit in the umcs register. doing so disables refreshing the upper bank of dram. if the data in the upper bank of dram does not have to be retained, no special action is required. if the data in the upper bank of dram must be retained, two options are available. the refresh control unit counter can be monitored through the edram register. when the counter reaches all zeros, a refresh occurs. the user can then disable the upper bank of dram using the uden bit in the ucms register, access the ucs -connected device, and then re-enable the upper bank of dram before the next refresh is scheduled to occur (usually 15.6 s). this retains the data in the upper bank of dram. alternatively, a software routine can conduct a read from all rows of the upper dram. then the uden bit can be switched to enable ucs and disable ras1 . the user then has the total refresh time (usually 16 ms) before the dram must be re-enabled to retain its data. after re-enabling the dram, the user should once again conduct reads on all the dram row addresses before letting the refresh controller resume refreshing the dram. 6.5.4 option to overlap dram with pcs the pcs7 Cpcs0 signals can overlap dram blocks with different wait states without external or internal bus contention. the ras0 or ras1 signals assert along with the appropriate pcs signal. the cas0 and cas1 signals do not assert, preventing the dram from writing erroneously or driving the data bus during a read. the pcs signals must be configured to have the same or greater number of wait states than the dram. in the case of an overlap, the bus width during pcs accesses is 16 bits. 6.5.5 dram refresh 6.5.5.1 dram refresh cycle when dram refresh is enabled, it operates off the processor internal clock. the following steps outline the refresh process: 1. the refresh control unit (rcu) checks the t bit field in the edram register to see if the counter = 0. if not, the clock decrements by 1 and the counter is checked again. this process is repeated until the counter = 0. 2. when the refresh counter = 0, the counter reloads the value from the rc field of the cdram register and starts again, simultaneously generating a cas-before-ras request to the bus interface unit. the dram refresh process continues until the en bit in the edram register is cleared. 3. the bus interface acknowledges the request. the refresh request stays active until the bus becomes available. 4. when the bus is free, the bus interface runs a dummy read cycle. note that the refresh clock counter continues counting independent of when the bus interface services the refresh request. if the hlda signal is active when a refresh request is generated (indicating a bus hold condition), then the microcontroller deactivates the hlda signal to perform a refresh cycle when the hold is negated. the circuit external bus master must negate the hold signal for at least one clock to allow the refresh cycle to execute. the refresh cycle has priority over all other bus cycles (cpu, dma, and so on). refresh changes no bits and looks like a read cycle. the various cycles follow this priority ranking: refresh (highest priority), hold, dma, and cpu (lowest). 5. after the refresh cycle completes, the hlda signal goes active and the controller continues with whatever activity was occurring before the refresh. 6. the request is removed. dram controller 6-6 am186?cc/ch/cu microcontrollers users manual 6.5.5.2 dram refresh intervals during a refresh cycle, the ad bus drives the address to ffffh, which prevents the pcs and mcs signals from asserting inadvertently. pcs and mcs decode should never contain the address fffffh. the ucs signal does not assert during a refresh cycle. if two banks of dram are being used in a system (i.e., ras0 and ras1 ), then both banks are refreshed at the same time. the interval counter (cdram register and edram register) is expanded by two bits over earlier am186 microcontrollers. the refresh counter has a maximum timer count that reaches 163.9 s at 50 mhz. see table 6-5 and equation 6-1. the normal refresh rate on a dram is 15.6 s. this refresh rate allows for each of the 1024 row addresses to be refreshed in the required 16 ms. some drams might have different refresh rates for low-power drams and special considerations. table 6-5 demonstrates the typical values that a programmer might want to use for refresh time intervals to be placed into the rc bit field of the cdram register. the am186cc/ch/cu microcontrollers support drams with a cas-before-ras refreshing scheme. a refresh is generated based on the system clock frequency. the maximum count value for a refresh is 163.9 s at 50 mhz. the cas-before-ras refresh cycle is seven clock cycles long. an 11-bit counter inserts a refresh bus cycle after the last bus cycle concludes to run the cas-before-ras cycle. equation 6-1 refresh interval time equation 6.5.6 hardware-related considerations n the lcs memory space supports use of either the dram interface or the sram interface, not both. n an external bus master needs to be able to deassert hold in response to hlda going inactive for dram refresh cycles to take place. 6.5.7 software-related considerations do not program the refresh period too small. if you do, the system does not have time to execute code. table 6-5 refresh interval times cpu frequency clock period cdram counter (hex) cdram counter (decimal) refresh interval time 50 mhz 20 ns 30ch 780d 15.6 s 40 mhz 25 ns 270h 624d 15.6 s 25 mhz 40 ns 186h 390d 15.6 s cdram counter value (decimal) = refresh interval time clock period dram controller am186?cc/ch/cu microcontrollers users manual 6-7 6.5.8 comparison to other devices the dram controller is similar to the am186ed dram controller, with these primary enhancements: 50 mhz, extended refresh interval times, and faster drams. the am186cc/ch/cu microcontrollers support 25-ns to 70-ns edo dram only. it does not support fast page mode dram. 6.6 initialization on both an external and internal reset, the following occurs: n the value of the cdram register becomes 0000h, setting the dram refresh period to 0. n the value of the edram register becomes 0000h, clearing and disabling the refresh counter. n the uden bit of the umcs register and the lden bit of the lmcs register both become 0, disabling ucs and lcs dram. see chapter 5, chip selects.. n the cas and ras multiplexed pins default to their alternate functions as shown in table 6-1 on page 6-2. n ucs is the inverse of the state of the ucsx8 that was latched on exiting external reset. if ucsx8 is 0, ucs is 8 bits wide; if ucsx8 is 1, ucs is 16 bits wide. in either case, ucs defaults to non-dram. dram controller 6-8 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 7-1 chapter 7 interrupts 7.1 overview an interrupt is a request to the cpu for service. cpus receive interrupt requests from a variety of sources, both internal and external. when the cpu receives a request, it stops executing the current task, and if the new task is of higher priority, begins executing that routine. at the end of the routine, the cpu returns to the original task. some interrupts can be disabled. these are called maskable interrupts. nonmaskable interrupts cannot be disabled. the am186cc/ch/cu microcontrollers feature an interrupt controller, which arranges the maskable interrupt requests by priority and presents them one at a time to the cpu. in addition to interrupts managed by the interrupt controller, the microcontroller supports eight nonmaskable interruptsan external or internal nonmaskable interrupt (nmi), a trace interrupt, and software interrupts and exceptions. the interrupt controller supports the maskable interrupt sources through the use of 15 channels. to make this possible, most interrupt channels support multiple interrupt sources. these channels are programmable to support the external interrupt pins or various peripheral devices that can be configured to generate interrupts. the maskable interrupt sources include 17 external sources plus a number of internal sources. the am186cc microcontroller has 19 internal maskable interrupt sources. the am186ch hdlc microcontroller has 14 internal maskable interrupt sources. the am186cu usb microcontroller has 13 internal maskable interrupt sources. the following am186cc microcontroller peripherals can generate internal interrupts: n three on-board timers (two of the timers can operate as pulse width modulators) n two uarts n four hdlc channels n the gci n four pairs of transmit/receive smartdma channels n four general-purpose dma channels n the usb peripheral controller cc ch cu cc interrupts 7-2 am186?cc/ch/cu microcontrollers users manual the following am186ch hdlc microcontroller peripherals can generate internal interrupts: n three on-board timers (two of the timers can operate as pulse width modulators) n two uarts n two hdlc channels n two pairs of transmit/receive smartdma channels n four general-purpose dma channels the following am186cu usb microcontroller peripherals can generate internal interrupts: n three on-board timers (two of the timers can operate as pulse width modulators) n two uarts n two pairs of transmit/receive smartdma channels n four general-purpose dma channels n the usb peripheral controller system configuration determines which of these devices and signals are available as interrupt sources. in addition to these internal interrupts, nine interrupt signals and eight pios can be configured as external interrupt sources. an nmi can be generated externally or internally. an external nmi is generated with the nmi signal. an internal nmi is generated by the microcontrollers watchdog timer. for more information on the watchdog timer, see chapter 11, watchdog timer. a trace interrupt is generated with the trace flag (tf bit) in the processor status flags (flags) register. see chapter 2, configuration basics. software can also generate interrupts and exceptions. a software interrupt is generated with the int or into instruction; a software exception is an interrupt resulting from an error condition after executing any instruction. software interrupt and exception sources are: divide error exception, breakpoint interrupt, into detected overflow exception, array bounds exception, unused opcode exception, and esc opcode exception. 7.2 block diagram figure 7-1 shows how the microcontroller supports interrupts. the interrupt controller is the interface between the execution unit and all the peripheral interrupt requests and external interrupt signals. the watchdog timer can generate an nmi when a time-out value is reached. software can determine whether an nmi was generated externally or internally by reading the rstflag and exrst bits in the watchdog timer control (wdtcon) register. ch ch interrupts am186?cc/ch/cu microcontrollers users manual 7-3 figure 7-1 interrupts block diagram 7.3 system design table 7-1 lists the interrupt signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. for diagrams of some example applications, see chapter 3, system overview. watchdog timer interrupt controller execution unit/ external nmi internal nmi int request control priority bus grant bus request interrupt state eoi execution unit notes: 1. software interrupt and traps are generated and resolved within the execution unit. interrupt sources timers (3) int8/pwd (1) int7Cint0 (8) pio5, 15, 27, 29, 30, 33, 34, 35 (8) general-purpose dmas (4) high-speed uart (1) uart (1) hdlcs (4) gci (1) smartdmas (4) usb (1) hdlcs (2) smartdmas (2) usb (1) smartdmas (2) cc ch cu bus interface 1 interrupts 7-4 am186?cc/ch/cu microcontrollers users manual . 7.4 registers table 7-2 lists the registers used by the microcontroller for interrupts. in addition, the if flag in the processor status flags (flags) processor register is used to enable or disable interrupts (see registers used on page 7-18). appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ ch/cu microcontrollers register set manual , order #21916. table 7-1 interrupt multiplexed signals signal multiplexed signal(s) default signal function int0 int0 maskable interrupt requests int1 int1 int2 int2 int3 int3 int4 int4 int5 int5 int6 pio19 1 notes: 1. for information about using pios as external interrupt sources, see pios as interrupts on page 7-18. pio19 1 int7 pwd 2 , pio7 1 2. selected by setting the pwd bit in the syscon register. pio7 1 int8 pwd 2 , pio6 1 pio6 1 pio5 1 ras1 , mcs3 ras1 pio15 1 wr wr pio27 1 tmrin0 pio27 pio29 1 dt/r dt/r pio30 1 den /ds den pio33 1 ale ale pio34 1 bhe , aden bhe pio35 1 srdy srdy nmi nmi nonmaskable interrupt interrupts am186?cc/ch/cu microcontrollers users manual 7-5 table 7-2 interrupt controller register summary offset register mnemonic register name description 300h ch0con interrupt channel 0 control configures one of the 15 interrupt channels. 302h ch1con interrupt channel 1 control 304h ch2con interrupt channel 2 control 306h ch3con interrupt channel 3 control 308h ch4con interrupt channel 4 control 30ah ch5con interrupt channel 5 control 30ch ch6con interrupt channel 6 control 30eh ch7con interrupt channel 7 control 310h ch8con interrupt channel 8 control 312h ch9con interrupt channel 9 control 314h ch10con interrupt channel 10 control 316h ch11con interrupt channel 11 control 318h ch12con interrupt channel 12 control 31ah ch13con interrupt channel 13 control 31ch ch14con interrupt channel 14 control 320h eoi end-of-interrupt used to clear the in-service bit of an interrupt that is currently in service. 322h poll poll indicates the interrupt type of the highest priority pending interrupt. 324h pollst poll status copy of the poll register. reading the poll status register has no effect on the rest of the system. 326h imask interrupt mask contains the mask bits for interrupt channels 0C14. these are the same physical mask bits that exist in all of the channel control registers, but here all channels are accessible at one time. 328h primsk priority mask determines the minimum priority required for a maskable interrupt source to be requested. 32ah inserv in-service indicates which channels are in-servicethe channels interrupt service routine is active. 32ch reqst interrupt request indicates which channels have pending requests. 32eh intsts interrupt status indicates the status of the general-purpose dma and timer interrupt channels. 330h dmahlt dma halt contains the dhlt bit which, when set, halts all dma activity. this bit is set by an nmi, and cleared by any iret instruction. this bit can be read or written by software. interrupts 7-6 am186?cc/ch/cu microcontrollers users manual 7.5 operation 7.5.1 usage note: before using the interrupts, ensure multiplexed signals are configured to reflect the use of the interrupts and not other functionality (see table 7-1 on page 7-4). 7.5.1.1 types of interrupt channels the interrupt channels can be organized into five groups: channel 0 (timers), channel 1 (int0 only), channels which support both an external and internal source (channels 2, 3, and 8C13), channels which support two internal sources (channels 4C7), and channel 14 (shared interrupts). channel 1 is a straightforward, single interrupt channel. for a list of interrupt types, see table 7-3 on page 7-12. for a map of the interrupt channels, see table 7-4 on page 7-16. the following sections discuss the other groups. 7.5.1.1.1 timer interrupt requests channel interrupt channel 0 supports the three timers. each timer has a bit in its control register that determines whether it is enabled to generate interrupt requests to the channel. the timers share a single programmable priority set in the ch0con register. in addition, the three timers have relative priorities (see table 7-3 on page 7-12). the interrupt controller uses the relative priority to arbitrate between the timers when more than one has an interrupt request pending. the channel logic determines which of the sources has the highest priority pending request and generates the interrupt vector based on that request. in previous parts, it could be confusing that all three interrupts required the same eoi (that of tmr0) even though they had different vectors. this happened because for all other sources, the vector number was identical with the eoi type. in the am186cc/ch/cu microcontrollers, any of the three vector numbers can be used for the eoi; however, all three function identically by clearing the in-service bit for channel 0. table 7-3 on page 7-12 lists the eoi type for each interrupt. channel 9 (supports general-purpose dma0 and general-purpose dma1 as well as int4) and channel 10 (supports general-purpose dma2 and general-purpose dma3 as well as int5) have similar behavior to the timers in regard to their support of the two dma channels. 7.5.1.1.2 external and internal interrupt request channels at any given point in time, interrupt channels 2, 3, 8, 9, 10, 11, 12, and 13 all support either an external or an internal source, but not both. the src bit in the chxcon register determines the source for channels 2, 3, and 8C11. channels 12 and 13 support the external source until the pwd bit in the syscon register is set. for example, channel 2 services the usb when the src bit is set, or int1 when the src bit is cleared. the setting 332h shreq interrupt shared request indicates if an int signal that is enabled for shared interrupts is currently requesting an interrupt on the shared channel, channel 14. 334h shmask interrupt shared mask determines if an int signal is masked (disabled) as a source for channel 14. 336h intpol interrupt polarity sets the polarity, active high or active low, of the int signals. 338h piopol pio polarity sets the polarity, active high or active low, of the eight pio signals that can be configured as interrupt sources. table 7-2 interrupt controller register summary (continued) offset register mnemonic register name description interrupts am186?cc/ch/cu microcontrollers users manual 7-7 or clearing of the src bit does not affect the vector generated, so int1 and the usb share the same interrupt vector. because only one can be generating interrupts at a time, this is unambiguous. all channels have a single programmable priority that is set in the chxcon register. 7.5.1.1.3 two internal interrupts request channels channels 4, 5, 6, and 7 support two internal interrupts. there is no src bit in the chxcon registers for these channels because both sources on the channel can be active at the same time. for example, channel 4 supports both hdlc_a and smda0. these sources are programmed to either generate or mask their interrupt requests to the channel through bits in the control registers of the individual peripherals. the channel logic distinguishes between the different interrupt request sources and generates the vector based on the source. the channel has a single programmable priority that is set in the chxcon register. in addition, the two sources for the channel have relative priorities (see table 7-3 on page 7-12). the interrupt controller uses the relative priorities to arbitrate between the two sources when both have interrupt requests pending. 7.5.1.1.4 shared interrupt request channel channel 14 is the shared interrupt request channel. all sources on the shared channel have the same interrupt vector and the same priority. software must examine the shared request (shreq) register to determine which source generated the interrupt. note that software must configure a pio pin as a pio input or output before using it as an interrupt source. 7.5.1.2 using maskable interrupts 1. before configuring the external interrupts int8Cint0 and the pio interrupts, clear the if flag in the flags register (with the cli instruction). however, most of the microcontrollers internal interrupts can be safely configured while maskable interrupts are enabled (i.e., the if flag is set). the if flag is cleared, disabling maskable interrupts, when the processor comes out of reset. 2. for pio interrupts, program the associated pio pin as a pio input through the piomodex and piodirx registers. 3. for external interrupts int8Cint0, program the polarity, active high vs. active low, through the intpol register. 4. program the source and priority for the associated interrupt channel through the src and pr bits in the chxcon register. note: do not perform step 3 and step 4 in a single write for edge-sensitive external interrupts. in this case, the polarity transition may be latched and generate a spurious interrupt request. level-sensitive interrupts are not latched so any spurious request disappears before external interrupts are enabled. 5. specify the minimum priority required for an interrupt request to be recognized by setting the pri bits in the primsk register. 6. specify the priority for the interrupts generated on a channel by setting the pri bits in each of the chxcon registers. the msk (mask or enable) bit can be set concurrently. 7. enable the desired interrupts by programming the ch bits in the imask register (if the msk bits were not configured in step 6). because these bits are physically identical to the msk bits in each of the chxcon registers, individual channels can be configured with the associated chxcon register. note: do not write to the imask register while interrupts are enabled (the if bit in the flags register is set). in this case, spurious interrupt requests may be generated, including requests from devices whose interrupts were disabled both before and after the write to interrupts 7-8 am186?cc/ch/cu microcontrollers users manual the imask register. it is safe to write the msk bits in the chxcon registers while interrupts are enabled. 8. program the shmask register to enable the int and pio interrupts that share channel 14. the shreq interrupt request is generated if any shared interrupt is asserted that is not masked off in the shmask register. 9. if interrupts are not enabled, enable interrupts by setting the if flag in the flags register using the sti instruction. 7.5.1.3 using nonmaskable interrupts to generate an nmi, use the nmi signal or watchdog timer. to generate a trace interrupt, set the tf bit in the flags register. to generate a software interrupt, execute an am186 instruction that generates an interrupt. this can be the int or into instruction, or a software exception caused by an instruction. for more information, see nonmaskable interrupts on page 7-18. 7.5.2 definitions of interrupt terms the following definitions cover some of the terminology used in describing interrupts. n interrupt channel: the group of logic that is comprised of a control register, an in- service bit, a request bit, and a mask bit. n interrupt source: any source such as an on-chip peripheral (internal) or physical pin (external) that can request an interrupt. n interrupt type : an eight-bit number assigned to each discrete interrupt, as listed in table 7-3 on page 7-12. each interrupt type does not need a unique interrupt channel; one interrupt channel can support more than one interrupt type. however, if one channel supports two interrupt types, then those two types have the same level of programmable priority. n programmable priority: each channel has eight levels of programmable priority, which are set in the channel control (chxcon) register. programmable priority determines which interrupt to service when two interrupts are requested at the same time. an interrupt service routine is interrupted by another interrupt request of equal or higher programmable priority, as long as the if flag in the flags register is set. for more information on setting the flags register, see chapter 2, configuration basics. if the programmable priority levels are equal, the overall priority number is used to resolve requests generated at the same time. the overall priority is not used to determine if a pending interrupt can interrupt an already executing interrupt service routine (isr). n overall priority: each interrupt source has an overall priority number which is only used to arbitrate between two interrupt sources that have priority requests pending with the same programmable priority level. overall priority is not used if the programmable priority is sufficient to resolve the pending highest-priority request. n interrupt vector address: this equals the interrupt type times four and is the location in memory that stores the address of the interrupt service routine for each interrupt type. n interrupt vector table: a memory area of 1 kbyte beginning at address 00000h that contains up to 256 four-byte interrupt vector addresses organized by segment/offset. n maskable interrupts: maskable interrupts can be affected by programming and are enabled and disabled by setting the if flag in the flags register. n nonmaskable interrupts: nonmaskable interrupts cannot be affected by programming, nor are they affected by the if flag. interrupts am186?cc/ch/cu microcontrollers users manual 7-9 n software interrupt: an interrupt initiated by the int or into software instruction, or by a software exception. a software interrupt does not affect the if flag. n software exception: a software interrupt that occurs when an instruction causes a particular condition in the processor. a software exception does not affect the if flag. n trace interrupt: the trace interrupt is the highest priority interrupt. it is a software interrupt in that it is initiated by software, but unlike other software interrupts, it does clears the if flag. n hardware interrupt: any one of the maskable interrupts, the nmi, and the watchdog timer interrupt. when a hardware interrupt is generated, the if flag is cleared unless in polled mode. 7.5.3 interrupt sequence the following sections describe how the microcontroller services interrupts. 7.5.3.1 requesting the interrupt when an interrupt is requested, the internal interrupt controller verifies that the interrupt is enabled and that there are no higher priority interrupt requests being serviced or pending. if the interrupt request is granted, the interrupt controller uses the interrupt type to access a vector from the interrupt vector table. each interrupt source has a corresponding interrupt type. each interrupt type has a four- byte vector available in the interrupt vector table. the interrupt vector table is located in the 1024 bytes from 00000h to 003ffh. each four-byte vector consists of a 16-bit offset (ip) value and a 16-bit segment (cs) value. the 8-bit interrupt type is shifted left two bit positions (multiplied by four) to generate the index into the interrupt vector table, as shown in figure 7-2. figure 7-2 interrupt vector translation when an interrupt is taken, the type is multiplied by four and the processor fetches the pointer to the interrupt service routine from that interrupt vector address. table 7-3 on page 7-12 shows a list of the types assigned to each interrupt source, as well as the interrupt vector address and the overall priority. the first entries in the table are the nonmaskable and software interrupt sources. the overall priority numbers are used only to resolve two interrupts that have identical programmable priority requests pending. in these cases, the type with the lowest overall priority number gets the highest priority. for overall priority numbers with letters, the lower letter is considered of higher priority (e.g., 2a is a higher priority than 2b). interrupt vector table locations ef 01 ab cd 12 34 56 78 interrupt vector for type 1 interrupt vector for type 0 0008 (2 ? 4) 0004 (1 ? 4) 0000 (0 ? 4) interrupt vector type 1 = ef01:abcd interrupt vector type 0 = 1234:5678 interrupts 7-10 am186?cc/ch/cu microcontrollers users manual 7.5.3.2 servicing the interrupt nonmaskable interruptsthe trace interrupt, the nmi/watchdog timer interrupt, and software interrupts (both user-defined (int) and software exceptions)are serviced regardless of the setting of the if flag in the flags register. for more information about nonmaskable interrupts, see nonmaskable interrupts on page 7-18. for maskable hardware interrupt requests to be serviced, the if flag must be set by the sti instruction, and the mask bit associated with each interrupt must be reset. for more information about maskable interrupts, see maskable interrupts on page 7-13. to service an interrupt request, the processor goes through the following steps: 1. when the processor senses a valid hardware interrupt, it pushes the next instruction address (cs:ip) and the flags register onto the stack. 2. after the processor pushes the flags register onto the stack, it clears the interrupt enable flag (if) to disable maskable interrupts during the interrupt service routine (isr). 3. the processor then loads the segment:offset values from the interrupt vector table into the code segment (cs) and the instruction pointer (ip), and begins executing the isr. 7.5.3.3 acknowledging the interrupt when the microcontroller services an interrupt, it sets the corresponding chx bit in the inserv register. the microcontroller generates no external acknowledge cycles; the only external indication that an interrupt is being serviced is that the processor reads the interrupt vector table. 7.5.3.4 end-of-interrupt (eoi) software must write to the end-of-interrupt (eoi) register to reset the chx bit in the inserv register when an interrupt service routine for a maskable interrupt completes. there are two types of writes to the eoi registerspecific eoi and non-specific eoi. in a specific eoi, software must specify the interrupt type in the eoi register s bit field to indicate which chx bit is to be reset. specific eoi is applicable when interrupt nesting is possible or when the highest priority chx bit that was set does not belong to the service routine in progress. in a non-specific eoi, software does not specify which chx bit is to be reset. instead, the interrupt controller clears the chx bits for all interrupt channels whose priorities match that of the highest priority interrupt in service. 7.5.3.5 returning from the interrupt the interrupt return (iret) instruction pops the flags register and the return address off the stack. program execution resumes at the point where the interrupt occurred. the interrupt enable (if) flag is restored by the iret instruction along with the rest of the processor status flags. if the if flag was set before the interrupt was serviced, interrupts are re-enabled when iret is executed. if there are valid interrupts pending when the iret is executed, the instruction at the return address is not executed. instead, the processor services the new interrupt immediately. if an isr intends to permanently modify the value of any of the saved flags, it must modify the copy of the flags register that was pushed onto the stack. interrupts am186?cc/ch/cu microcontrollers users manual 7-11 7.5.4 interrupt priority table 7-3 on page 7-12 shows the predefined types and overall priority structure for the am186cc/ch/cu microcontrollers. the overall priority column shows the priority for the interrupts at power-on reset and at watchdog timer reset. interrupt sources that constitute one request source share the same overall priority level with respect to other interrupt sources but are prioritized among themselves. this priority is indicated by letters following the priority number, with a having the highest priority, then b, etc. nonmaskable interrupts (types 0hC7h) are always higher priority than maskable interrupts. maskable interrupts have a programmable priority, set in the channel control (chxcon) registers, which overrides the overall priority. 7.5.4.1 nonmaskable interrupt and software interrupt priority the nonmaskable interrupts and software interrupts from 00h to 07h always take priority over the maskable hardware interrupts. within the nonmaskable and software interrupts, the trace interrupt has the highest priority, followed by the nmi/watchdog-timer interrupt, followed by the remaining software exceptions. after the trace interrupt and the nmi/watchdog-timer interrupt, the remaining software exceptions are mutually exclusive and can only occur one at a time, so there is no further priority breakdown. 7.5.4.2 maskable hardware interrupt priority beginning with interrupt type 08h (the timer 0 interrupt), the maskable hardware interrupts have both an overall priority and a programmable priority (see table 7-3). the programmable priority is the primary priority for maskable hardware interrupts and is set with the pr bit in the cgxcon registers. the overall priority is the secondary priority for maskable hardware interrupts. each of the maskable hardware interrupts has a programmable priority from zero to seven, with zero being the highest priority. because all maskable interrupts are set to a programmable priority of seven on reset, the overall priority of the interrupts determines the priority in which each interrupt is granted by the interrupt controller until programmable priorities are changed by reconfiguring the chxcon registers. for example, if the int6Cint0 interrupts are all changed to programmable priority six and no other programmable priorities are changed from the reset value of seven, then the int6C int0 interrupts take precedence over all other maskable interrupts. (within int6Cint0, the hierarchy is as follows: int0>int1>int2>int3>int4>int5>int6.) interrupts 7-12 am186?cc/ch/cu microcontrollers users manual table 7-3 interrupt types interrupt source interrupt/ eoi type vector table address related instruction or channel 1 notes: 1. see the am186 and am188 family instruction set manual, order #21267, for more information about the in- structions. see table 7-5 on page 7-17 for more information about the channels. overall priority nonmaskable interrupts divide error exception 00h 00h div, idiv 1c 2 2. these software exceptions can only occur one at a time, so there is no further priority breakdown. trace interrupt 01h 04h all 1a nmi / watchdog 02h 08h n/a 1b breakpoint interrupt 03h 0ch int3 1c 2 into detected overflow exception 04h 10h into 1c 2 array bounds exception 05h 14h bound 1c 2 unused opcode exception 06h 18h undefined opcodes 1c 2 esc opcode exception 07h 1ch esc opcodes 1c 2 maskable interrupts timer 0 08h 20h channel 0 2a timer 1 09h 24h channel 0 2b timer 2 0ah 28h channel 0 2c int0 0bh 2ch channel 1 3 int1 3 / usb 0ch 30h channel 2 4 int2 3 / high-speed uart 0dh 34h channel 3 5 hdlc a 0eh 38h channel 4 6a sdma0 0fh 3ch channel 4 6b hdlc b 10h 40h channel 5 7a sdma1 11h 44h channel 5 7b hdlc c 12h 48h channel 6 8a sdma2 13h 4ch channel 6 8b hdlc d 14h 50h channel 7 9a sdma3 15h 54h channel 7 9b int3 3 / gci 16h 58h channel 8 10a int4 3 / gp dma0 17h 5ch channel 9 10b gp dma1 18h 60h channel 9 10a int5 3 / gp dma2 19h 64h channel 10 11a gp dma3 1ah 68h channel 10 11b int6 3 / uart 1bh 6ch channel 11 12 int7 3 / 2nd pwd 4 1ch 70h channel 12 13 int8 / pwd 4 1dh 74h channel 13 14 pio5, pio15, pio27, pio29, pio30, pio33Cpio35 / int 7C1 (channel 14) 5 1eh 78h channel 14 15 cc cu cc ch cc ch cc ch cc ch cc cc cu cc cc cu cc interrupts am186?cc/ch/cu microcontrollers users manual 7-13 7.5.5 maskable interrupts 7.5.5.1 maskable interrupt cycle when the interrupt controller receives a request, it does the following: 1. sets the appropriate channel bit in the interrupt request (reqst) register to indicate a pending interrupt. if the request is from the on-board timers or general-purpose dma, it also sets the appropriate bit in the interrupt status (intsts) register to indicate a pending interrupt. if the request is for a channel 14 interrupt, it also sets a bit in the shared request (shreq) register to indicate a pending interrupt. 2. verifies the request by checking that the interrupt is enabled. an interrupt is enabled when the associated msk bit in the imask register is set. an interrupt request coming in through the shared request channel, channel 14, must also have the associated msk bit in the shmask register set. if the associated msk bit is not set, the interrupt is not recognized. 3. verifies that the requesting interrupts priority, set in the pri field of the chxcon register, is equal to or greater than the priority set in the primask register. if the interrupt source has not been programmed to equal or greater priority than the primask, the interrupt is not recognized. 4. compares the programmable priority of the requesting interrupt with that of any interrupts currently in service. if the interrupt source is not of equal or greater priority than the highest priority interrupt in service, the interrupt is not recognized. 5. if the interrupt is recognized, the controller generates an interrupt request to the execution unit. 6. if the if flag in the flags register is set, the execution unit recognizes the request. otherwise, the request remains pending until interrupts are enabled or the interrupting condition is cleared. 7. passes the interrupt type (also called interrupt number) to the bus interface so the processor can fetch the associated vector from the interrupt vector table. the interrupt type provides an index into the interrupt vector table. the actual interrupt vector, the address of the interrupt service routine, is found in the table at the address indicated by the interrupt type times 4. 8. sets the associated ch bit for the interrupt channel in the inserv register to indicate that an interrupt on that channel is currently being serviced by software. 9. the controller clears the ch bit for the channel when an eoi instruction is executed with either of two conditions: a specific eoi that specifies this channel or a non-specific eoi when this channel is the highest priority interrupt whose ch bit is set. 3. the type and overall priority for the int1Cint7 pins in this table assume that these pins are being serviced by a dedicated channel; that is, they are not being serviced by channel 14. when the int1Cint7 pins are being ser- viced by channel 14, they share type 1eh, overall priority 15, as indicated by the last row in table 7-3. 4. pwd is generated on the low-to-high transition of the pwd input; the second pwd is generated on the high- to-low transition. 5. see the shreq register description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for information on the shared channel 14. interrupts 7-14 am186?cc/ch/cu microcontrollers users manual 7.5.5.2 interrupts in polled mode software can handle interrupt requests in polled mode. in polled mode, configure the interrupt sources exactly as in normal interrupt mode, but do not set the if bit in the flags register. this disables automatic hardware servicing of interrupt requests. in this case, software must periodically read the poll or pollst register to determine if a valid interrupt request is pending. reading the poll or pollst register provides identical information; however, a read of the poll register generates an interrupt recognition cycle whereas a read of the pollst register does not. except for the manner in which the interrupt recognition is generated, and the fact that software must jump to the interrupt service routine, the behavior under normal interrupt and polled mode interrupt is identical. this means, for example, that the chx bit in the insvr register must be cleared by an eoi instruction as in normal interrupt mode. 7.5.5.3 considerations for nmi, software interrupts, and traps the nonmaskable interrupt (nmi) is not processed through the interrupt controller. its detection is not affected by the settings of the if flag, the bits in the insrv register, or by the priority mask. when an nmi interrupt is taken, the if flag is cleared and the dhlt bit is set. this disables maskable interrupts and inhibits dma transfers. although the nmi is the highest priority hardware interrupt, it does not participate in the priority resolution scheme of the maskable interrupts. setting the if flag using the sti instruction during an nmi service routine is discouraged because any maskable interrupt may interrupt an executing nmi routine, assuming it meets the criteria outlined above. dma activity may be re-enabled by clearing the dhlt bit but this could increase the number of cycles required to complete the nmi routine and, consequently, the number of cycles during which interrupts are disabled. a currently executing nmi service routine may be preempted by a second nmi request. nmi is active when the part is reset and cannot be disabled. the nmi can be generated externally through the nmi pin or internally through the watchdog timer. the microcontroller logically ors the two sources internally to provide a single signal to the execution unit. because the nmi signal is edge-sensitive, it is possible to block the recognition of a watchdog timer nmi by holding the external nmi signal asserted. systems that do not use external nmi should hold this pin low to yield control to the watchdog timer nmi. a software interrupt or trap is not processed through the interrupt controller and is not affected by the setting of the if flag, the bits in the insrv register, by the priority mask, or by a currently executing nmi service routine. 7.5.5.4 maskable interrupt overview interrupt types 08h through 1eh are maskable (see table 7-3 on page 7-12). the maskable interrupts are enabled and disabled by the if flag in the flags register, but the int command can execute any interrupt regardless of the setting of if. maskable interrupts are supported through the interrupt controller, which contains the configuration and status of all the interrupt sources, as well as priority resolution logic to select which interrupts to process in which order. the interrupt controller supports maskable interrupts with 15 interrupt channels. because of the large number of interrupt sources available, some sources share interrupt channels. table 7-4 on page 7-16 and table 7-5 on page 7-17 show which channels service each source. interrupts am186?cc/ch/cu microcontrollers users manual 7-15 the interrupt controller uses the peripheral registers listed in table 7-2 on page 7-5 to support generating a maskable interrupt. in addition, the flags processor register contains a flag to enable the interrupts and one to set the trace interrupt. for more information about the interrupt registers, see registers used on page 7-18. of the maskable interrupts, 17 signals are provided for external interrupt sources: 9 interrupt signals and 8 pios (the nmi signal is nonmaskable and is generally used for unusual events like power failure). the interrupt types for these inputs are generated internally. every interrupt channel has an in-service bit. if a lower-priority device requests an interrupt while the in-service bit (is) is set for a high-priority interrupt, the interrupt controller does not generate an interrupt. in addition, if another interrupt request occurs from the same interrupt source while the in-service bit is set, the interrupt controller does not generate an interrupt. this allows interrupt service routines operating with interrupts enabled to be suspended only by interrupts of equal or higher priority than the in-service interrupt. when an interrupt service routine completes, software must reset the proper in-service bit by writing the eoi type to the eoi register. this is required to allow subsequent interrupts from this interrupt source and to allow servicing of lower-priority interrupts. software should execute a write to the eoi register at the end of the interrupt service routine just before the return from interrupt instruction. 7.5.5.5 maskable interrupt block diagram figure 7-3 shows a partial block diagram of how the sources and channels are used (see figure 7-1 on page 7-3 for another block diagram). the three timers share channel 0 and produce three separate types. the int0 signal is dedicated to channel 1. the gp dma0 and gp dma1 are muxed with the int4 signal onto channel 9, and they produce up to two separate types (only one type is generated if channel 9 services the int4 signal). the int4 signal is also connected to the channel 14 shared interrupts through a mask register and shares the same type as the rest of the channel 14 shared interrupts. figure 7-3 partial block diagram of interrupt controller scheme 15 interrupt channels 3 types ch0 int4 gp dma1 gp dma0 ch9 ch14 2 types 8 pios int1-3,5-7 1 shared type ch1 int0 tim0 tim1 tim2 1 type mask ch1 interrupts 7-16 am186?cc/ch/cu microcontrollers users manual table 7-4 interrupt channel map interrupt source interrupt channel 1 0123 4 5 6 7 8 9 10 11 12 13 14 timer 0 x timer 1 x timer 2 x high-speed uart x uart x hdlc_a x hdlc_b x hdlc_c x hdlc_d x gci x sdma0 x sdma1 x sdma2 x sdma3 x gp dma0 x gp dma1 x gp dma2 x gp dma3 x usb x int0 x int1 x x int2 x x int3 x x int4 x x int5 x x int6 x x int7 x x int8 x pwd 2 x 2nd pwd 2 interrupt x pio5 x pio15 x pio27 x pio29 x pio30 x pio33 x pio34 x pio35 x cc ch cc ch cc cc cc cc ch cc ch cc cu cc cu cc cu interrupts am186?cc/ch/cu microcontrollers users manual 7-17 notes: 1. channels 0 to 3 and 8 to 13 can have only one interrupt source active at a time (e.g., channel 2 can only service the int1 signal or the usb at any one time). channels 4 to 7 (shaded) can service up to two sources at once (e.g., channel 4 can service the hdlc_a as well as sdma0 interrupt requests). the peripherals that generate the inter- rupts on channels 4 to 7 have the option of enabling or disabling their requests. channel 14 (shaded) is provided to allow a second channel to service interrupt requests from external signals. this is useful for systems that require a large number of peripheral interrupts (e.g., if a system is using usb interrupts via channel 2, the int1 signal is able to request an interrupt through channel 14). channel 14 can simultaneously service any source indicated in its col- umn. for channel 14, a register individually masks on or off the signals serviced by this channel so that individual control of interrupt sources is possible. 2. for a complete description of pulse width demodulation (pwd) mode, see chapter 10, programmable timers. table 7-5 interrupt channel sources interrupt channel default source optional source 0 timer 0, timer 1, and timer 2 1 int0 2 int1 usb 3 int2 high-speed uart 4 hdlc channel a and smartdma channel pair 0 5 hdlc channel b and smartdma channel pair 1 6 hdlc channel c and smartdma channel pair 2 7 hdlc channel d and smartdma channel pair 3 8 int3 gci 9 int4 general-purpose dma 0 and 1 10 int5 general-purpose dma 2 and 3 11 int6 uart 12 int7 pwd 1 notes: 1. the pwd source is selected by setting the pwd bit in the syscon register. 13 int8 pwd 1 14 shared request 2 2. the shared request source is controlled by the shreq and shmask registers. the following sources can be enabled to use the shared request channel: pio5, pio15, pio27, pio29, pio30, pio33, pio34, and pio35; and int pins 7C1. cc cu cc ch cc ch cc ch cc ch cc cc cu cc cc cu cc interrupts 7-18 am186?cc/ch/cu microcontrollers users manual 7.5.5.6 pios as interrupts eight pios (pio5, pio15, pio27, pio29, pio30, pio33, pio34, and pio35) are programmable as external interrupt sources on shared channel 14. these pios are level- triggered. pio15, pio29, pio30, pio33, pio34, and pio35 default to their alternate function at external or internal reset. to use these signals as interrupts, enable them as interrupts in the shmask register. typically, software should configure these signals as inputs in the piomodex and piodirx registers when using them as interrupt sources. if any of these signals is configured as both a pio output and as an interrupt source, the pio output signal generates interrupts. for more information, see table 9-3 on page 9-6. in addition, three pios (pio6, pio7, and pio19) are multiplexed with external interrupt signals (int8, int7, and int6, respectively) so they can act as interrupts when the signals interrupt signal is enabled. these signals can be programmed with the ltm bit in the chxcon register to be edge- or level-triggered. 7.5.5.7 registers used each interrupt channel has a control register, an in-service bit, a request bit, and a mask bit programmed with the 15 channel control registers, the in-service register, the interrupt request register, and the interrupt mask register. because channel 14 shares interrupts, it requires two additional registers to implement the shared interrupts: the shared mask register and the shared request register. the control register for channel 14 contains a priority field and mask bit only. for detailed information about these and the other peripheral registers used to control interrupts, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. in addition, bits 8 and 9 in the flags register relate to interrupt operation. bit 8 of the flags register is the trace flag (tf). when tf is set to 1, a trace interrupt occurs after each instruction executes. tf is cleared by the trace interrupt after the processor status flags are pushed onto the stack. the trace service routine can continue tracing by popping the flags back with an iret instruction. bit 9 of the flags register is the interrupt enable flag (if). if acts as an enable for all maskable interrupts. if if is set to 1, maskable interrupts are enabled and can cause processor interrupts. individual maskable interrupts can still be disabled through their corresponding mask bit in the imask or chxcon registers. some peripheral devices have their own interrupt mask bits, as well. clearing if to 0 disables all maskable interrupts regardless of the setting of the mask bits in the imask or chxcon registers or any other peripheral control mask bits. the if flag does not affect the nmi, trace, or software exception interrupts (interrupt types 00h to 07h), and it does not affect the execution of any interrupt through the int instruction. 7.5.6 nonmaskable interrupts interrupt types 00h through 07h (see table 7-3 on page 7-12) and all software interrupts cannot be masked by programming, and are not affected by the setting of the if flag. software interrupts are initiated with the int or into instruction. a software exception interrupt occurs when an instruction causes an interrupt due to some condition in the processor. interrupt types 00h, 03h, 04h, 05h, 06h, and 07h are software exception interrupts. for more information about int or other instructions, see the am186 and am188 family instruction set manual , order #21267. interrupts am186?cc/ch/cu microcontrollers users manual 7-19 7.5.6.1 software interrupts up to 256 possible interrupts can be initiated by the int or into instructions. int 21h causes an interrupt to the vector located at 00084h in the interrupt vector table. int ffh causes an interrupt to the vector located at 003fch in the interrupt vector table. 7.5.6.2 divide error exception (interrupt type 00h) when a div or idiv instruction quotient cannot be expressed in the number of destination bits, it generates a divide error exception. 7.5.6.3 trace interrupt (interrupt type 01h) if the trace flag (tf) in the flags register is set, the trace interrupt is generated after most instructions. the trace interrupt is the highest priority interrupt. this interrupt allows programs to execute in single-step mode. the interrupt is not generated after prefix instructions like rep, instructions that modify segment registers like pop ds, or the wait instruction. taking the trace interrupt clears the tf bit after the flags are pushed onto the stack. the iret instruction at the end of the single step interrupt service routine restores the processor status flags (including the tf bit) and transfers control to the next instruction to be traced. taking the trace interrupt also clears the if flag. trace mode is initiated by pushing the flags register onto the stack, then setting the tf flag on the stack, and then popping the flags. for more information about the flags register, see chapter 2, configuration basics. 7.5.6.4 nonmaskable interrupt (interrupt type 02h) an nmi can be generated internally or externally. an internal nmi is generated with the watchdog timer. for more information about the watchdog timer, see chapter 11, watchdog timer. an external nmi is generated with the nmi signal. this signal indicates to the microcontroller that an interrupt request has occurred. the nmi signal is the highest priority hardware interrupt and, unlike the int8Cint0 signals, cannot be masked. when nmi is asserted, the processor transfers program execution to the location specified by the nonmaskable interrupt vector in the interrupt vector table. additionally, when an nmi occurs, dmas are suspended. if your application is using a dma channel, the nmi interrupt handler may need to update the dma configuration settings to account for the dma being suspended by the nmi. an nmi transition from low to high is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. to guarantee that the interrupt is recognized, the nmi signal must be asserted for at least one clkout period. for information about the nonmaskable interrupt and interrupt priority processing, see considerations for nmi, software interrupts, and traps on page 7-14. 7.5.6.5 breakpoint interrupt (interrupt type 03h) the 1-byte version of the int instruction (int3) causes a breakpoint interrupt. 7.5.6.6 int0 detected overflow exception (interrupt type 04h) if the of bit is set in the flags register, an int0 instruction generates the int0 detected overflow exception. for more information about the flags register, see chapter 2, configuration basics. interrupts 7-20 am186?cc/ch/cu microcontrollers users manual 7.5.6.7 array bounds exception (interrupt type 05h) if an array index is outside the array bounds, a bound instruction generates an array bounds exception. the array bounds are located in memory at a location indicated by one of the instruction operands. the other operand indicates the value of the index to be checked. for more information, see the am186 and am188 family instruction set manual , order #21267. 7.5.6.8 unused opcode exception (interrupt type 06h) if the processor attempts to execute an undefined opcode, it generates an unused opcode exception. 7.5.6.9 esc opcode exception (interrupt type 07h) if the processor attempts to execute an esc opcode (d8hCdfh), it generates the esc opcode exception. the processor does not check the escape opcode trap bit. the return address of this exception points to the esc instruction that caused the exception. if a segment override prefix preceded the esc instruction, the return address points to the segment override prefix. note: all numeric coprocessor opcodes cause a trap. the am186cc/ch/cu microcontrollers do not support the numeric coprocessor interface. 7.5.7 software-related considerations n the watchdog timer can generate an nmi. this interrupt can be taken at any time. unlike the maskable interrupts, the controller is not inhibited from taking a second nmi request while the nmi interrupt service routine is executing. therefore a watchdog timer- generated nmi can interrupt, or be interrupted by, an externally generated nmi. for more information about the watchdog timer nmi, see considerations for nmi, software interrupts, and traps on page 7-14. n writing a zero to the appropriate channel bit in the interrupt request (reqst) register clears the pending interrupt. this facility provides a simple way to clear a spurious edge- triggered interrupt that may have occurred when initially configuring a pio pin as an interrupt source. 7.5.8 comparison to other devices the interrupt controller supports the fully nested master mode and polled mode operation available in all amd am186 devices. the interrupt controller does not support slave mode, cascade mode, or special fully nested mode. support for the nmi and software interrupts are similar to master mode in amds am186es microcontroller. 7.6 initialization on both an external and internal reset, the following occurs: n all priority bits in the channel control (chxcon) registers are set to 1. this places all sources at the lowest priority (level 7). the overall priority of the interrupts determines the priority in which each interrupt is granted by the interrupt controller until programmable priorities are changed by reconfiguring the chxcon registers. n all mask bits in the channel control (chxcon) registers are set to 1, so all interrupts are masked. n all level-triggered mode (ltm) bits in the channel control (chxcon) registers are cleared, resulting in edge-triggered mode. n all source bits in the channel control (chxcon) registers are cleared, defining the source as that channels external interrupt source. interrupts am186?cc/ch/cu microcontrollers users manual 7-21 n the end-of-interrupt (eoi) register is cleared, so no in-service bits are cleared. n the poll (poll) and poll status (pollst) registers are cleared, so polling mode is disabled. n the interrupt mask (imask) register and shared mask (shmask) registers are set to ffffh, so all interrupts are masked. n the prm bits in the priority mask (primsk) register are set to 7d, allowing interrupts of all priorities. n the in-service (inserv) register is cleared, indicating that no interrupts are active. n the interrupt request (reqst), interrupt status (intsts), and shared request (shreq) registers are cleared, indicating there are no pending interrupts. n the dma halt (dmahlt) register is cleared, so dma activity is unaffected. n all bits in the interrupt polarity (intpol) and pio polarity (piopol) registers are set to 1, so int9Cint0 and pio5, pio15, pio27, pio29, pio30, and pio33Cpio35 are set to be active high. n multiplexed signals int8Cint6 default to pio functionality as shown in table 7-1 on page 7-4. n multiplexed signals pio15, pio29, pio30, and pio33Cpio35 default to their alternate functionality, as described in chapter 9, programmable i/o signals. n the if flag in the flags register is cleared, disabling maskable interrupts. interrupts 7-22 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 8-1 chapter 8 dma controller 8.1 overview direct memory access (dma) permits the transfer of data between memory and peripherals without cpu involvement. with dma transfers, the dma controller becomes the bus master. the arbitration for the bus is internal to the processor and is not visible externally. when the dma no longer has transfers pending (no internal or external drqs are asserted) or a higher priority event occurs, the dma controller removes its request for the bus thus freeing the bus for other types of cycles. the type of dma transfer dictates how long the dma controller has control of the bus. however, because a dma transfer is using the bus, the processor can be slowed down if it also needs the bus. each of the am186cc/ch/cu microcontrollers contains a dma controller that provides both smartdma channels and general-purpose dma channels. the general-purpose dma channels can be used for data transfer between memory and i/o spaces (i.e., memory-to- i/o or i/o-to-memory) or within the same space (i.e., memory-to-memory or i/o-to-i/o). in addition, the general-purpose dma controller supports data transfer between some internal peripherals and memory or i/o. the smartdma channels provide a method for transmission and reception of data across multiple memory buffers and a sophisticated buffer-chaining mechanism. these channels are always used in pairs: transmitter and receiver. the transmit channels can only transfer data from memory to a peripheral; the receive channels can only transfer data from a peripheral to memory. the am186cc microcontroller provides a total of 12 dma channels: eight smartdma channels and four general-purpose dma channels. four of the smartdma channels (two pairs) are dedicated for use with two of the on-board hdlc channels. the remaining four smartdma channels (two pairs) can support either the third or fourth hdlc channel or universal serial bus (usb) endpoints a, b, c, or d. on-chip peripherals that support general-purpose dma are timer 2, the two asynchronous serial ports (the uart and the high-speed uart), and the usb peripheral controller. external peripherals support dma transfers through the external dma request signals. each general-purpose channel accepts a dma request from one of four sources: the dma request signals (drq1Cdrq0), timer 2, the uarts, or the usb peripheral controller. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) the am186ch hdlc microcontroller provides a total of eight dma channels: four smartdma channels (two transmit-receive pairs, 0 and 1) and four general-purpose dma channels. the smartdma channel pairs are dedicated to the two on-board hdlc channels. on-chip peripherals that support general-purpose dma are timer 2, and the two asynchronous serial ports (the uart and the high-speed uart). external peripherals support dma transfers through the external dma request signals. each general-purpose channel accepts a dma request from one of three sources: the dma request signals (drq1Cdrq0), timer 2, or the uarts. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) the am186cu usb microcontroller also provides four smartdma channels (two transmit- receive pairs, 2 and 3) and four general-purpose dma channels. the smartdma channel cc ch cu dma controller 8-2 am186?cc/ch/cu microcontrollers users manual pairs support the usb endpoints a, b, c, or d. on-chip peripherals that support general- purpose dma are timer 2, the two asynchronous serial ports (the uart and the high- speed uart), and the usb peripheral controller. external peripherals support dma transfers through the external dma request signals. each general-purpose channel accepts a dma request from one of four sources: the dma request signals (drq1Cdrq0), timer 2, the uarts, or the usb peripheral controller. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) up to 64 kbytes or 64 kwords can be transferred to or from even or odd addresses on the am186cc/ch/cu microcontrollers. two bus cycles (a minimum of eight clocks) are necessary for each general-purpose dma data transaction. for word transfers, both the source and destination addresses must be configured as 16-bit addresses. the smartdma channels only support byte transfers. data is written or read from sequential byte addresses in the memory buffers. the smartdma channels also feature fly-by dma transferswhat would typically take two cycles (a read and write) is moved in a single cycle on the external processor bus; read and write are performed concurrently in one cycle. the general-purpose dma channels and the smartdma channels can be programmed so that one channel/channel pair is always given priority over the other, or they can be programmed to alternate cycles when both have dma requests pending. dma controller am186?cc/ch/cu microcontrollers users manual 8-3 8.2 block diagram figure 8-1 shows the block diagram for the general-purpose dma and smartdma controllers. figure 8-1 dma block diagram dma3C0 control (2) dma3C0 transfer count dma3C0 dest addr (2) dma3C0 source addr (2) sdma3C0 control tx_dma3C0 tx_dma3C0 20-bit gp dma sdma sdma control arbiter dma generator cycle drq select drq1Cdrq0 control bus tc bus dst/src addr bus select drq11 Cdrq0 rx_dma3C0 rx_dma3C0 bus request bus grant pcb interface address decode drq11Cdrq0 sdma3C0 status tx_dma3C0 dmareg pcb block usb hdlc timer biu int cntl biu add/sub state machine state machine buffer descriptor count buffer descriptor pointer current buffer descriptor buffer descriptor count buffer descriptor pointer cc cu cc ch dhlt uart/ high-speed uart dma controller 8-4 am186?cc/ch/cu microcontrollers users manual 8.3 system design table 8-1 lists the dma signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. . 8.4 registers the dma controller is programmed through the use of registers: seven registers for each general-purpose channel and nine for each pair of smartdma channels (see table 8-2). in addition, software can use the dma halt (dmahlt) register (an interrupt controller register) to halt dma activity. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. dma channel control registers can be changed while the channel is operating. any changes made during dma operations affect the current dma transfer. all dma registers except the gdxcon0 and gdxcon1 registers can be modified or altered during any dma activity. any changes made to these registers are reflected immediately in dma operation. table 8-1 dma multiplexed signals signal function multiplexed signal(s) default signal drq0 dma requests pio9 pio9 drq1 drq1 table 8-2 dma controller register summary offset register mnemonic register name description general-purpose dma channel registers 100h gd0con0 general-purpose dma0 control 0 set up general-purpose dma channel 0. software must stop dma operation before writing to these registers, or results will be unpredictable. 102h gd0con1 general-purpose dma0 control 1 104h gd0srcl general-purpose dma0 source address low the 16 bits of this register, combined with four bits of the high register, produce a 20-bit source address for general-purpose dma channel 0. 106h gd0srch general-purpose dma0 source address high four bits of this register [19C16], combined with the 16 bits of the low register, produce a 20-bit source address for general-purpose dma channel 0. 108h gd0dstl general-purpose dma0 destination address low the 16 bits of this register, combined with four bits of the high register, produce a 20-bit destination address for general-purpose dma channel 0. dma controller am186?cc/ch/cu microcontrollers users manual 8-5 10ah gd0dsth general-purpose dma0 destination address high four bits of this register [19C16], combined with the 16 bits of the low register, produce a 20-bit destination address for general-purpose dma channel 0. 10ch gd0tc general-purpose dma0 transfer count sets the transfer count (the number of dma transfers to be performed) for general-purpose dma channel 0. 110h gd1con0 general-purpose dma1 control 0 behaves the same as general-purpose dma0 registers, but for dma channel 1. 112h gd1con1 general-purpose dma1 control 1 114h gd1srcl general-purpose dma1 source address low 116h gd1srch general-purpose dma1 source address high 118h gd1dstl general-purpose dma1 destination address low 11ah gd1dsth general-purpose dma1 destination address high 11ch gd1tc general-purpose dma1 transfer count 120h gd2con0 general-purpose dma2 control 0 behaves the same as general-purpose dma0 registers, but for dma channel 2. 122h gd2con1 general-purpose dma2 control 1 124h gd2srcl general-purpose dma2 source address low 126h gd2srch general-purpose dma2 source address high 128h gd2dstl general-purpose dma2 destination address low 12ah gd2dsth general-purpose dma2 destination address high 12ch gd2tc general-purpose dma2 transfer count 130h gd3con0 general-purpose dma3 control 0 behaves the same as general-purpose dma0 registers, but for dma channel 3. 132h gd3con1 general-purpose dma3 control 1 134h gd3srcl general-purpose dma3 source address low 136h gd3srch general-purpose dma3 source address high 138h gd3dstl general-purpose dma3 destination address low 13ah gd3dsth general-purpose dma3 destination address high 13ch gd3tc general-purpose dma3 transfer count table 8-2 dma controller register summary (continued) offset register mnemonic register name description dma controller 8-6 am186?cc/ch/cu microcontrollers users manual smartdma channel pair 0 and 1 registers 140h sd0con smartdma0 control sets up smartdma channel 0. 142h sd0trcal smartdma0 transmit ring count / address low indicates the number of available buffer descriptors per transmit ring in smartdma channel 0. also contains the low address bits [15C4] of the transmit buffer descriptor ring address for smartdma channel 0. 144h sd0trah smartdma0 transmit ring address high points to the transmit buffer descriptor ring high address bits [19C16] for smartdma channel 0. 146h sd0rrcal smartdma0 receive ring count / address low indicates the number of available buffer descriptors per receive ring in smartdma channel 0. also contains the low address bits [15C4] of the receive buffer descriptor ring address for smartdma channel 0. 148h sd0rrah smartdma0 receive ring address high points to the receive buffer descriptor ring high address bits [19C16] for smartdma channel 0. 14ah sd0stat smartdma0 status indicates the status of smartdma channel 0. 14ch sd0cbd smartdma0 current buffer descriptor indicates the buffer descriptor currently accessed by smartdma channel 0. 14eh sd0ctad smartdma0 current transmit address indicates the current address of the data being transmitted by smartdma channel 0. 150h sd0crad smartdma0 current receive address indicates the current address of the data being received by a smartdma channel. 158h sd1con smartdma1 control behaves the same as smartdma channel 0 registers, but for smartdma channel 1. 15ah sd1trcal smartdma1 transmit ring count / address low 15ch sd1trah smartdma1 transmit ring address high 15eh sd1rrcal smartdma1 receive ring count / address low 160h sd1rrah smartdma1 receive ring address high 162h sd1stat smartdma1 status 164h sd1cbd smartdma1 current buffer descriptor 166h sd1ctad smartdma1 current transmit address 168h sd1crad smartdma1 current receive address table 8-2 dma controller register summary (continued) offset register mnemonic register name description cc ch dma controller am186?cc/ch/cu microcontrollers users manual 8-7 8.5 operation the am186cc/ch/cu microcontrollers contain two distinct types of dma channels: general-purpose dma channels and smartdma channels. the smartdma channels are further broken down into transmit and receive channels, which are used in pairs. the microcontrollers dma channels can be used as shown in table 8-3, table 8-4, and table 8-5. the discussion of general-purpose dma channels begins in general-purpose dma channels on page 8-11; the discussion of smartdma channels begins in smartdma channels on page 8-26. in some cases, a hybrid between dma processing and interrupt processing is appropriate. this is described in dma and interrupts on page 8-10. smartdma channel pair 2 and 3 registers 170h sd2con smartdma2 control behaves the same as smartdma channel 0 registers, but for smartdma channel 2. 172h sd2trcal smartdma2 transmit ring count / address low 174h sd2trah smartdma2 transmit ring address high 176h sd2rrcal smartdma2 receive ring count / address low 178h sd2rrah smartdma2 receive ring address high 17ah sd2stat smartdma2 status 17ch sd2cbd smartdma2 current buffer descriptor 17eh sd2ctad smartdma2 current transmit address 180h sd2crad smartdma2 current receive address 188h sd3con smartdma3 control behaves the same as smartdma channel 0 registers, but for smartdma channel 3. 18ah sd3trcal smartdma3 transmit ring count / address low 18ch sd3trah smartdma3 transmit ring address high 18eh sd3rrcal smartdma3 receive ring count / address low 190h sd3rrah smartdma3 receive ring address high 192h sd3stat smartdma3 status 194h sd3cbd smartdma3 current buffer descriptor 196h sd3ctad smartdma3 current transmit address 198h sd3crad smartdma3 current receive address table 8-2 dma controller register summary (continued) offset register mnemonic register name description cc cu dma controller 8-8 am186?cc/ch/cu microcontrollers users manual table 8-3 am186cc communications controller dma channel use dma channel associated peripheral general-purpose dma channels 0C3 memory-to-memory transfers (note i/o space can be used in addition to memory space), timer 2, external peripherals (via the drq signals), internal uart or high-speed uart, or any usb data endpoint (aCd) configured in either direction smartdma pair 0 receive channel hdlc a receiver smartdma pair 0 transmit channel hdlc a transmitter smartdma pair 1 receive channel hdlc b receiver smartdma pair 1 transmit channel hdlc b transmitter smartdma pair 2 transmit channel hdlc c transmitter or usb data endpoint b if configured as a usb in endpoint 1 smartdma pair 2 receive channel hdlc c receiver or usb data endpoint a if configured as a usb out endpoint 1 notes: 1. for smartdma channels 2 and 3, the transmit and receive cannot be assigned to different pe- ripherals. for example, if smartdma channel 2 receive is assigned to usb data endpoint a, then smartdma channel 2 transmit can be used for usb data endpoint b, but cannot be used with the hdlc controller. smartdma pair 3 transmit channel hdlc d transmitter or usb data endpoint d if configured as a usb in endpoint 1 smartdma pair 3 receive channel hdlc d receiver or usb data endpoint c if configured as a usb out endpoint 1 table 8-4 am186ch hdlc microcontroller dma channel use dma channel associated peripheral general-purpose dma channels 0C3 memory-to-memory transfers (note i/o space can be used in addition to memory space), timer 2, external peripherals (via the drq signals), internal uart or high-speed uart smartdma pair 0 receive channel hdlc a receiver smartdma pair 0 transmit channel hdlc a transmitter smartdma pair 1 receive channel hdlc b receiver smartdma pair 1 transmit channel hdlc b transmitter cc ch dma controller am186?cc/ch/cu microcontrollers users manual 8-9 8.5.1 when to use dma using dma is appropriate under certain circumstances. in general, using dma means trading programming simplicity for efficient data movement between peripherals. for most devices, using dma does not mean that interrupt handlers are no longer needed, although the interrupt handlers perform differently than when dma is not used. using dma can produce the following benefits: n reduced system interrupt latency, thereby helping to guarantee data integrity note that this is often a second-order effect (e.g., if system interrupt latency is too long for device a, it may be useful to use dma with device b to rectify it). n reduced bus or cpu cycles dma code consumes fewer bus and cpu cycles than interrupt or polling code. n improved communications performance some peripheral devices require dma for proper operation. for example, the usb peripheral controller in the am186cc and am186cu microcontrollers requires dma to transmit or receive packets which are larger than an endpoints fifo size. 8.5.2 dma priority dma channels can be programmed to three levels of priority (a single value applies to both the transmit and receive channels for one smartdma channel pair). higher priority dma channels are granted the bus before lower priority channels and can effectively hold off lower priority dma requests for multiple transfers. when two dma requests of the same programmed priority have transfers pending, they alternate transfers. when three or more requests of equal priority have transfers pending, they take turns (i.e., 123123123...). dma cycles always have priority over internal cpu cycles except between internally locked memory accesses or word accesses to odd memory locations. however, an external bus hold or a refresh cycle takes priority over a dma cycle. because an interrupt request cannot suspend a dma operation and the cpu cannot access memory during a dma cycle, interrupt latency time suffers during sequences of continuous dma cycles. however, an nmi request causes all internal dma activity to halt. this allows table 8-5 am186cu usb microcontroller dma channel use dma channel associated peripheral general-purpose dma channels 0C3 memory-to-memory transfers (note i/o space can be used in addition to memory space), timer 2, external peripherals (via the drq signals), internal uart or high-speed uart, or any usb data endpoint (aCd) configured in either direction smartdma pair 2 transmit channel usb data endpoint b if configured as a usb in endpoint smartdma pair 2 receive channel usb data endpoint a if configured as a usb out endpoint smartdma pair 3 transmit channel usb data endpoint d if configured as a usb in endpoint smartdma pair 3 receive channel usb data endpoint c if configured as a usb out endpoint cu dma controller 8-10 am186?cc/ch/cu microcontrollers users manual the cpu to respond quickly to the nmi request. software can also inhibit dma transfers by setting the dhlt bit in the dmahlt register. priorities for the general-purpose dma channels are set through the gdxcon0 registers; smartdma channel priorities are set with the sdxcon registers. 8.5.3 dma request synchronization synchronized data transfers are either source or destination synchronizedeither the source of the data or the destination of the data generates a drq to request the data transfer. note that the terms source and destination are relative to the data movement. for example, a uart receiver is source-synchronized; the uart is the source of the data and the drq (see figure 8-2). dma transfers can also be unsynchronized (i.e., drq is always asserted, and the transfer takes place continually until the correct number of transfers has occurred). for more information about general-purpose dma channel synchronization, see setting synchronization on page 8-17. for more information about smartdma channel synchronization, see smartdma channel request source and synchronization on page 8-27. figure 8-2 source versus destination synchronization 8.5.4 dma acknowledge the am186cc/ch/cu microcontrollers do not provide an explicit dma acknowledge signal. because both source and destination registers are maintained, a read from a requesting source or a write to a requesting destination serves as the dma acknowledge signal. because the chip-select lines can be programmed to be active for a given block of memory or i/o space, and the dma source and destination address registers can point to the same given block, a chip-select line can indicate a dma acknowledge. 8.5.5 dma and interrupts in some cases, a combination of both dma processing and interrupt processing is appropriate (e.g., when a certain amount of protocol processing must be performed for each character, and this processing should take place at the interrupt level). in this situation, using a circular receive buffer with extended reads can effectively extend or replace the uart fifo with a buffer in main memory. for more information, see using buffer queues serial port receive data serial port transmit data (sprxd) register (sptxd) register rxd txd memory buffer uart receiver uart transmitter here the source of the data is requesting the transfer so the uart receiver is source-synchronized. here the destination of the data is requesting the transfer so the uart transmitter is destination synchronized. dma controller am186?cc/ch/cu microcontrollers users manual 8-11 or circular buffers on page 8-20. this method helps guarantee data integrity by ensuring that data is transferred to main memory whether or not the interrupt task can execute. the dma channel can be set to interrupt immediately on receipt of data by setting the interrupt (int) and terminal count (tc) bits in the gdxcon0 register. the interrupt task is then a relatively low priority because it does not have to pull the characters out of the uart before they are overwritten by new data. (the effective uart fifo size has been increased by the dma buffer size.) when the interrupt task has finished processing all the data in the circular buffer (its read pointer is equal to the destination address), the interrupt can set tc to cause another interrupt as soon as additional characters arrive. processing the received data within a low-priority interrupt routine means that flow-control information, such as xons and xoffs, may not be seen as quickly. to alleviate this condition, transmission can be done without using dma (e.g., from within the same interrupt routine, or by programming the interrupt code). in the latter, the interrupt code could program the transfer count (gdxtc) register to send a maximum of n characters at a time, using dma, where '2 ? n' is a value that does not overrun the far side's receive fifo high-water mark. 8.5.6 general-purpose dma channels the am186cc/ch/cu microcontrollers each provide four general-purpose dma channels, which are similar to legacy am186 general-purpose dma channels. the four channels can be used for data transfers as shown in table 8-6. table 8-6 general-purpose dma data transfers source destination memory memory i/o internal peripherals: uart high-speed uart usb external peripherals i/o memory i/o internal peripherals: uart high-speed uart usb external peripherals internal peripherals: timer 2 1 uart high-speed uart usb notes: 1. timer 2 acts as a dma request source only; no data is transferred to or from timer 2. memory i/o external peripherals memory i/o cc cu cc cu dma controller 8-12 am186?cc/ch/cu microcontrollers users manual 8.5.6.1 general-purpose dma usage note: before using the general-purpose dma channels, ensure multiplexed signals are configured to reflect the use of dma and not other functionality (see table 8-1 on page 8-4). to use any of the four general-purpose dma channels, software must perform the following steps. note that while the source, destination, and count registers can be set in any order, the control registers must be set last. 1. specify the source address in the gdxsrcl and gdxsrch source address registers for the corresponding dma channel. 2. specify the destination address in the gdxdstl and gdxdsth destination address registers for the corresponding dma channel. 3. specify the transfer count in the gdxtc count register for the corresponding dma channel. 4. when performing a dma transfer to or from a peripheral, configure the dma before enabling the peripheral. for configuration of peripherals, see the applicable chapter. 5. configure the dma transfer options in the gdxcon0 and gdxcon1 control registers for the corresponding dma channel. 6. enable dma transfer in the gdxcon0 and gdxcon1 control registers for the corresponding dma channel. all dma registers except the gdxcon0 and gdxcon1 registers can be modified while the channel is operating. any changes made to these registers affect the current dma transfer. 8.5.6.2 general-purpose dma cycle the four general-purpose dma channels on the am186cc/ch/cu microcontrollers are completely interchangeable, and the register sets are identical. from the programmer's point of view, a dma cycle proceeds as follows: 1. the dma channel receives a dma request. each dma channel can service requests from timer 2, an external peripheral, or the internal uarts. dma channels on the am186cc and am186cu microcontrollers can also service requests from the usb peripheral controller. dma channels can also be set to unsynchronized, which causes the drq to be continuously asserted. this is used for memory-to-memory transfers. 2. the dma controller reads a byte or word from the programmed source address, which can be in i/o space or in memory, and then writes that byte or word to the programmed destination address, which can also be in i/o space or memory. unless the channel is set to unsynchronized or to accept requests from timer 2, the channel should be programmed so that either reading from the source or writing to the destination clears the request. for example, reading from the serial port receive data (sprxd) register clears a uart receive dma request. 3. the source and destination address pointers are then adjusted by independently programmable amounts. the adjustment increment for each pointer can be 0 (e.g., for a peripheral address that does not change), +1, +2, C1, or C2. (unpredictable results may occur when the transfer size is a word (two bytes) and the adjustment increment is 1 or C1; when the transfer size is one byte and the adjustment increment is +2 or C2, the high byte is ignored.) to implement circular buffers, the pointers can also wrap on 1-, 2-, 4-, 8-, 16-, 32-, or 64-kbyte boundaries. cu cc dma controller am186?cc/ch/cu microcontrollers users manual 8-13 4. if the gdxtc register is non-zero, it decrements. 5. if the gdxtc register became zero and either the terminal count (tc) bit is set or the transfer type is unsynchronized, the start/stop (st) bit is reset, and further dma requests on that channel are ignored. 6. if the gd x tc register became zero and the interrupt (int) bit is set, an interrupt request is generated. this action is independent of whether the tc bit is set. an entire sequence of dma cycles is initiated by setting the st bit. this bit can be set manually at any time, and is also set automatically by any write to the gdxtc register when the auto start (ast) bit is set. setting the st bit initiates a sequence of dma transactions if one of the following is true: n the gdxtc register is non-zero. n the tc bit is 0 and the transfer type is source or destination synchronized. if neither of these conditions are met, hardware resets the st bit without executing any dma transfers. otherwise, the st bit is reset by the hardware after executing one or more transfers as discussed in the previous dma cycle description. if a transfer is synchronized and the tc bit is 0, dma transfers continue as long as dma requests are being made until the st bit is manually cleared. this mode is typically used with the address wrap option to implement circular buffers (see using buffer queues or circular buffers on page 8-20). 8.5.6.3 general-purpose dma transfer suspension the following conditions suspend general-purpose dma transfers: n deassertion of drq n a bus hold condition n a refresh cycle by an nmi/watchdog timer interrupt n a pending dma request of equal or higher priority n the dhlt bit in the dmahlt register set to 1 by an nmi or by software 8.5.6.4 general-purpose dma source and destination addresses each general-purpose dma channel has a 20-bit source address and a 20-bit destination address. the 20-bit addresses are split over two source registers (gdxsrcl and gdxsrch) and two destination registers (gdxdstl and gdxdsth), with the four most significant bits (ad19Cad16) going into a separate register from the 16 low-order bits (ad15Cad0). the address is specified as a 20-bit linear address, not as a segment:offset pair. for example, for the segment c000h and offset 1000h, the linear address would be: (c000h x 16) + 1000h = c1000h; therefore, the low register = 1000h and the high register = 0ch. to use a dma channel, software must initialize all four address registers for that channel. the addresses can be individually incremented or decremented after each transfer. for more information, see incrementing or decrementing addresses on page 8-15. the source and destination addresses can each be in either memory space or i/o space. this is specified by programming the sm/io bit in the gdxcon1 register. the ad19Cad16 bits are ignored when the address is in i/o space. because the dma channels can perform transfers to or from odd addresses, there is no restriction on values for the destination and source address registers. higher transfer rates can be achieved if all word transfers are performed to and from even addresses so that accesses can occur in single 16-bit bus dma controller 8-14 am186?cc/ch/cu microcontrollers users manual cycles. word transfers to 8-bit address spaces are supported only when the source decrement or increment is 2 bytes. the am186cc/ch/cu microcontrollers have the added feature of being able to transfer by dma to and from the uart and high-speed uart. the am186cc and am186cu microcontrollers can also transfer by dma to and from usb peripherals. transfering between dma and peripherals is accomplished by programming the dma controller to perform transfers between a data buffer (located either in memory or i/o space) and the peripheral data register. it is important to note that when a dma channel is in use by a peripheral, the corresponding external dma request signal is deactivated. for a discussion of using dma and the on-chip peripherals, see selecting dma request sources on page 8-15. 8.5.6.5 general-purpose dma terminal count each dma channel has a 16-bit transfer count (gdxtc) register. software must program the gdxtc register with the desired number of transfers and set the terminal count (tc) bit in the gdxcon0 register to 1 to enable terminal count. if terminal count is enabled, the channel performs the requested number of transfers, decrementing the value in the gdxtc register after each transfer. when the count reaches zero, the dma transfer terminates. if the tc bit is 0, the dma controller decrements the value of gdxtc after each transfer but does not terminate the transfer when the count reaches zero. the gdxtc register wraps back to its maximum value and continues decrementing. if the current transfer is an unsynchronized transfer, dma terminates when the count reaches zero. if the auto start (ast) bit in the gdxcon0 register is set, dma resumes transferring every time the gdxtc register is reloaded with a new value. when a channel is connected to a usb transmit endpoint, the am186cc or am186cu microcontroller generates a signal internally when the terminal count is reached. the usb peripheral can use this signal to signal the end-of-packet on a transmit. 8.5.6.6 general-purpose dma channel operations the general-purpose dma control registers (gdxcon0 and gdxcon1) determine the dma channel operations. these registers specify the following options: n the relative priority of the dma channel with respect to other dma channels (see dma priority on page 8-9) n whether the dma resumes a transfer every time the count register is reloaded with a new value (see general-purpose dma terminal count on page 8-14) n whether the source or destination address is in memory or i/o space (see general- purpose dma source and destination addresses on page 8-13) n if an interrupt is generated when the transfer count is reached (see generating interrupts on page 8-15) n whether bytes or words are transferred (see transferring bytes or words on page 8-15) n whether the source or destination address is incremented, decremented, or maintained constant after each transfer (see incrementing or decrementing addresses on page 8-15) n the dma request source for the channel (see selecting dma request sources on page 8-15) cu cc cu cc dma controller am186?cc/ch/cu microcontrollers users manual 8-15 n the dma synchronization for the channel (setting synchronization on page 8-17) n whether dma transfers use buffer queues or circular buffers (see using buffer queues or circular buffers on page 8-20) 8.5.6.6.1 generating interrupts the general-purpose dma channels can generate an interrupt request when the terminal count value in the gdxtc register reaches 0. to program this feature, set the int bit in the gdxcon0 register to 1. 8.5.6.6.2 transferring bytes or words the ts bit in the gdxcon0 register can enable either byte or word transfers. 8.5.6.6.3 incrementing or decrementing addresses the source and destination addresses can increment or decrement after each transfer, or remain constant. specify the action with the sinc and dinc bits in the gd x con1 register. the increment or decrement factor of the source and destination addresses are programmed independently; however, both the source and destination have to be the same size. word transfers are only supported when the address is incremented or decremented by 2 (an increment by one causes unpredictable results). byte transfers can be incremented or decremented by 1 or 2. when a byte transfer is incremented or decremented by 2, the high byte is ignored. because the dma controller stores addresses as 20-bit linear values, there are no segment restrictions on the address increment and decrement. however, when using the circular buffer feature, the address boundary is limited to the size of the buffer. for example, when using a 1-kbyte circular buffer, the address has to start at a 1-kbyte boundary. for more information, see using buffer queues or circular buffers on page 8-20. 8.5.6.6.4 selecting dma request sources the dsel bit field in the gdxcon0 register sets the dma request source for that channel. as shown in figure 8-3, the dma request source can be an external drq signal, timer 2, uart receiver, uart transmitter, high-speed uart receiver, or high-speed uart transmitter. the am186cc and am186cu microcontrollers also support usb endpoints a, b, c, or d as request sources. each usb endpoint can be configured either for receive or transmit. in addition to setting the dma request source, the dsel bit field also selects the synchronization type (see setting synchronization on page 8-17). cu cc dma controller 8-16 am186?cc/ch/cu microcontrollers users manual figure 8-3 dma request sources dma request from timer 2 the gdxcon0 register can configure a dma channel to accept the output of timer 2 as a drq signal to generate periodic data transfers. note that this feature generates a drq periodicallyeven if there is no data. to use this feature, software should program timer 2 with the t2con register for continuous modeto reach the maximum count and start counting again. each time the timer reaches the maximum count, it generates a single drq. the dma controller latches the timer 2 drq signal to guarantee that the dma channel does not miss the drq if the bus is not immediately available (e.g., if a higher priority dma has control of the bus). if a second timer 2 drq is generated before the first request is serviced, the second request is lost. dma request from uarts transfers between the dma and the uarts are accomplished by programming the gdxcon0 register to perform transfers between a data buffer (located either in memory or i/o space) and a serial port data register (sptxd, sprxd, hsptxd, or hsprxd). note: using a dma channel with a uart deactivates the corresponding external dma request signal. for dma to the uart or high-speed uart, specify the following configuration details for the dma by writing the address of the register into the gdxdstl and gdxdsth registers: the transmit data register (sptxd or hsptxd) address; either i/o-mapped or memory- mapped; as a byte destination, or word destination if using extended writes. the destination address (the address of the transmit data register) should remain constant throughout the dma operation. for dma from the uart or high-speed uart, specify the following configuration details for the dma by writing the address of the register into the gdxsrcl and gdxsrch registers: the receive data register (sprxd or hsprxd) address; either i/o-mapped or memory-mapped; as a byte source, or word source if using extended writes. the source address (the address of the receive data register) should remain constant throughout the dma operation. uart receiver uart transmitter high-speed uart receiver high-speed uart transmitter memory or i/o usb endpoint a usb endpoint b usb endpoint c usb endpoint d drq external drq signal unsynchronized transfer dma drq source select timer 2 (latched) cu cc dma controller am186?cc/ch/cu microcontrollers users manual 8-17 dma request from usb because usb can use either general-purpose dma or smartdma channels, this is discussed separately in dma and usb on page 8-43. 8.5.6.6.5 setting synchronization the dsel bit field in the gdxcon0 register sets the dma request source for that channel (see selecting dma request sources on page 8-15). unlike prior am186 parts, this bit also sets the synchronization. general-purpose dma transfers can be unsynchronized, source-synchronized, or destination-synchronized. the source or destination device implies the synchronization type as shown in table 8-7. dma synchronization affects the behavior of the dma operation and system performance as a whole. all dma transfers observe the programmed ready and wait-state conditions for any chip select active for that cycle. drq must be deasserted before the end of the dma transfer to prevent another dma cycle from occurring. the timing for the required deassertion depends on whether the transfer is source-synchronized or destination-synchronized. unsynchronized transfers for unsynchronized dma transfers, the drq signal is internally tied high. when initiated, an unsynchronized dma transfer begins immediately and consumes all bus cycles until the terminal count value in the gdxtc register reaches 0. unsynchronized dma is generally used for copying data between memory locations, between i/o locations, or between memory and i/o locations. for example, unsynchronized dma can initialize ram during start-up. source-synchronized transfers source-synchronized dma transfers require either an internally generated drq (e.g., from a uart receiver) or an external device that asserts the associated external drq signal for table 8-7 general-purpose dma request source and synchronization dma request source synchronization type memory or i/o unsynchronized timer 2 source uart receiver source uart transmitter destination high-speed uart receiver source high-speed uart transmitter destination usb requset sources usb endpoint a receiver source usb endpoint a transmitter destination usb endpoint b receiver source usb endpoint b transmitter destination usb endpoint c receiver source usb endpoint c transmitter destination usb endpoint d receiver source usb endpoint d transmitter destination cu cc cc cu dma controller 8-18 am186?cc/ch/cu microcontrollers users manual a general-purpose dma channel. in source synchronization, the device providing the data asserts the dma request. figure 8-4 shows a typical source-synchronized dma transfer. when an external device is asserting drq, the request must be deasserted at least four clock cycles before the end of the transfer (at t1 of the deposit phase) to prevent another transfer from taking place. if more transfers are not required, a source-synchronized transfer allows the source device at least three clock cycles from the time it is acknowledged to deassert its drq line. like unsynchronized dma transfers, source-synchronized dma transfers have the capability of consuming all bus cycles if the drq remains asserted for multiple transfers. an example of this would be the emptying of a fifo. figure 8-4 source-synchronized general-purpose dma transfers destination-synchronized transfers destination-synchronized dma transfers require either an internally generated drq (e.g., from a uart transmitter), or an external device that asserts the associated external drq signal for a general-purpose channel. in destination synchronization, the device receiving the data asserts the dma request. figure 8-5 shows a typical destination-synchronized dma transfer. the dma controller does not sample the drq line for a channel until four cycles after the end of the write phase of a destination-synchronized dma transfer. this delay allows the external device sufficient time to remove its request if it does not want another transfer. the delay also allows other devices access to the bus, including instruction or data fetches by the processor and other dma transfers (including transfers by lower priority dma requests). if another device starts a bus cycle during the dma idle cycles, the entire bus cycle completes before giving the bus back to the dma. if no other bus activity is initiated, another dma cycle begins. because the dma controller relinquishes the bus after every destination-synchronized transfer, the cpu can initiate a bus cycle. as a result, a complete bus cycle is often inserted t1 t2 t3 t4 t1 t2 t3 t4 clkout drq (first case) drq (second case) fetch cycle fetch cycle 1 2 notes: 1. this source-synchronized transfer is not followed immediately by another dma transfer, because drq is deasserted at least four clock cycles before the end of the transfer. 2. this source-synchronized transfer is immediately followed by another dma transfer, because drq is not deasserted soon enough. dma controller am186?cc/ch/cu microcontrollers users manual 8-19 between destination-synchronized transfers. table 8-8 shows the maximum dma transfer rates based on the different synchronization strategies. figure 8-5 destination-synchronized general-purpose dma transfers deasserting drq in externally synchronized transfers, drq1 or drq0 must be deasserted before the end of the dma transfer to prevent another dma cycle from occurring. the timing for the required deassertion depends on whether the transfer is source-synchronized or destination- synchronized. a dma request is not acknowledged from the same source for four processor clock cycles after the end of the deposit cycle. in a source-synchronized dma transfer, the drq signal must be deasserted at least four clocks before the end of the transfer. if more transfers are not required, a source-synchronized transfer allows the source device at least three clock cycles from the time it is acknowledged to deassert its drq line. for more information, see dma acknowledge on page 8-10. table 8-8 maximum dma transfer rates synchronization type maximum dma transfer rate (mbytes/s) 50 mhz 40 mhz 25 mhz unsynchronized 12.5 10 6.25 source-synchronized 12.5 10 6.25 destination-synchronized (cpu needs bus) 8.33 5 3.125 destination-synchronized (cpu does not need bus) 10.0 5 3.125 t1 t2 t3 t4 t1 t2 t3 t4 clkout drq (first case) drq (second case) fetch cycle deposit cycle 1 2 ti ti notes: 1. this destination-synchronized transfer is not followed immediately by another dma transfer, because drq is deasserted during the four idle states. 2. this destination-synchronized transfer is immediately followed by another dma transfer, because drq is not deasserted soon enough. ti ti t1 dma controller 8-20 am186?cc/ch/cu microcontrollers users manual a destination-synchronized transfer differs from a source-synchronized transfer in that the four cycle delay allows the destination device to deassert its drq signal four clocks before another request is latched. without this delay, the destination device would not have time to deassert its drq signal. because of the four extra cycles, a destination-synchronized dma channel allows other bus masters to take the bus during the idle states. 8.5.6.6.6 using buffer queues or circular buffers note: this discussion assumes the channel is using a memory buffer (i.e., that the source or destination address is programmed to increment or decrement). if the address is programmed to remain constant, no memory buffer is in use, and neither buffer queues nor circular buffers are used. see incrementing or decrementing addresses on page 8-15 for more information. the gdxcon1 register contains two fields that specify whether the source and/or destination addresses for that dma channel should wrap when the addresses reach a programmed boundary. these fields are programmed independently; wrapping could be enabled for one address and not for the other. when wrapping is disabled, the memory buffer is treated as a linear array. this is typically called a buffer queue . with a buffer queue, data is written/read to sequential byte or word addresses until a terminal count is reached. the dma should be programmed to terminate when the terminal count is reached, or data may be written past the end of the buffer. when wrapping is enabled, the memory buffer is treated as a circular buffer (sometimes called a ring buffer ). in this case, data is written/read to sequential byte or word addresses until the programmed buffer length is reached, at which point the address is reset to its initial value; data is never written outside the programmed buffer space. circular buffers can be programmed to be 1, 2, 4, 8, 16, 32, or 64 kbytes in length, and must be aligned to an address which is a multiple of the programmed size. the use of a circular buffer reduces the overhead required in programming the dma channel and may result in more efficient use of the transmitting or receiving device. however, in the case where a circular buffer is being used to receive data, software must ensure that valid received data is removed from the buffer before it is overwritten by the dma controller on the next pass. conversely, for transmit circular buffers, software must write valid transmit data into the buffer before that buffer address is read by the dma controller. to avoid overwriting data in a circular buffer, compare the source address with the buffer address. for example, the address contained in a dma channel's source address registers is the address of the next byte of data to be transmitted. data that is logically between this address and the buffer address being written to by software (in a circular fashion) has not yet been transmitted. if the source address registers contain the address xxxx0050 when software is writing to address xxxx0150, then the addresses from xxxx0050 through xxx0149 contain valid data for transmission. addresses outside of this range, but within the buffer, do not contain valid data. this may be data that has already been transmitted or may be addresses that have never been written. for string data or other data which is naturally represented as consecutive bytes or words in memory, using circular buffers involves additional overhead because the data must be moved between its storage location and the circular buffer. for these data types, a buffer queue may be a more efficient solution. dma controller am186?cc/ch/cu microcontrollers users manual 8-21 example of using buffer queues and circular buffers with the uarts note: this section discusses implementation tradeoffs for using the general-purpose dma channels. to have a concrete system to discuss, the integrated uart and high-speed uart are used as examples, but much of this information is applicable to using the general- purpose dma channels with other peripherals as well. in general, there are two distinct ways that general-purpose dma can be used: buffer queues and circular buffers. these two techniques are discussed and contrasted below. in addition, these two methods can be mixed (e.g., queues of messages for transmit and circular buffers for receive). a careful analysis of the final system is required to determine the best method to use. many systems, especially those communicating with other equipment rather than with human beings in interactive mode, transmit and receive messages in large blocks. these messages can be forwarded to a host pc through the usb interface, or forwarded through an isdn line or other wan setup using hdlc. with this sort of message protocol, it may be advantageous under some circumstances to perform a dma transfer directly to or from a queue of buffers, rather than to or from a single circular buffer per direction. buffer queues are a viable way to transfer data to and from some devices with general- purpose dma. however, buffer queues are only useful for dma with the uarts under very special circumstances. the primary advantage to using dma transfer straight from a queue of buffers is the reduction of data motion. transmission is relatively straightforward: the dma channel is programmed with the correct source address and transfer count for each buffer; and the dma channel is set up to stop transmitting and to interrupt when the end of the buffer is reached. when the interrupt occurs, the buffer is freed, and the next buffer is set up to be transferred out using dma. reception is more difficult because it is not always known up front exactly how long the incoming message is. even if the message size is fixed, line errors can corrupt the perceived length. for both reception and transmission, issues such as compression, transparency, and crc generation and checking mean that software must usually examine each character individually. in this case, using a circular buffer is generally the best way to use dma with a uart (because each character is being read by software anyway, and the number of characters to be transmitted is different than the number of characters in the original buffer), although dma is not necessarily the best way to transfer data to and from the uart. the determination of whether to use dma at all for this sort of protocol processing is dependent on system loading and maximum uart baud rate. if cpu cycles are at a premium (e.g., for data compression), it may be worthwhile to use dma. many uart serial drivers use circular buffers for temporary storage of incoming and outgoing characters. the primary drawback to using a circular buffer is that it doubles the bus bandwidth required to handle each character received or transmitted. for example, if a string is written out to a serial port, using a circular buffer requires four bus transactions for each character (read it from the string, write it to the buffer, read it from the buffer, write it to the transmit port), whereas without the buffer, two transactions would suffice (read the character from the string, write it to the transmit port). nevertheless, circular buffers are popular because the alternative often requires more coding and is usually more error-prone (e.g., a buffer containing a string could inadvertently be reused before the string is completely transmitted). for this reason, the am 186cc/ch/cu microcontrollers dma has excellent circular buffer support. with the general-purpose dma channels, this is achieved by setting bits in the gdxcon1 register to a nonzero value to select a buffer size between 1 and 64 kbytes. dma controller 8-22 am186?cc/ch/cu microcontrollers users manual software must ensure that this buffer is aligned on a multiple of its size. this is easily done for statically allocated buffers with a good linker/locator; for dynamically allocated buffers, the software must waste the size of one buffer. this waste can usually be reduced or eliminated by allocating and deallocating additional buffers; this is highly dependent on the operating system and memory allocation library. transmitting using dma and circular buffers is easy and does not require interrupt support. note that using dma for transmission for the uart is not required for data integrity reasons, so dma should only be used for uart transmissions if one of the following applies: n cpu throughput can be improved by reducing the time spent in the uart interrupt handler. n transmission throughput can be improved by reducing the latency between transmitted characters. note that it is easy to measure intercharacter latency to determine the maximum possible improvement available by improving uart transmission. table 8-9 gives typical register values for using circular buffers with the uarts. table 8-9 example register settings for uarts and circular buffers general-purpose dma register bit(s) in register value for transmit dma value for receive dma gdxcon0 (control 0) st (start/stop) clear (is set by load of gdxtc register) set after all other fields and uart set correctly ast (auto start) set clear tc (terminal count) set typically clear int (interrupt) clear for single-tasking; set for multitasking set p (relative priority) depends on rest of system depends on rest of system; higher than transmit ts (transfer size) 0 for 8 bit, 1 for 9 bit 0 for 8 bit, 1 for 9 bit or extended status dsel (dma request select) (high-speed) uart transmitter (high-speed) uart receiver gdxcon (control 1) sm/io (source address space select) set (memory) clear (i/o) saw (source address wrap) set to size of buffer clear sinc (source increment) 1 for 8 bit, 2 for 9 bit 0 dm/io (destination address space select) clear (i/o) set (memory) daw (destination address wrap) clear set to size of buffer dinc (destination increment) 0 1 for 8 bit, 2 for 9 bit or extended status gdxsrcl (source address low) dsa[15C0] buffer address mod 64k (h)sprxd dma controller am186?cc/ch/cu microcontrollers users manual 8-23 when the dma channel is initialized as shown in table 8-9, transmitting a string is performed as follows: 1. copy the string from the source to the buffer at the current write pointer position, being careful to take buffer wrap into account, and being careful not to overwrite data already in the buffer which is not yet transmitted. (whether or not data has been transmitted can be easily determined by reading the dma channel's source address register and comparing it against the write pointer position.) calculate a new write pointer position, and save it in memory to use for subsequent writes. 2. stop the dma (reset the st bit) to ensure that the transfer count is stable. 3. add the length of the new string to the transfer count (gdxtc) register. a read/modify/ write cycle adjusts the gdxtc register, and the write to the register automatically restarts the dma (if the ast bit is set). interrupts are required for transmit under the following conditions: n if the xon/xoff protocol is used, the dma must be shut off to transmit flow control characters, and also to stop transmitting when an xoff is received. one way this protocol could work is that when dma is to be stopped, the ast and st bits can be reset; when dma is to be restarted, both these bits can be set again. if this technique is used, steps 2 and 3 above (stopping dma and updating transfer count) should be performed as an atomic operation (i.e., with interrupts disabled) to avoid conflicts with the xon/xoff interrupt handler. n if a multitasking system is used, an attempt to write too much data to the buffer should write as much as possible, and then block the task performing the write until additional space is available. in this case, the gdxtc register should not be programmed with the actual count of characters in the buffer, but instead be programmed with the lesser of the actual count and the amount of space to wait for before restarting the blocked task. also, the interrupt bit should be set. when the interrupt occurs, the transfer count should immediately be reprogrammed to the actual remaining buffer count to avoid delay in transmission, and the blocked task should be marked as ready to run. reception using circular buffers for the uart, dma reception using a circular buffer is potentially more useful than transmission because transferring received characters into a circular buffer can help improve data integrity. (characters are never lost due to interrupt latency.) like basic transmission, basic reception using a circular buffer is simple. software maintains a read pointer into the buffer and can dynamically determine the number of characters available for reading at any time by reading the destination address, subtracting the read gdxsrch (source address high) dsa[19C16] buffer address div 64k 0 gdxdstl (destination address low) dda[15C0] (h)sptxd buffer address mod 64k gdxdsth (destination address high) dda[19C16] 0 buffer address div 64k gdxtc (transfer count) tc set to total string length whenever writes performed set to high-water mark table 8-9 example register settings for uarts and circular buffers (continued) general-purpose dma register bit(s) in register value for transmit dma value for receive dma dma controller 8-24 am186?cc/ch/cu microcontrollers users manual pointer from it, and dividing the result by the buffer size. the remainder of this division is the number of bytes available for reading. the difficulty again revolves around multitasking and flow control, with the added problem of error handling. receive xon/xoff flow control xon/xoff flow control with dma is problematic because, in general, the received flow control characters should not be stored in the buffer, and also because the characters should typically be acted on immediately. this may make dma impractical for implementing xon/xoff flow control with the uart. the high-speed uart can be programmed to stop using dma and interrupt the cpu whenever a flow control character arrives, so that an interrupt routine can act on the flow-control character and then restart the dma operation. note that baud rate, system latency, and the depth of the fifo must be considered when determining if this is practical for a given implementation. in addition to detecting and acting on flow-control characters in the data stream, the receiving task must also detect when the circular buffer is getting full so that an xoff can be sent. this can be accomplished by programming the transfer count register with a value that is the current room available in the buffer minus a constant high-water mark, and setting the int bit, but not the tc bit in the gdxcon0 register. this causes the dma to interrupt when there is room (buffer size minus high-water mark) in the buffer, and an xoff can be sent. the value chosen for the high-water mark should take into account far-end latency in dealing with an xoff, plus latency associated with sending the xoff through the high- speed uart transmit fifo, if it is enabled. receive hardware flow control hardware flow control is simple if the connected device performs true hardware flow control (i.e., stops transmitting on the next character boundary when rtr is dropped). some uarts and systems perform pseudo-hardware flow control. in these uarts, the flow control signal can cause an interrupt, but may not stop characters already queued to go out. in this case, the high-speed uart's receive fifo may be sufficient to guarantee that overruns do not occur. if the uart is being used, or if the high-speed uart's receive fifo is not large enough to guarantee that the other side will stop quickly enough, then rtr should be performed using a pio, and an algorithm similar to the one described for receive xon/xoff control should be used, so that the far side is requested to stop sending before the dma buffer is actually full. the fifo threshold is one half of the fifo depth and is not programmable. if the attached device is capable of real hardware flow control, then the tc bit in the gdxcon0 register can be set, and the transfer count register can be programmed with the amount of room left in the buffer. when dma ceases, the hardware flow control signal is automatically asserted. dma controller am186?cc/ch/cu microcontrollers users manual 8-25 receive multitasking in a single-tasking system, received characters are held in the circular buffer until higher- level code is ready for them. in a multitasking system, it may be desirable for receipt of characters to cause an interrupt to signal that a task switch should take place. when dma is used with one of the uarts on the am186cc/ch/cu microcontrollers, the hardware is typically programmed to cause interrupts under these two conditions: n after a programmed number of characters have been received. to do this, the programmed transfer count is usually the lesser of this desired number and the number required to implement proper flow control. n when no characters have been received for a certain period of time (signifying that the other end has probably finished transmitting a message). this is accomplished by interrupting on the uart idled bit in the (h)spstat register, which causes an interrupt when 40 bit times have gone by without detecting a start bit. receive error processing several kinds of errors and exceptional conditions can occur when receiving asynchronous character data. breaks, parity errors, and framing errors indicate an exceptional external condition. overrun errors indicate that data has been lost due to system latency. a character match interrupt (high-speed uart only) can indicate that an xon or xoff has been received. the am186cc/ch/cu microcontrollers offer great flexibility in dealing with these exceptions. if the exdrd bit in the uart's control 1 register is set, and the dma is set up to transfer a word for every character, exceptions can be stored in the circular buffer along with the character that caused them. if the exdrd bit is reset, exceptions that cause interrupts cause dma activity to stop until an interrupt task services the exception. the decision of whether to set or clear the exdrd bit depends on the intended usage. if the target baud rate is high relative to system loading, setting the exdrd bit can prevent the loss of data due to interrupt latency. this is especially true when using the uart, or when using the high-speed uart without the fifo. if break or address bit information is to be stored with the character for later retrieval, setting the exdrd bit is appropriate. setting this bit can complicate system software, especially if xon/xoff flow control is used, because the flow control characters are stored in the circular buffer. the system software must find the character and perform the correct action immediately, and then ignore the character when reading data out of the buffer later. when using the fifo on the high-speed uart, these exceptions (break, parity error, framing error, address bit, overrun error, and character match) are placed in the fifo and move with the associated data so that the software can match the exception with the correct character. this means that a system programming error that keeps data from being pulled out of the fifo (e.g., misprogramming of the dma) may keep interrupts from ever occurring. for this reason, the high-speed uart has an additional overrun error-immediate (oerim) interrupt bit that is not placed in the fifo. software can monitor or interrupt on oerim to detect and correct this sort of system programming error. small or misaligned circular buffers if a circular buffer is smaller than 1k, is not aligned on a multiple of its size, or the size is not a power of 2, the address wrap features of the dma are not available. the dma can still be used to implement a circular buffer, but it requires more programming effort, and the required interrupt could introduce unacceptable latency into the system. system software must always use interrupts, set the tc bit, and carefully program the transfer count register dma controller 8-26 am186?cc/ch/cu microcontrollers users manual so that the address never exceeds the boundary of the buffer. software must manually wrap the buffer address back to the start of the buffer whenever an interrupt signifies the end of the buffer. this is not too burdensome for uart transmit buffers because there is no hard latency requirement for asynchronous transmission, but this could be a problem for receive buffers if the interrupt latency could cause characters to be missed. 8.5.7 smartdma channels the am186cc/ch/cu microcontrollers each contain smartdma channels, compatible with the dma in the amd am79c90 c-lance (local area network controller for ethernet). this lance-compatible buffer descriptor ring interface provides a method for transmission and reception of data across multiple memory buffers. the ring descriptor interface also provides a method for reporting status on multiple received and transmitted packets while ensuring that status information is always correctly linked with the associated data. unlike the general-purpose dma channels, which can be used for memory-to-memory or i/o-to-i/o transfers, the smartdma channels are highly specialized. these channels must be used in pairs. each pair consists of a transmit channel and a receive channel. the transmit channels transfer data from memory to a transmitting device (such as an hdlc transmitter). receive channels transfer data from a receiving device (such as an hdlc receiver) to memory. four of the eight smartdma channels (two pairs) in the am186cc microcontroller are dedicated for use with the on-board hdlc channels. the remaining four smartdma channels (two pairs) can support either the third or fourth hdlc channel or usb endpoints a, b, c, or d. the four smartdma channels (two pairs), sdma0 and sdma1, in the am186ch hdlc microcontroller support the two on-board hdlc channels. the four smartdma channels (two pairs), sdma2 and sdma3, in the am186cu usb microcontroller support usb endpoints a, b, c, or d. this section describes these smartdma channels. 8.5.7.1 smartdma channels introduction with a traditional dma controller, such as the general-purpose dma, the typical mode of operation is to dma transfer a buffer of information (either filling a receive buffer, or emptying a transmit buffer) and program the dma controller to interrupt the cpu when the end of the buffer is reached. however, if the data rate is high relative to system loading and interrupt latency, data could be lost before the interrupt service routine reinitializes the dma controller to point to the next buffer. for some peripherals, such as uarts, this problem is easily solved by the ability of the general-purpose dma controller to manage a circular buffer. if such a circular buffer is managed correctly, dma is never halted to wait on cpu interrupt activity. a circular buffer does not work as well for packet-oriented communications such as hdlc and usb because of the requirement to delineate packet boundaries. also, in a typical system, each packet can be routed to a different destination, so the data would have to be copied out of the circular buffer and into another peripherals circular buffer. smartdma channels solve these problems by maintaining a circular queue of buffer descriptorsa descriptor ring rather than a circular data buffer. the hardware itself updates a buffer descriptor when a full buffer is transferred, then automatically fetches the next descriptor and starts transferring data to the new buffer. because the hardware cc ch cu dma controller am186?cc/ch/cu microcontrollers users manual 8-27 performs this operation without software intervention, the latency is significantly lower than if an interrupt task performed the same operation. software must still read and write the buffer descriptors, but the latency requirements are greatly relaxed because multiple descriptors are queued at one time. the software can take, on average, the time it takes to transmit or receive a buffer to update each descriptor, and software can increase allowable latency even more by updating several descriptors at the same time. 8.5.7.2 smartdma channel request source and synchronization the smartdma channels support only specific, predetermined request sources. these sources in turn determine the synchronization type for each channel. synchronization type for the smartdma channels is not programmable. the synchronization types are shown in table 8-10, table 8-11, and table 8-12. the memory buffer addresses are taken from the buffer descriptor ring, as explained in smartdma channel memory overview on page 8-28. in the am186cc microcontroller, smartdma channel 2 and smartdma channel 3 provide the dsel bit in the sdxcon control register for selecting between the hdlc and usb request source. the address of the peripheral does not need to be programmed into the smartdma channel because these devices have an internal interface to the associated smartdma channel. in the am186cu usb microcontroller, the dsel bit must be programmed correctly for usb support. the smartdma channels support only byte transfers. the data is written or read from sequential byte addresses in the memory buffers. table 8-10 am186cc smartdma channel request source and synchronization smartdma channel direction source destination synchronization 0 transmit memory buffer hdlc a transmit fifo destination receive hdlc a receive fifo memory buffer source 1 transmit memory buffer hdlc b transmit fifo destination receive hdlc b receive fifo memory buffer source 2 transmit memory buffer hdlc c transmit fifo or usb endpoint b transmit fifo destination receive hdlc c receive fifo or usb endpoint a receive fifo memory buffer source 3 transmit memory buffer hdlc d transmit fifo or usb endpoint d transmit fifo destination receive hdlc d receive fifo or usb endpoint c receive fifo memory buffer source cc cu cc dma controller 8-28 am186?cc/ch/cu microcontrollers users manual 8.5.7.3 smartdma channel memory overview figure 8-6 on page 8-29 and figure 8-7 on page 8-30 illustrate how smartdma channels use memory. each smartdma channel (both transmit and receive) has two registers that contain the base descriptor ring address and the number of entries in the descriptor ring. (a descriptor ring is merely a block of memory that the cpu and software use to control and describe data buffers.) there are two descriptor rings for each smartdma channel: one for transmit and one for receive. the sdxtrcal and sdxrrcal registers contain the three bits that encode the number of entries in the ring, and 12 bits (bits 15C4) to determine the 12 low address bits of the descriptor ring address, which is the start location in memory of the buffer descriptor ring. the sdxtrah and sdxrrah registers contain the four high bits (19C16) of the addresses. because the base address of the ring must be paragraph aligned (aligned to a 16-byte physical memory boundary), address bits 3C0 are always zeros. the address is specified as a 20-bit linear address, not as a segment:offset pair. for example, for the segment c000h and offset 1000h, the linear address would be: (c000h x 16) + 1000h = c1000h; therefore, the low register = 1000h and the high register = 0ch. the size of the transmit and receive descriptor rings (the ring count) is independently programmable to 1, 2, 4, 8, 16, 32, 64, or 128 descriptors. even when the ring size is set to 1, that entry is still interpreted as a descriptor, not as the memory buffer itself. each entry in the descriptor ring is composed of a 20-bit linear address for a buffer, an owner semaphore bit, a frame-start indicator bit, a frame-end indicator bit, a terminal count interrupt bit, and a 15-bit buffer byte count. other fields are also present but are dependent on whether the descriptor is in a transmit or receive descriptor ring. the address in each descriptor ring entry contains the address of the data buffer pointed to by that entry. note that the hdlc and usb peripheral controllers transmit data packets, which contain a block of data between a start and end indicator. a packet (e.g., all the hdlc data between two hdlc flag bytes) can be broken up into multiple buffers, but a buffer cannot contain data for different packets. table 8-11 am186ch smartdma channel request source and synchronization smartdma channel direction source destination synchronization 0 transmit memory buffer hdlc a transmit fifo destination receive hdlc a receive fifo memory buffer source 1 transmit memory buffer hdlc b transmit fifo destination receive hdlc b receive fifo memory buffer source table 8-12 am186cu smartdma channel request source and synchronization smartdma channel direction source destination synchronization 2 transmit memory buffer usb endpoint b transmit fifo destination receive usb endpoint a receive fifo memory buffer source 3 transmit memory buffer usb endpoint d transmit fifo destination receive usb endpoint c receive fifo memory buffer source ch cu dma controller am186?cc/ch/cu microcontrollers users manual 8-29 the owner semaphore (own) bit is a single-bit field in each buffer descriptor. this bit is set by software when the buffer is valideither it contains valid data for transmission or it is available to be overwritten by the receiver. the smartdma controller never sets the own bit. software must never clear the own bit while the smartdma controller is activethe software should first stop the dma operation by resetting the txst or rxst bit in the sdxcon register. (if the smartdma controller is already working on that buffer, clearing the own bit has no effect; if the smartdma controller was going to get the buffer, it would be in poll mode and wait until the buffer is available.) the smartdma controller clears the own bit when it releases control of the buffer. some systems may need to have dma transfer continue even if software has not kept up with the dma. this can be accomplished by setting the txs0 bit in sdxcon for the transmit dma channel or the rxs0 bit in sdxcon for the receive dma channel. setting these bits inhibits the associated smartdma channel from clearing the own bit after it is through processing a buffer. note: take care when setting these bits, because you may lose received data or transmit stale data. figure 8-6 smartdma channel descriptor ring example 1 2 3 4 4-entry descriptor ring memory own=0 own=1 own=1 own=0 software is processing here dma is processing here buffer 1 (packet x) buffer 2 (packet x) buffer 3 (packet x) buffer 4 (packet y) dma controller 8-30 am186?cc/ch/cu microcontrollers users manual figure 8-7 smartdma channel memory management figure 8-6 shows a descriptor ring with four entries. when own = 1, the smartdma channel owns the descriptor entry and can take data out or put data in the buffer. when own = 0, software owns the descriptor entry and the smartdma channel cannot access the buffer. this means in a transmit buffer, data is valid when own = 1; and in a receive buffer, data is valid when own = 0 (subject to any status error bit settings). descriptor ring entries are always accessed in order. in a transmit, the hardware always follows the software; in a receive, software follows the hardware. if a smartdma channel reaches a buffer whose own bit is not 1, the smartdma enters poll mode and waits for software to set the own bit. it does not advance past a buffer whose own bit is not set. keeping this in mind, the example in figure 8-6 indicates the following for a transmit or a receive. 8.5.7.3.1 transmit descriptor ring if figure 8-6 is a transmit descriptor ring, then software wrote the complete packet x (which spans buffers 1, 2, and 3 pointed to by descriptors 1, 2, and 3). after writing the complete packet, software set the own bit in each of the three descriptors. the own bits should be set in order, from the last descriptor in the packet to the first (3, then 2, then 1), to guarantee correct transmission of the packet. the channel has already transmitted the data from buffer 1 and is currently processing buffer 2. while packet x is being transmitted, software is writing data to buffer 4 for transmission of the next packet, packet y. smartdma channel transmit ring address registers (sdxtrcal and sdxtrah) transmit descriptor ring transmit buffer 1 address transmit descriptor ring address number of entries (n) in transmit buffer descriptor ring smartdma channel transmit ring count registers (sdxtrcal) transmit buffer 1 status/config transmit buffer 1 byte count transmit buffer 1(unused) transmit buffer 2 address transmit buffer 2 status/config transmit buffer 2 byte count transmit buffer 2(unused) transmit buffer n address transmit buffer n status/config transmit buffer n byte count transmit buffer n (unused) . . . transmit data buffer 1 transmit data buffer 2 transmit data buffer n transmit data buffer queue smartdma channel receive ring address registers (sdxrrcal and sdxrrah) receive descriptor ring receive buffer 1 address receive descriptor ring address number of entries (n) in receive buffer descriptor ring smartdma channel receive ring count registers (sdxrrcal) receive buffer 1 status/config receive buffer 1 byte count receive buffer 1 message count receive buffer 2 address receive buffer 2 status/config receive buffer 2 byte count receive buffer 2 message count receive buffer n address receive buffer n status/config receive buffer n byte count receive buffer n message count . . . receive data buffer 1 receive data buffer 2 receive data buffer n receive data buffer queue transmitter receiver dma controller am186?cc/ch/cu microcontrollers users manual 8-31 8.5.7.3.2 receive descriptor ring if figure 8-6 is a receive descriptor ring, then the own bit in the current buffer descriptor was 1 when the receive channel began to receive packet x. the packet was not completely received before reaching the terminal count for buffer 1, so the channel cleared the owner semaphore for descriptor 1, releasing it for processing by software, and advanced to 2 for continued reception of the packet. descriptor 3 has the own bit set, indicating that it is available for use by the receiver either for a continuation of packet x or for the next packet. software is currently processing the data in buffer 4 and will set the own bit in the descriptor when it has completed. 8.5.7.4 smartdma channel usage note: before using the smartdma channels, ensure multiplexed pins are configured to reflect the use of dma and not other functionality (see table 8-1 on page 8-4). to use any of the eight smartdma channels (four pairs), the following must be programmed. note that this must be done for both the transmitter and the receiver (because smartdma channels must be used in pairs) as well as for each channel pair used. the transmit and receive channels do not have to be enabled at the same time, but the smartdma channel should be initialized before the request source device is enabled. this allows the controller to fetch data about the initial receive and transmit buffers before receiving any drqs. in addition, because the smartdma channel works off of requests from the device, it is always safe to enable the dma before the device. enabling the device before the dma may result in data loss or an initial error condition being reported. 8.5.7.4.1 enabling the transmit channel to enable a smartdma transmit channel, software must perform the following tasks: 1. create the transmit buffer descriptor ring. 2. program the interrupt channel and configure the smartdma channel for interrupts. 3. add data buffers to the ring. 4. enable the transmit channel. create the transmit buffer descriptor ring 1. disable the transmit channel by clearing the txst bit in the sdxcon register to 0. 2. allocate the memory for the transmit buffer descriptor ring (see smartdma channel descriptor format on page 8-38 for the descriptor ring data structure). 3. clear the own bit for each descriptor to 0 (owned by software). 4. program the address and size of the transmit buffer descriptor ring into the smartdma channel registers. a. program the tra bits in the sdxtrcal register to the 12 low-address bits (bits 15C4) of the descriptor ring address, which is the start location in memory of the buffer descriptor ring. b. program the tra bits in the sdxtrah register to the four high-address bits (19C16) of the descriptor ring address. because the base address of the ring must be paragraph aligned (aligned to a 16-byte physical memory boundary), address bits 3C0 are always zeroes. c. program the trc bits in the sdxtrcal register to the number of entries in the transmit descriptor ring (the ring count). valid values are 1, 2, 4, 8, 16, 32, 64, or 128 descriptors. for more information about 3-bit encoding, see the am186?cc/ch/cu dma controller 8-32 am186?cc/ch/cu microcontrollers users manual microcontrollers register set manual , order #21916. even when the ring size is set to 1, that entry is still interpreted as a descriptor, not as the memory buffer itself. 5. point to the first buffer descriptor by clearing the sdxcbd register to 0. program the interrupt conditions the interrupt conditions are typically configured only once. 1. write the interrupt handler address to the vector table. see chapter 7, interrupts. 2. to generate an interrupt after transmitting the last byte of the packet, set the tepi bit in the sdxcon register to 1. 3. to generate an interrupt after detecting an unavailable buffer during transmission, set the tbui bit in the sdxcon register to 1. 4. to generate an interrupt after transmitting the last byte of the current buffer, set the ttci bit in the sdxcon register to 1. (note that the ttce bit in word 2 of the transmit buffer descriptor ring must also be set to 1.) 5. program the priority of this channel relative to other channels during simultaneous transfers using the p bit in the sdxcon register (this is typically configured only once). a 00b is a low priority; a 01b, medium; and a 10b, high. software clears the status bits in sdxstat after receiving an interrupt. software can use the sdxcbd register to monitor the transmit and receive buffers. software can also use the sdxctad register to determine the address in memory where the dma transmit process was interrupted. add data buffers to the transmit descriptor ring to place a data buffer in an entry in the transmit buffer descriptor ring: 1. find the first buffer descriptor for which the own bit is clear (bit = 0). this must be done in a circular manner relative to the current buffer descriptor index. in systems where the txs0 or rxs0 bits are set, thereby inhibiting clearing of the own bits, software must determine when it is safe to modify a descriptor ring entry. 2. program the data buffer address. a. program the ladr bits in word 0 to the low-order 16 address bits of the data buffer pointed to by the descriptor. b. program the hadr bits in word 1 to the high-order eight address bits of the data buffer pointed to by the descriptor. the highest four bits of the address must be set to 0000b. these address bits do not exist on the am186cc/ch/cu microcontrollers 20-bit address but are provided for lance compatibility. 3. program the data buffer size by setting the bcnt bits in word 2 to the length in bytes of the data buffer pointed to by the descriptor. 4. initialize the transmit buffer descriptor ring entries. a. set to 1 the ttce bit in word 2 to enable interrupt on terminal count; or clear to 0 to disable terminal count interrupt. (note that the ttci bit in the sdxcon register must also be set to 1.) b. set to 1 the stp bit in word 1 to indicate that this is the first buffer of the packet, or clear to 0 if the buffer contains a continuation of a packet from another buffer. c. set to 1 the enp bit in word 1 to indicate that this is the last buffer of the packet, or clear to 0 if the packet does not fit in one buffer and is continued in another. dma controller am186?cc/ch/cu microcontrollers users manual 8-33 d. set to 1 the own bit in word 1 to indicate the descriptor entry is owned by the smartdma channel. e. to force a poll of the own bit of the current buffer descriptor, set to 1 the poll bit in the sdxcon register. this has no effect if the smartdma is not currently waiting for a buffer to become available. 5. in the am186cc microcontroller, when using smartdma channel 2 or 3, select one of two alternate sources by clearing the dsel bit in the sdxcon register to 0 to select hdlc or to 1 to select usb. in the am186ch hdlc microcontroller, the dsel bit in the sdxcon register must be cleared to 0. in the am186cu usb microcontroller, the dsel bit in the sdxcon register must be set to 1. enable the transmit channel enable the transmit channel by setting the txst bit in the sdxcon register to 1. at this point, the smartdma transmit channel does not transmit any data because there are no valid buffers in the descriptor ring. as transmit data becomes available, software should modify entries in the ring to point to the data to be transmitted. buffers are added to the ring at the first ring location following the current transmit buffer descriptor value that has an own bit set to 0. 8.5.7.4.2 enabling the receive channel to enable a smartdma receive channel, software must perform the following tasks: 1. create the receive buffer descriptor ring. 2. program the interrupt channel and configure the smartdma channel for interrupts. 3. add data buffers to the ring. 4. enable the receive channel. 5. replace used data buffers. create the receive buffer descriptor ring 1. disable the receive channel by clearing the rxst bit in the sdxcon register to 0. 2. allocate the memory for the receive buffer descriptor ring (see smartdma channel descriptor format on page 8-38 for the descriptor ring data structure). 3. set the own bit for each descriptor to 1 (owned by hardware). 4. program the address and size of the receive buffer descriptor ring into the smartdma channel registers. a. program the rra bits in the sdxrrcal register to the 12 low address bits (bits 15C4) of the descriptor ring address, which is the start location in memory of the buffer descriptor ring. b. program the rra bits in the sdxrrah register to the four high address bits (19C16) of the descriptor ring address. because the base address of the ring must be paragraph aligned (aligned to a 16-byte physical memory boundary), address bits 3C0 are always zeroes. c. program the rrc bits in the sdxrrcal register to the number of entries in the receive descriptor ring (the ring count). valid values are 1, 2, 4, 8, 16, 32, 64, or 128 descriptors. for information about 3-bit encoding, see the am186?cc/ch/cu microcontrollers cc ch cu dma controller 8-34 am186?cc/ch/cu microcontrollers users manual register set manual , order #21916. even when the ring size is set to 1, that entry is still interpreted as a descriptor, not as the memory buffer itself. 5. point to the first buffer descriptor by clearing the sdxcbd register to 0. program the interrupt conditions the interrupt conditions are typically configured only once. 1. to generate an interrupt after receiving the last byte of the packet, set the repi bit in the sdxcon register to 1. 2. to generate an interrupt after detecting an unavailable buffer during reception, set the rbui bit in the sdxcon register to 1. 3. to generate an interrupt after receiving the last byte of the current buffer, set the rtci bit in the sdxcon register to 1. (note that the rtce bit in word 2 of the transmit buffer descriptor ring must also be set to 1.) add data buffers to the receive descriptor ring to place a data buffer in an entry in the receive buffer descriptor ring: 1. find the first buffer descriptor for which the own bit is clear (bit = 0). this must be done in a circular manner relative to the current buffer descriptor index. in systems where the txs0 or rxs0 bits are set, thereby inhibiting clearing of the own bits, software must determine when it is safe to modify a descriptor ring entry. 2. program the data buffer address. a. program the ladr bits in word 0 to the low-order 16 address bits of the data buffer pointed to by the descriptor. b. program the hadr bits in word 1 to the high-order eight address bits of the data buffer pointed to by the descriptor. the highest four bits of the address must be set to 0000b. these address bits do not exist on the am 186cc/ch/cu microcontrollers 20-bit address but are provided for lance compatibility. 3. program the data buffer size by setting the bcnt bits in word 2 to the length in bytes of the data buffer pointed to by the descriptor. 4. initialize the receive buffer descriptor ring entries. a. to enable interrupt on terminal count, set to 1 the rtce bit in word 2, or clear it to 0 to disable terminal count interrupt. (note that the rtci bit in the sdxcon register must also be set to 1.) b. program the priority of this channel relative to other channels during simultaneous transfers using the p bit in the sdxcon register. a 00b is a low priority; a 01b, medium; and a 10b, high. c. set to 1 the own bit in word 1 to indicate the descriptor entry is owned by the smartdma channel. d. to force a poll of the own bit of the current buffer descriptor, set to 1 the poll bit in the sdxcon register. 5. in the am186cc microcontroller, when using smartdma channel 2 or 3, select one of two alternate sources by clearing the dsel bit in the sdxcon register to 0 to select hdlc or to 1 to select usb. in the am186ch hdlc microcontroller, the dsel bit in the sdxcon register must be cleared to 0. cc ch dma controller am186?cc/ch/cu microcontrollers users manual 8-35 in the am186cu usb microcontroller, the dsel bit in the sdxcon register must be set to 1. software clears the status bits in sdxstat after receiving an interrupt. software can use the sdxcbd register to monitor the transmit and receive buffers. software can also use the sdxcrad register to determine the address in memory where the dma receive process was interrupted. enable the receive channel enable the receive channel by setting the rxst bit in the sdxcon register to 1. at this point, the smartdma receive channel is enabled. as received data is processed, software should modify entries in the ring to point to empty data buffers. buffers are added to the ring at the first ring location following the current buffer descriptor value that has an own bit cleared to 0. replace used data buffers 1. program the new data buffer address. a. program the ladr bits in word 0 to the low-order 16 address bits of the data buffer pointed to by the descriptor. b. program the hadr bits in word 1 to the high-order eight address bits of the data buffer pointed to by the descriptor. the highest four bits of the address must be set to 0000b. these address bits do not exist on the am 186cc/ch/cu microcontrollers 20-bit address but are provided for lance compatibility. 2. set to 1 the own bit in word 1 to indicate the descriptor entry is owned by the smartdma channel. 3. to force a poll of the own bit of the current buffer descriptor, set to 1 the poll bit in the sdxcon register. this bit has no effect if the smartdma channel is not currently waiting for a buffer to become available. 8.5.7.4.3 enable the peripheral device details for configuring and enabling the hdlc peripheral device being used can be found in chapter 15, high-level data link control (hdlc). details for configuring and enabling the usb peripheral device being used can be found in chapter 18, universal serial bus (usb). the dma should always be enabled before the requesting device is enabled. the dma should always be disabled after the requesting device is disabled. 8.5.7.5 smartdma channel cycle this section and the following sections describe the procedure the smartdma controller follows for both a transmit and a receive. 8.5.7.5.1 smartdma transmit channel cycle the flow diagram for the smartdma transmit channel is shown graphically in figure 8-8 on page 8-37 and discussed below. 1. when the transmit channel is first enabled, the smartdma controller enters initialization mode. 2. the transmit channel reads the current descriptor and checks to see if the owner semaphore (own) bit is set to 1. cu cc ch cc cu dma controller 8-36 am186?cc/ch/cu microcontrollers users manual if the own bit is 0, the software owns the current descriptor. in this case, the smartdma transmit channel periodically polls the descriptor until the own bit becomes 1. the transmit channel does not advance past a descriptor for which the own bit is 0. for information about forcing a poll, see smartdma channel descriptor polling on page 8-41. 3. if the own bit is 1 in the current descriptor, the transmit channel checks to see if the start-of-packet bit (stp) bit is set to 1. if the stp bit is 0, the transmit channel enters search-for-start-of-packet mode. this mode simply clears the own bit in the current descriptor and advances to the next descriptor ring entry. the transmit channel then returns to initialization mode, repeating these steps until it finds an entry with both the own and stp bits set to 1. 4. if the own and stp bits are both set to 1, the transmit channel reads the length of the buffer from the descriptor ring (bcnt bits in word 2) and programs that value into an internal terminal count register. the address of the buffer associated with this descriptor is read from the descriptor (ladr and hadr bits) into the sdxctad source address register. the transmit channel then enters normal-transmit mode. 5. in transmit mode, the channel transmits one byte of data from the memory buffer to the destination device for every drq. after each transfer, the source address in sdxctad is incremented and the internal transfer count is decremented. 6. when the internal terminal count is reached, the transmit channel checks the end-of- packet (enp) bit. a. if the enp bit is 0 in the current descriptor, the transmit channel attempts to acquire the next buffer. the transmit channel releases the current buffer by clearing the own bit (unless the txs0 bit is set). it then advances to the next descriptor in the ring. if the own bit is 0 (the software owns the descriptor), the transmit channel periodically polls the descriptor until own becomes 1. if an error condition occurs (e.g., a fifo underflow) before the transmit channel acquires the next descriptor, the error causes the requesting transmit source to shut down and the smartdma channel to be reprogrammed. if the transmit channel successfully acquires the next descriptor, the new buffer address and terminal count are loaded into the appropriate internal registers. b. when the terminal count is reached for a buffer for which the enp bit is set, the transmit channel enters transmit-end mode. in this mode, the transmit channel signals the end-of-packet to the device by asserting an internal signal during the transfer of the last data byte. the smartdma transmit channel waits for the packet to be sent successfully, then advances the index to the next buffer. if a complete packet is transmitted, the channel releases the current buffer by clearing the own bit before attempting to advance to the next buffer. if a packet is incomplete when the channel has reached terminal count on the buffer, it releases control of the buffer and advances to the next buffer in the ring. if the txs0 bit is set, the channel moves to the next buffer without clearing the own bit. whenever a packet needs to be retransmitted, the transmit channel must be disabled and the current buffer descriptor (sdxcbd) register must be programmed with the index of the buffer descriptor containing the stp bit for that packet. the transmit channel does not report any status in the buffer descriptor other than clearing the own bit. note: before disabling the transmit channel, you should stop the hdlc channel. dma controller am186?cc/ch/cu microcontrollers users manual 8-37 figure 8-8 smartdma transmit channel flow diagram 8.5.7.5.2 smartdma receive channel cycle the flow diagram for the smartdma receive channel is shown graphically in figure 8-9 on page 8-38 and discussed below. 1. when the receive channel is first enabled, the smartdma controller enters initialization mode. 2. the receive channel fetches the data for the first descriptor in the receive descriptor ring and checks to see if the owner semaphore (own) bit is set to 1. if the own bit is 0, the software owns the current descriptor. in this case, the smartdma receive channel periodically polls the descriptor until the own bit becomes 1. the receive channel does not advance past a descriptor for which the own bit is 0. for information about forcing a poll, see smartdma channel descriptor polling on page 8-41. 3. if the own bit is 1 in the current descriptor, the smartdma controller loads the address of the buffer into an internal receive address register. the length of the buffer is also read from the descriptor and programmed into an internal terminal count register. the receive channel then enters normal-receive mode. 4. in receive mode, the terminal count is decremented and the destination address is incremented for each byte transferred. the receiver remains in normal-receive mode until an end-of-packet is detected or the terminal count is reached. initialize channel transmit data get next buffer signal end of search for start-of-packet own=1 own=0 own=1 stp=1 stp=0 enp=0 enp=1 transmit search for available buffer own=1 own=1 (tc=0) (tc=0) (tc>0) transmit byte and decrement count notes: the tc bit is internal and not seen by users. owner semaphore bit set and not start-of-packet owner semaphore bit not set owner semaphore bit set owner semaphore bit set and start-of-packet clear owner semaphore bit and advance to next descriptor terminal count and not end-of-packet owner semaphore bit set terminal count and end-of-packet wait for packet to be sent dma controller 8-38 am186?cc/ch/cu microcontrollers users manual 5. if the terminal count reaches zero before the end-of-packet signal from the device is asserted, the receiver closes the current buffer and enters get-next-buffer mode. in this mode, the receiver reads the next descriptor in the descriptor ring and determines if the own bit is set. if the own bit is 0, the receiver remains in get-next-buffer mode, periodically polling the descriptor, until the own bit becomes set. when the own bit is detected as set, the receiver loads the buffer address and terminal count from the new descriptor and returns to normal-receive mode. 6. when the receiver detects the end-of-packet signal from the device, the receiver moves to receive-end mode. in receive-end mode, the receiver reads the status information from the device and writes it to the descriptor. the end-of-packet bit is set in the descriptor and the own bit is cleared. if rxs0 is set, the eop bit is set but the own bit not cleared. 7. the receiver advances the descriptor ring pointer and enters initialize mode. 8.5.7.6 smartdma channel descriptor format each entry in the descriptor ring consists of four 16-bit words. table 8-13 shows the format of the transmit descriptor ring; table 8-14, the receive descriptor ring. figure 8-9 smartdma receive channel flow diagram initialize channel receive data get next buffer owner semaphore set signal end of own=0 own=1 enp=0 enp=1 receive search for available buffer own=1 own=1 receive byte and decrement count (tc=0) (tc=0) (tc>0) notes: the tc bit is internal and not seen by users. owner semaphore bit not set owner semaphore bit set owner semaphore bit set te r m i n a l count and end-of-packet terminal count and not end-of-packet write status, clear owner semaphore bit, and advance to next descriptor. dma controller am186?cc/ch/cu microcontrollers users manual 8-39 table 8-13 smartdma transmit channel descriptor format bit number bit name description transmit buffer address (word 0) 15C0 ladr 1 notes: 1. the address programmed in the ladr and hadr fields is a linear address, not a segment:offset address. for example, if a transmit data buffer starts at segment address c000h and offset 1000h, it would be programmed as follows: linear address= (segment address x 16) + offset address = (c000h x 16) + 1000h = c1000h ladr = 1000h hadr = 0ch the ladr (low order) field contains the 16 low-order address bits of the data buffer pointed to by this descriptor. the ladr field is written by the software and not changed by the smartdma channel. transmit buffer status/config (word 1) 15 own 0 = descriptor entry is owned by the software. 1 = descriptor entry is owned by the smartdma channel. the software sets the own bit after filling the buffer pointed to by this descriptor. the smartdma channel clears the own bit (unless the txs0 bit is set) after transmitting the contents of the buffer. neither the software nor the smartdma channel can alter a descriptor entry after it has relinquished ownership. 14C10 reserved 9stp the stp (start of packet) bit indicates that this is the first buffer to be used by the smartdma channel for this packet. it is used to chain data buffers. the stp bit is set by the software and is not changed by the smartdma channel. the stp bit must be set in the first buffer of the packet, or the smartdma channel skips over this descriptor and polls the next descriptor(s) until both the own and stp bits are set. 8enp the enp (end of packet) bit indicates that this is the last buffer used by the smartdma channel for this packet. it is used to chain data buffers. if both the stp and enp bits are set, the packet fits into one buffer and there is no data chaining. the enp bit is set by the software and is not changed by the smartdma channel. 7C0 hadr 1 the hadr (high order) field contains the eight high-order address bits of the data buffer pointed to by this descriptor. the highest four bits of the address must be set to 0000b. these address bits do not exist in the microcontrollers 20-bit address but are provided for lance compatibility. the hadr field is written by the software and not changed by the smartdma channel. transmit buffer byte count (word 2) 15 ttce 0 = disable ttc interrupt. 1 = enable ttc interrupt. this bit is used to enable the transmit terminal count interrupt. 14C0 bcnt the bcnt (buffer byte count) field contains the length in bytes of the buffer pointed to by this descriptor. this number is expressed in 2s complement format and indicates the number of bytes from this buffer that are transmitted by the smartdma channel. this field is written by the software and not changed by the smartdma channel. for example, if you want to transfer 64 bytes, take the number 64 (40h), complement it (7fbfh), and increment it by 1 (7fc0h). place this number (7fc0h) in the bcnt field. transmit buffer word 3: this word is used for receive channels only; the transmit channels do not write any status to this word. dma controller 8-40 am186?cc/ch/cu microcontrollers users manual table 8-14 smartdma receive channel descriptor format bit number bit name description receive buffer address (word 0) 15C0 ladr 1 the ladr (low order) field contains the 16 low order address bits of the data buffer pointed to by this descriptor. the ladr field is written by the software and not changed by the smartdma channel. receive buffer status/config (word 1) 15 own 0 = descriptor entry is owned by the software. 1 = descriptor entry is owned by the smartdma channel. the smartdma channel clears the own bit (unless the rxs0 bit is set) after filling the buffer pointed to by this descriptor. the software sets the own bit after emptying the buffer. neither the software nor the smartdma channel can alter a descriptor entry after it has relinquished ownership. 14 err the err (error summary) bit is the logical or of fram, oflo, crc and hbuf. 13 fram the fram (framing error) bit indicates that the received frame did not contain a multiple of eight bits. the crc bit is not checked when the fram bit is set. the fram bit is valid only when the enp bit is set and the oflo bit is not. this bit is not used when the usb is the receive request. this bit is cleared by software. 12 oflo the oflo (overflow error) bit indicates that the internal receive fifo has detected an overflow condition. the oflo bit is valid only when the enp bit is not set. this bit is cleared by software. 11 crc the crc (cyclic redundancy check error) bit indicates: ? when hdlc is the requesting source, the current frame has a crc error. ? when usb is the requesting source, one of the following errors occurred: ? if the usb endpoint type is bulk, the possible errors are: crc, bit stuff, more than max packet value sent by software, data pid error, or data toggle error. ? if usb endpoint type is iso, the possible errors are: crc, bit stuff, more than max packet value sent by software, or data pid error. the crc bit is valid only when the enp bit is set and the oflo bit is not. this bit is cleared by software. 10 hbuf the hbuf (buffer error) bit indicates that the current frame has one of the following errors: ? frame ended in an abort instead of a flag. ? frame length was longer than the maximum length allowed. in this case, the mcnt field is equal to the maximum length allowed. ? frame length was shorter than the minimum allowed. part of the data of the frame was already discarded in the receiver. the mcnt field indicates the number of bytes that were output by the fifo, not the number of bytes in the frame. this bit is not used when the usb is the receive request. this bit is cleared by the software. 9stp the stp (start of packet) bit indicates that this is the first buffer used by the smartdma channel for this packet. it is used to chain data buffers. the stp bit is set by the smartdma channel. 8enp the enp (end of packet) bit indicates that this is the last buffer used by the smartdma channel for this packet. it is used to chain data buffers. if both the stp bit and the enp bit are set, the packet fits into one buffer and there is no data chaining. the enp bit is set by the smartdma channel. dma controller am186?cc/ch/cu microcontrollers users manual 8-41 8.5.7.7 smartdma channel descriptor polling when any of the smartdma channels on the am186cc/ch/cu microcontrollers require a new buffer and the owner semaphore (own) bit for the next descriptor in the descriptor ring is not set, the channel does a periodic poll (read) of the descriptor to determine if software has set the own bit in the intervening time. to assure that this polling has a minimal effect on interrupt latency and system performance, the dma uses a single counter to trigger the poll. each channel is given a unique timer value that is used to initiate the poll; these values are evenly dispersed throughout the timer period. this behavior guarantees that only a single smartdma channel attempts to poll its descriptor ring at any given time. the automatic poll timer completes one cycle every 64k processor clocks. this results in a potential poll cycle every 8k clocks. the smartdma channel control (sdxcon) register provides bits that allow software to request an immediate poll of one or both of the current descriptors (transmit channel and/ or receive channel). this poll does not affect the polling status of any other channel. a poll is never performed if the smartdma channel does not currently need the next buffer. this is true even if software sets the bit requesting an immediate poll. 7C0 hadr 1 the hadr (high order) field contains the eight high-order address bits of the data buffer pointed to by this descriptor. the highest four bits of the address must be set to 0000b. these address bits do not exist in the microcontrollers 20-bit address space but are provided for lance compatibility. the hadr field is written by the software and not changed by the smartdma channel. receive buffer byte count (word 2) 15 rtce 0 = disable rtc interrupt. 1 = enable rtc interrupt. this bit is used to enable the receive terminal count interrupt. 14C0 bcnt the bcnt (buffer byte count) field contains the length in bytes of the buffer pointed to by this descriptor. this number is expressed in 2s complement format and indicates the number of bytes allocated for this buffer. this field is written by the software and not changed by the smartdma channel. for example, if you want to transfer 64 bytes, take the number 64 (40h), complement it (7fbfh), and increment it by 1 (7fc0h). place this number (7fc0h) in the bcnt field. receive buffer message count (word 3) 15 reserved read/write as zero. 14C0 mcnt the mcnt (message byte count) field contains the length in bytes of the frame. the mcnt field is valid only when the err bit is 0 and the enp bit is 1. this field is written by the smartdma channel and cleared by software. notes: 1. the address programmed in the ladr and hadr fields is a linear address, not a segment:offset address. for example, if a receive data buffer starts at segment address c000h and offset 1000h, it would be programmed as follows: linear address= (segment address x 16) + offset address = (c000h x 16) + 1000h = c1000h ladr = 1000h hadr = 0ch table 8-14 smartdma receive channel descriptor format (continued) bit number bit name description dma controller 8-42 am186?cc/ch/cu microcontrollers users manual 8.5.7.8 smartdma channel interrupts smartdma channels can generate interrupts based on three conditions. the interrupt remains pending until software clears the associated status bit(s). the following list shows the different interrupt types, and gives some useful information about the characteristics of the interrupt. n tepi and repi (transmit/receive end of packet) interrupts are asserted when the last byte of a packet is transmitted or received. if many of the packets are short or appear to be short (e.g., due to an excessively noisy communications line), then the frequency of the interrupts may be higher than desired. n ttci and rtci (transmit/receive terminal count) interrupts are asserted when the last byte of a buffer is transmitted or received. the ttce/rtce bit in word 2 of the descriptor entry must also be set to use this interrupt. because generation of this interrupt is controllable on a buffer-by-buffer basis, it can be set up so that an interrupt occurs every n buffers, where n is completely under software control. this can be a useful way to reduce frequency of interrupts while ensuring that there are always descriptors available for the hardware. however, relying solely on this interrupt for a receive descriptor chain could mean that up to the last nC1 buffers in the ring go unprocessed. if rtci is the primary interrupt for a receive descriptor ring, a timer interrupt can also be used to detect leftover buffers after the other side has stopped sending. this can be a one-shot timer that is reset on every rtc interrupt, so that the timer expires shortly after the next rtc interrupt is expected. this timer interrupt generally should not be required on transmit descriptor rings, because any system that wants to be interrupted after there are no more buffers in the ring to send out can rely on the tbui interrupt (see the description below). n tbui and rbui (transmit/receive buffer unavailable) interrupts are asserted when an attempt to load the next descriptor in the ring finds that the own bit is 0. as discussed above, tbui can be used to determine if all buffers have been sent. you should not rely on rbui interrupts to cause software to make more buffers available to the hardware, or on tbui interrupts to cause software to make additional buffers within a single packet available to the hardware. the interrupt latency associated with either of these tasks could cause fifo overflows or underruns. rbui can be used as a type of watchdog interruptif rbui interrupts are occurring, it means that, for some reason, the system is not giving the receiver buffers fast enough. 8.5.7.9 smartdma channel use without cpu intervention in each smartdma channel, the user has the option of not clearing the own bit after dma has finished accessing a buffer (with the txs0 and rxs0 bits in the sdxcon register). this option provides the effect of a circular buffer from which data is accessed without the intervention of software. in a typical scenario, an hdlc receive channel and a different hdlc transmit channel, or an hdlc receive channel and a usb in endpoint, share a circular buffer. this shared buffer is implemented in software by making the transmit dma channel read from the same memory area to which the receive dma channel is writing. a software pll attempts to keep the write pointer slightly ahead of the read pointer so that stale data is never read by the transmitter, and so that the receiver never overwrites data not yet transmitted. in case of an error, both the transmit and receive channel can be disabled and reprogrammed to start at any particular buffer descriptor in the ring. dma controller am186?cc/ch/cu microcontrollers users manual 8-43 the following facilities aid in smartdma channel circular buffer management: n when receiving transparent hdlc data, no buffer status is transferred to the smartdma channel. the received data is simply a continuous stream of samples, and the smartdma controller keeps cycling through buffers without ever storing an eop. n the txso and rxso bits in the sdxcon registers can be set to keep the dma controller from returning buffer descriptors to the software. if the own bit is never updated, the dma controller can run through the descriptor ring multiple times without software intervention. n the sdxctad and sdxcrad registers can be read to determine the current buffer position, to enable a software pll to be able to control the rate of buffer filling/emptying. n if an error occurs, the sdxcbd registers can restart the dma at any arbitrary point in the buffer. in the simplest instance, a circular buffer can be formed by using a ring with a single descriptor. the descriptor contains the starting address and length of the circular buffer, and the stp and own bits must be set so that the dma controller uses the buffer. if code is to allow for adjustment of the buffer pointer (e.g., in case a usb isochronous transfer has an error or is missing), then the ring should have two descriptors in it. each descriptor points to a portion of the physical buffer, and the dma can be started at any arbitrary point by adjusting the descriptors' starting addresses and lengths, and setting the sdxcbd registers to point to the correct descriptor. 8.5.8 dma and usb the integrated usb peripheral controller is the only am186cc and am186cu microcontroller peripheral capable of using either general-purpose dma or a smartdma channel. each of the four usb data endpoints is connected to a single smartdma channel, and can be connected to any of the general-purpose dma channels. dma is a powerful tool when used with the usb peripheral controller. in addition to providing increased throughput and responsiveness to usb requests, it allows the use of larger packets, and it enables the usb peripheral controller's automatic rate control feature for isochronous transfers based on the pcm highway frame clock or an external frame clock source. for more information about using dma with the usb peripheral controller, see chapter 18, universal serial bus (usb). 8.5.9 software-related considerations software must stop dma operation before writing to the gdxcon1 register, or the results are unpredictable. stopping the smartdma channel has no effect while a request is pending on the channel. before stopping the channel, make sure the requesting peripheral (hdlc channel or usb endpoint) is stopped. 8.5.10 comparison to other devices n the general-purpose dma channels are the same as on other am186 controllers. n smartdma channels are compatible with the am79c90 c-lance dma. cc cu dma controller 8-44 am186?cc/ch/cu microcontrollers users manual 8.6 initialization on both an internal and external reset, the following occurs: n all the general-purpose dma and smartdma channel registers are cleared to 0. n any dma transfer in progress is aborted. n multiplexed signal drq0 defaults to its pio functionality. am186?cc/ch/cu microcontrollers users manual 9-1 chapter 9 programmable i/o signals 9.1 overview the am186cc/ch/cu microcontrollers provide 48 user-programmable input/output signals (pios). many of these signals share a pin with at least one alternate function. if an application does not need the alternate function, the associated pio can be programmed through the pio registers. if a pin is enabled to function as a pio, the alternate function is disabled and does not affect the pin. conversely, the value of any pin configured as a pio does not affect the alternate function of the pin. when configured as a pio, an appropriate default value for the signal is sent to the associated device rather than the value on the pin. a pio can be configured to operate as an input or output, with or without internal pullup or pulldown resistors (pullup or pulldown depends on the pin configuration and is not user- configurable), or as an open-drain output. additionally, eight pios can be configured as external interrupt sources. for information on this interrupt functionality, see chapter 7, interrupts. associated bits in the pio mode, pio direction, pio data, pio set, and pio clear registers control each of the 48 pios. because these registers are 16 bits wide, each pio function requires three registers (see table 9-2). two additional registers are provided for ease of use. 9.2 block diagram figure 9-1 shows the pio operation. programmable i/o signals 9-2 am186?cc/ch/cu microcontrollers users manual figure 9-1 pio operation block diagram 9.3 system design table 9-1 lists the pio signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. the table also shows which register bit programs the pin to be the pio or alternate function. . alternate function data out data out pio direction register write dir dq pio mode register write mode dq pio output write data dq pio input dq s r dir read dir pio data register write set write clear data in read mode read set read clear read data pio bus v ss or v cc 1 100k alternate function data in pad notes: 1. depends on pullup or pulldown. 2. when the pio is enabled, an appropriate default value is driven on the alternate function data in. mode default value 2 1 0 programmable i/o signals am186?cc/ch/cu microcontrollers users manual 9-3 table 9-1 pio multiplexed signals signal multiplexed signal(s) default signal register[bit] pio0 tmrin1 pio0: input with pullup piomode0[0] pio1 tmrout1 pio1: input with pulldown piomode0[1] pio2 pcs5 pio2: input with pullup piomode0[2] pio3 pcs4 pio3: input with pullup piomode0[3] pio4 mcs0 pio4: input with pullup piomode0[4] pio5 mcs3 / ras1 pio5: input with pullup piomode0[5] pio6 int8 / pwd pio6: input with pullup piomode0[6] pio7 int7 pio7: input with pullup piomode0[7] pio8 ardy ardy: input with pullup piomode0[8] pio9 drq0 pio9: input with pulldown piomode0[9] pio10 sden pio10: input with pulldown piomode0[10] pio11 sclk pio11: input with pullup piomode0[11] pio12 sdata pio12: input with pullup piomode0[12] pio13 pcs0 pcs0 : input with pullup piomode0[13] pio14 pcs1 pcs1 : input with pullup piomode0[14] pio15 wr wr : input with pullup piomode0[15] pio16 rxd_hu pio16: input with pullup piomode1[0] pio17 dce_cts_a pcm_tsc_a pio17: input with pullup piomode1[1] pio18 dce_rtr_a pio18: input with pullup piomode1[2] pio19 int6 pio19: input with pullup piomode1[3] pio20 txd_u/ dce_txd_d / pcm_txd_d pio20: input with pullup piomode1[4] pio21 uclk usbsof usbsci pio21: input with pullup piomode1[5] pio22 dce_rclk_c pcm_clk_c pio22: input with pulldown piomode1[6] pio23 dce_tclk_c pcm_fsc_c pio23: input with pulldown piomode1[7] pio24 cts_u dce_tclk_d pcm_fsc_d pio24: input with pullup piomode1[8] pio25 rtr_u dce_rclk_d pcm_clk_d pio25: input with pullup piomode1[9] pio26 rxd_u dce_rxd_d pcm_rxd_d pio26: input with pullup piomode1[10] pio27 tmrin0 pio27: input with pullup piomode1[11] pio28 tmrout0 pio28: input with pulldown piomode1[12] cc ch cc ch cc ch cc cc cc cu cc cu cc cc cc cc cc cc cc cc cc cc programmable i/o signals 9-4 am186?cc/ch/cu microcontrollers users manual pio29 dt/r dt/r : three-state output with pullup piomode1[13] pio30 den / ds den : three-state output with pullup piomode1[14] pio31 pcs7 pio31: input with pullup piomode1[15] pio32 pcs6 pio32: input with pullup piomode2[0] pio33 ale ale: three-state output with pulldown piomode2[1] pio34 bhe bhe : input with pullup piomode2[2] pio35 srdy srdy: input with pullup piomode2[3] pio36 dce_rxd_b pcm_rxd_b pio36: input with pullup piomode2[4] pio37 dce_txd_b pcm_txd_b pio37: input with pullup piomode2[5] pio38 dce_cts_b pcm_tsc_b pio38: input with pullup piomode2[6] pio39 dce_rtr_b pio39: input with pullup piomode2[7] pio40 dce_rclk_b pcm_clk_b pio40: input with pullup piomode2[8] pio41 dce_tclk_b pcm_fsc_b pio41: input with pullup piomode2[9] pio42 dce_rxd_c pcm_rxd_c pio42: input with pulldown piomode2[10] pio43 dce_txd_c pcm_txd_c pio43: input with pulldown piomode2[11] pio44 dce_cts_c pcm_tsc_c pio44: input with pullup piomode2[12] pio45 dce_rtr_c pio45: input with pullup piomode2[13] pio46 cts_hu dce_cts_d pcm_tsc_d pio46: input with pullup piomode2[14] pio47 rtr_hu dce_rtr_d pio47: input with pullup piomode2[15] table 9-1 pio multiplexed signals (continued) signal multiplexed signal(s) default signal register[bit] cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc ch cc cc cc cc cc cc cc cc cc cc programmable i/o signals am186?cc/ch/cu microcontrollers users manual 9-5 9.4 registers the 16 registers listed in table 9-2 program the pio signals. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. 9.5 operation 9.5.1 usage note: before using the pios, ensure multiplexed pins are configured to reflect the use of pio and not other functionality (see table 9-1 on page 9-3). to define a pin to be used as a pio, use the following process: 1. set the applicable bits in the pio mode and pio direction registers. to avoid changing system pio functionality unintentionally, it is good programming practice to do a read- modify-write when setting these bits. 2. manipulate data with the pio data, pio set, and pio clear registers. 9.5.2 defining the pio signal as input or output table 9-3 shows how the bit settings for the pio mode and pio direction registers affect signal function. the internal pullup and pulldown resistors each have a value of approximately 10 k w . table 9-2 pio register summary offset register mnemonic register name description 3c0h piomode0 pio mode 0 set pio15Cpio0 to pio or alternate function, and as input or output (see table 9-3). 3c2h piodir0 pio direction 0 3c4h piodata0 pio data 0 stores read or write data driven on outputs pio15Cpio0. reads of this register reflect the value of the pin. 3c6h pioset0 pio set 0 sets pio data register contents for pio15Cpio0. 3c8h pioclr0 pio clear 0 clears pio data register contents for pio15Cpio0. 3cah piomode1 pio mode 1 set pio31Cpio16 to pio or alternate function, and as input or output (see table 9-3). 3cch piodir1 pio direction 1 3ceh piodata1 pio data 1 stores read or write data driven on outputs pio31Cpio16. reads of this register reflect the value of the pin. 3d0h pioset1 pio set 1 sets pio data register contents for pio31Cpio16. 3d2h pioclr1 pio clear 1 clears pio data register contents for pio31Cpio16. 3d4h piomode2 pio mode 2 set pio47Cpio32 to pio or alternate function, and as input or output (see table 9-3). 3d6h piodir2 pio direction 2 3d8h piodata2 pio data 2 stores read or write data driven on outputs pio47Cpio32. reads of this register reflect the value of the pin. 3dah pioset2 pio set 2 sets pio data register contents for pio47Cpio32. 3dch pioclr2 pio clear 2 clears pio data register contents for pio47Cpio32. programmable i/o signals 9-6 am186?cc/ch/cu microcontrollers users manual 9.5.3 driving data on the pio if a pio signal is enabled as an output, the value in the corresponding bit in the pio data register is driven on the signal with no inversion. whether a pio signal is enabled as an input or as an output, a synchronized value from the pio signal is reflected in the value of the corresponding bit in the pio data register, with no inversion for pio data register reads. 9.5.4 using pios as open-drain outputs the pio data registers permit the pio signals to operate as open-drain outputs. this is accomplished by keeping the appropriate pdata bits constant in the pio data and pio mode registers and writing the data value into its associated bit position in the pio direction register. the output is either driving low or is disabled, depending on the data. 9.5.5 setting and clearing data the am186cc/ch/cu microcontrollers offer two additional registers, which can be used to set and clear the pio data register. a write to the pio set or pio clear registers functions as shown in table 9-4; a read does not change the pio data register contents. a read of the pio set or pio clear registers returns the last value written by software in the corresponding pio data register (including changes made via the pio set and pio clear registers). this enables software to read back the value that would be driven if a pio is changed from an input to an output. table 9-3 pio mode and pio direction register bit settings mode pio mode register pio direction register pin function alternate operation 0 0 alternate operation with pullup/pulldown (pio functionality disabled) pio 01 pio input with pullup/pulldown 1 notes: 1. the following pio signals can be configured as interrupt sources in the interrupt controllers shared mask (shmask) register: pio5, pio15, pio27, pio29, pio30, pio33, pio34, and pio35. typically, these signals should be configured as inputs when used as an interrupt source. however, if any of these signals is configured as both a pio output and as an interrupt source, the pio output signal generates interrupts. 10 pio output with pullup/pulldown 1 11 pio input without pullup/pulldown 1 table 9-4 pio set and pio clear registers effect on pio data register pio set register function pio clear register function written to pio set register bit old pio data register bit new pio data register bit written to pio clear register bit old pio data register bit new pio data register bit 000000 011011 101100 111110 programmable i/o signals am186?cc/ch/cu microcontrollers users manual 9-7 9.5.6 hardware-related considerations choose your pios wisely. the following pio signals are multiplexed with alternate signals that may be used by emulators: pio8, pio15, pio33, pio34, and pio35. consider any emulator requirements for the alternate signals before using these pins as pios. for more information, see chapter 4, emulator support. 9.5.7 software-related considerations n the pio set and pio clear registers provide an efficient, nondestructive means to modify specific data values for the pios. previous am186 devices required the user to perform a read-mask-modify-write approach when modifying pio data values (and preserving the values of other bits in the register). with the pio set and pio clear registers, specific bits can be set or cleared in a single write. n when configuring pios, modify only the bits relevant to your application by reading the existing register value, masking the bits needed, and writing the register. 9.5.8 comparison to other devices n the pio registers are similar to previous am186 controller implementations. the pio mode, pio direction, and pio data registers behave similarly; the pio set and pio clear registers have been added. n the am186cc/ch/cu microcontrollers offer 48 pios rather than the 32 offered in other am186 implementations, and these pios have different pin assignments. 9.6 initialization on both an external and internal reset, the following occurs: n the piomode0 register defaults to 0000h, the piodir0 register to 1effh, piomode1 to 0000h, piodir1 to 9fffh, piomode2 to 0000h, and piodir2 to fff1h. this defaults the pios to various configurations as shown in table 9-1 on page 9-3. (pio8, pio13, pio14, pio15, pio29, pio30, pio33, pio34, and pio35 default to their alternate operation. the remaining pios default to the pio function.) system initialization code must reconfigure pios as required. n the piosetx and pioclrx registers default to 0000h. n the piodatax registers default to values dependent on the system configuration. for more information, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. programmable i/o signals 9-8 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 10-1 chapter 10 programmable timers 10.1 overview there are three 16-bit programmable timers in the am186cc/ch/cu microcontrollers. timers 0 and 1 are identical and may be used to generate periodic external signals or waveforms or to count or time external events. each of these two timers has an input and an output pin. timer 2 is an internal timer which can be used to prescale timers 0 and 1 to provide longer time-out periods, or to generate dma requests for the general-purpose dma channels (see chapter 8, dma controller). all three timers can be programmed to generate periodic interrupts. the source clock for timer 2 is one-fourth of the cpu clock frequency (every fourth cpu clock tick). the source clock for timers 0 and 1 can be the timer input pin, timer 2, or one- fourth of the cpu clock,. the microcontroller also provides a pulse width demodulation (pwd) option for measuring the low state and high state durations of a toggling input signal. 10.2 block diagram figure 10-1 shows the block diagram for the programmable timers. figure 10-1 programmable timers block diagram cpu, memory, and other peripheral devices pcb interface interrupt dma tmrout0 tmrout1 controller controller int7 notes: 1. in pwd mode, the tmrin0, tmrin1 and int7 pins can be used as pios. if int7 is to be used as an external interrupt in pwd mode, it must be programmed to use the shared interrupt channel (channel 14). timer 0 timer 1 timer 2 timers pwd bit int8/pwd tmrin0 tmrin1 in syscon register ch12 ch13 0 0 0 1 1 1 ch0 programmable timers 10-2 am186?cc/ch/cu microcontrollers users manual 10.3 system design table 10-1 lists the programmable timer signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. when tmrin0 or tmrin1 is programmed as a pio, the corresponding signal is held high (asserted) internally, except in pwd mode where tmrin0 is replaced with int8 and tmrin1 is replaced with the inverse of int8. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. . 10.4 registers the registers listed in table 10-2 program the timers. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. table 10-1 programmable timer multiplexed signals signal function multiplexed signal(s) default signal pwd pulse-width demodulator int8 pio6 pio6 tmrin0 timer inputs pio27 pio27 tmrin1 pio0 pio0 tmrout0 timer outputs pio28 pio28 tmrout1 pio1 pio1 table 10-2 programmable timers register summary offset register mnemonic register name description 340h t0con timer 0 mode/control controls the functionality of timer 0. 342h t0cnt timer 0 count the value of this register is incremented by 1 for each timer event until the compare value is reached. 344h t0cmpa timer 0 maxcount compare a this register holds a compare value for t0cnt. 346h t0cmpb timer 0 maxcount compare b this register holds a compare value for t0cnt. 348h t1con timer 1 mode/control controls the functionality of timer 1. 34ah t1cnt timer 1 count the value of this register is incremented by 1 for each timer event until the compare value is reached. 34ch t1cmpa timer 1 maxcount compare a this register holds a compare value for t1cnt. 34eh t1cmpb timer 1 maxcount compare b this register holds a compare value for t1cnt. 350h t2con timer 2 mode/control controls the functionality of timer 2. 352h t2cnt timer 2 count this value of this register is incremented by 1 for each timer event until the compare value is reached. 354h t2cmpa timer 2 maxcount compare a this register holds a compare value for t2cnt. programmable timers am186?cc/ch/cu microcontrollers users manual 10-3 10.5 operation 10.5.1 usage note: if timer 0 or timer 1 is being used without the associated tmrin pin, the pin must be held high or programmed as a pio, otherwise the timer will not increment. before using the programmable timers, ensure multiplexed pins are configured to reflect the use of the timers and not other functionality (see table 10-1). 1. clear the current count by writing zero to the txcnt register. 2. specify the timer maximum count by writing to the timer maxcount compare (txcmpy) registers for the timer being used. 3. specify the actions taken when the timer count reaches maximum by setting bits in the corresponding timer mode and control (txcon) register. 4. enable the timer by setting both the en and inh bits in the corresponding timer mode and control (txcon) register. the timer count registers can be read or written at any time, regardless of whether the corresponding timer is running. the timers count from their initial value to the programmed compare value and then reset on the same clock. the value in the timer count register never equals the compare value. if the external pins are used (timer 0 and timer 1), the pio mode and pio direction bits for these pins must be configured for alternate operation. these pins are configured as pios at external and internal reset. for more information, see chapter 9, programmable i/o signals. 10.5.2 timer 2 when enabled, timer 2 increments the t2cnt register value at every fourth processor clock. after the timer increments, the microcontroller compares the t2cnt value with the value of the t2cmpa register. when the two values are equal, the microcontroller takes the following actions: n resets t2cnt to zero and sets the mc (max count reached) bit in the t2con register. n if the int bit is set in t2con, generates an interrupt request. software must clear the mc bit. n sends a pulse to timer 0 and timer 1 which can be used to increment those timers. n sends a dma request to the general-purpose dmathe dma may act on or ignore this request depending on how it is programmed. n if the cont (continuous mode) bit is zero, clears the en (enable) bit and the timer stops counting. if cont is one, the timer remains enabled and continues counting. since the comparison is done after the count is incremented, if t2cnt and t2cmpa are initially set to the same value, the comparison of t2cnt to t2cmpa will not be equal until 4 ? 0ffffh processor clocks after the counter is enabled. 10.5.3 timer 0 and timer 1 timers 0 and 1 provide identical functionality. unlike timer 2, timers 0 and 1 each have an input and output pin associated with the timer. they can also use timer 2 as a prescaler providing a 32-bit time-out count. programmable timers 10-4 am186?cc/ch/cu microcontrollers users manual three bits in the control register and the external tmrin pin control the way timer 0 and timer 1 count: n when the ext (external clock) bit is set, the tmrin signal provides the clock for the associated timer. in this mode, the timer count increments once for each low to high transition on the tmrin pin. the external clock speed cannot be greater than one fourth of the processor clock. the timer output can take up to six clock cycles to respond to the clock or gate input because of internal synchronization and pipelining of the timer circuitry. n when the rtg (retrigger) bit is set, a low to high transition on tmrin resets the value in the timers current count register. the timer counts during both the high and low phases of the tmrin signal. n when the p (prescaler) bit is set, timer 2 provides the clock for the associated timer. the timer increments once each time timer 2 reaches its maximum count. table 10-3 summarizes the behavior of the timers. timers 0 and 1 provide two maximum count compare registers, txcmpa and txcmpb. the setting of the alt (alternate compare) bit determines whether one or both of these compare registers are used. when alt is zero, only txcmpa is used. when alt is one, both compare registers are used. when alt is zero , the timer behaves as follows: n each time the timer increments, it compares the value in txcnt to the value in txcmpa. n if the compare is not equal, the timer: C holds tmroutx high. n if the compare is equal, the timer: C pulses tmroutx low for a single processor clock. C resets the txcnt register to zero. C sets the mc (maxcount reached) bit. software must clear the mc bit. C if the int bit is set in txcon, the timer generates an interrupt request. C if the cont (continuous mode) bit is zero, the timer clears the en (enable) bit and the timer stops counting. if the cont bit is one, the timer remains enabled and continues counting. table 10-3 timer 0 and timer 1 behavior txcon bit value tmrin ext rtg p low high low -> high 0 0 0 hold 1/4 processor clock no effect 0 0 1 hold timer 2 time-out no effect 0 1 0 1/4 processor clock 1/4 processor clock resets count 0 1 1 timer 2 time-out timer 2 time-out resets count 1 x x no effect no effect increments count programmable timers am186?cc/ch/cu microcontrollers users manual 10-5 when alt is set and the timer is using txcmpa (initial value after reset), the timer behaves as follows: n the riu (register-in-use) bit is zero (this is a read-only bit). n holds the tmroutx signal high (inverse of riu). n each time the timer increments, it compares the value in txcnt to the value in txcmpa. n if the compare is equal, the timer: C resets the txcnt register to zero. C sets the mc (maxcount reached) bit. software must clear the mc bit. C if the int bit is set in txcon, the timer generates an interrupt request. C sets the riu bit and performs the next compare against txcmpb. when alt is set and the timer is using txcmpb , the timer behaves as follows: n the riu (register-in-use) bit is one (this is a read-only bit). n holds the tmroutx signal low (inverse of riu). n each time the timer increments, it compares the value in txcnt to the value in txcmpb. n if the compare is equal, the timer: C resets the txcnt register to zero. C sets the mc (maxcount reached) bit. C if the int bit is set in txcot, the timer generates an interrupt request. software must clear the mc bit. C clears the riu bit and tmroutx transitions to high. C if the cont (continuous mode) bit is zero, the timer clears the en (enable bit) and the timer is disabled. if the cont bit is set, the timer remains enabled and performs the next compare against txcmpa. because the comparison is done after the count is incremented, if txcnt and txcmpa are set to the same value, the comparison of txcnt to txcmpa will not be equal until the current count reaches its maximum value, wraps around through zero and counts to the txcmpa value. setting txcmpb to zero provides the maximum time-out for the second phase of the timer. setting the alt bit and using the two compare registers allows timer 0 and timer 1 to generate waveforms on the associated tmrout pins. 10.5.4 requesting interrupts the int bits in the t0con, t1con, and t2con registers control interrupt request generation when a maximum count is reached. the request remains asserted for as long as the mc bit in the txcon register is set. software must clear this bit. if the maximum count and compare registers are both set to 0000h, the timer associated with that compare register counts from 0000h to ffffh before requesting an interrupt. with a 40-mhz clock, a timer configured this way interrupts every 6.5536 ms. when the alt bit is set for timer 0 or timer 1, the mc bit is set both when the timer reaches the txcmpa value and when the timer reaches the txcmpb value. software can differentiate these two conditions by examining the riu bit. the riu bit is 1 when the programmable timers 10-6 am186?cc/ch/cu microcontrollers users manual txcmpa value is reached (timer is now comparing against txcmpb). the riu bit is 0 when the txcmpb value is reached (timer is now comparing against txcmpa). 10.5.5 software polling software can poll the mc bit in the t0con, t1con, and t2con registers to monitor timer status rather than using interrupts. this bit must be cleared by software. 10.5.6 generating waveforms when programmed to use both compare values (alt bit in txcon is 1), timer 0 and timer 1 can generate waveforms on the associated tmrout pin. the txcmpa value determines the duration of the high phase of the output waveform. the txcmpb value determines the duration of the low phase of the output waveform. for more information, see the timer examples available on the amd website at ftp.amd.com . 10.5.7 pulse width demodulation for many applications, such as bar-code reading, it is necessary to measure the width of a signal in both its high and low phases. the am186cc/ch/cu microcontrollers provide a pulse width demodulation (pwd) option to fulfill this need. the pwd bit in the system configuration (syscon) register enables the pwd option. note that the am186cc/ch/ cu microcontrollers do not support analog-to-digital conversion. figure 10-1 on page 10-1 shows the routing of signals when pulse width demodulation is either enabled or disabled. the waveform for pwd mode is input on the int8/pwd pin. this pin is of type schmitt trigger in both normal interrupt and pwd modes. note that this pin is multiplexed with pio6 and defaults to the pio function at external and internal reset. in pwd mode, software uses timer 0 and timer 1 to measure the high and low pulse width of the input signal. interrupt 8 (channel 13, type 1dh) and interrupt 7 (channel 12, type 1ch) notify software of the transitions of the measured input signal. timer 0 starts its count on the low-to-high transition on the pwd input and counts the high signal duration. timer 1 starts its count on the high-to-low transition on the pwd input and counts the low signal duration. the low-to-high transition of the pwd input generates an interrupt request using channel 13 (type 1dh). the high-to-low transition of the pwd input generates an interrupt request using channel 12 (type 1ch). figure 10-2 shows the behavior of the pwd function for a typical input waveform. figure 10-2 pulse width demodulation example (1) (3) (1) (3) (2) (2) (4) (4) 1. a channel 13 (int8) interrupt request is generated. 2. timer 0 counts during the high phase of the input signal. 3. a channel 12 (int7) interrupt request is generated. 4. timer 1 counts during the low phase of the input signal. programmable timers am186?cc/ch/cu microcontrollers users manual 10-7 as shown in figure 10-1 on page 10-1, entering pulse width demodulation mode by setting the pwd bit in the syscon register does not have any direct effect on the timer block other than to reroute the tmrin0 and tmrin1 signals. the timers retain their full functionality and programmability. in the typical pulse width demodulation application, configure the t0con and t1con registers with a write of c001h (en + inh + cont). the isr for channel 13 reads the value in t1cnt to determine the length of the low phase of the signal, and then resets the t1cnt register to zero. the interrupt service routine (isr) for channel 12 reads the value in t0cnt to determine the length of the high phase of the signal and then resets the t0cnt register to zero. set the txcmpa compare value high enough to ensure that the signal duration will not exceed the maximum count. the isr should check the mc bit of the associated timer to determine if the maximum count has been exceeded. if the mc bit is set, software must then determine the appropriate response to this overflow situation. it may be sufficient to add the txcmpa register value to the txcnt register value to generate the correct signal duration. 10.5.7.1 handling short signal durations in applications where the pulse width is short, it may be necessary to poll the interrupt request bits in the interrupt request (reqst) register and jump to the isr rather than actually taking interrupts. 10.5.7.2 handling long signal durations when the timers are configured for pwd (en + inh + cont), the maximum duration of each phase of the input signal should not exceed 4 ? txcmpa processor clocks because the timer increments every fourth processor clock in this configuration. to extend the maximum measurable duration using pwd, software can enable timer interrupts, use timer 2 as a prescaler, or both. if the int (interrupt) bit is set in either t0con or t1con, the associated timer generates an interrupt request on channel 0type 08h for timer 0 and type 09h for timer 1. the isr for these interrupts should add the programmed maxcount (the value of the txcmpa register) to a memory location and clear the mc bit in the txcon register each time the interrupt is taken. the isr for channel 13 (interrupt type 1dh) must add the value of the timer 1 memory location to the current t1cnt register to determine the duration of the low phase of the signal. the isr for channel 12 (interrupt type 1ch) must add the value of the timer 0 memory location to the current t0cnt register to determine the duration of the high phase of the signal. in both cases the calculated duration must be multiplied by four to yield the total number of processor clocks. if the p (prescaler) bit is set in either t0con or t1con, the associated timer increments once for each timer 2 time-out. this increases the maximum measurable duration to 4 ? t2cmpa ? txcmpa. however, the precision of the measurement falls from within four processor clocks of the actual value to within 4 ? t2cmpa processor clocks of the actual value. for this reason, the value of t2cmpa should be kept as small as possible. this solution uses fewer processor cycles and has less of an effect on system performance than the use of timer interrupts. in applications where extremely long signals need to be measured, both the p bit and the int bit can be set either in t0con or t1con or both. programmable timers 10-8 am186?cc/ch/cu microcontrollers users manual 10.5.8 software-related considerations n timer 2 can generate a dma request. for more information, see chapter 8, dma controller. n timer 0 and timer 1 each have two 16-bit count compare registers. these registers can be used together to expand the time resolution for the timers. for more information, see the timer mode and control registers in the am186?cc/ch/cu microcontrollers register set manual , order #21916. 10.5.9 comparison to other devices the programmable timers are 100% compatible with the timers in the am186es and am186ed microcontrollers. 10.6 initialization on both an external and internal reset, the following occurs: n the values of all the timer registers are cleared to 0000h. n all the timer signals default to pio operation (see table 10-1 on page 10-2). n the pwd bit in the syscon register is cleared to 0. am186?cc/ch/cu microcontrollers users manual 11-1 chapter 11 watchdog timer 11.1 overview the am186cc/ch/cu microcontrollers provide a full-featured watchdog timer that can generate nonmaskable interrupts (nmis), internal resets, and system resets when the time- out value is reached. the time-out value is programmable and ranges from 2 10 to 2 26 processor clocks. throughout this chapter, an external reset refers to a reset of the microcontroller as initiated by the res signal, which resets the cpu and the internal peripherals. internal reset refers to a reset initiated by the watchdog timer. system reset refers to a reset of the external peripherals connected to the controller as initiated by the resout signal, which is pulled low during an external reset and can be pulled low during an internal reset. the watchdog timer provides a method to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. software errors can sometimes be resolved by recapturing control of the execution sequence through a watchdog-timer-generated nmi. when an external device fails to respond, or responds incorrectly, it may be necessary to reset the controller or the entire system, including external devices. the watchdog timer provides the flexibility to support both nmi and reset generation. the watchdog timer is enabled at reset. 11.2 block diagram figure 11-1 shows a block diagram of the watchdog timer. figure 11-1 watchdog timer block diagram watchdog timer (external) res resout execution unit (external) nmi internal nmi internal res internal rd wr data peripheral reset control counter key detect devices watchdog timer 11-2 am186?cc/ch/cu microcontrollers users manual 11.3 system design table 11-1 lists the watchdog timer signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. . systems that require a guaranteed recovery time from software or hardware errors should use the watchdog timer. generation of the internal nmi signal on the first watchdog timer time-out can be useful in systems where it may be possible to recover from glitches, corrupted data, or incorrect code without resetting either the controller or the board. this is especially true where potential data recovery is important. such systems should have the nmi interrupt handler routine in rom to ensure that it has not been corrupted by runaway code. however, in most systems, the interrupt table, which must be located at address 00000h, is located in ram and so is subject to corruption. generation of the resout signal should be used in systems where a system hang may be caused by incorrect behavior of an external device. the watchdog timer reset duration, and therefore the duration of the resout signal on a watchdog timer reset, is 2 16 processor clocks. this allows sufficient time for external devices to reach their reset state. the watchdog timer must function in all cases where either the software or external devices have failed to respond appropriately. the watchdog timer has incorporated several features to ensure that this is the case. n the watchdog timer is active after reset. n the watchdog timers default configuration after a power-on reset is to generate a reset on the first time-out and to assert the resout signal. n software can disable the watchdog timer control (wdtcon) register after reset and, while it is disabled, it can be written any number of times. when software enables the watchdog timer, the register becomes read-only except for two flag bits. this allows bootup or monitor code to disable the watchdog timer until the system has been configured. n each single write to the watchdog timer must be preceded by writes of a keyed sequence. detection of the keyed sequence allows a single write to the wdtcon register. n the watchdog timer time-out counter can only be reset by the initial enabling write to the wdtcon register or by writing a special key sequence to the wdtcon register. these features guarantee that the watchdog timer is not affected by runaway code. software can determine whether an nmi or reset event was caused by an external source or by the watchdog timer by reading the wdtcon register. the nmiflag bit is set when the watchdog timer generates an nmi; the rstflag bit is set when the watchdog timer generates a reset. software can clear, but not set, these bits. table 11-1 watchdog timer multiplexed signals signal function multiplexed signal(s) default signal res controller reset res nmi nonmaskable interrupt nmi watchdog timer am186?cc/ch/cu microcontrollers users manual 11-3 11.4 registers the register shown in table 11-2, wdtcon, programs the watchdog timer. figure 11-2 illustrates the rules for accessing the wdtcon register. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. figure 11-2 access to the wdtcon register 11.5 operation 11.5.1 usage 1. enable the watchdog timer by writing the keyed sequence of 3333h followed by cccch to the wdtcon register address. this sequence opens the wdtcon register for a single write. any number of processor cycles, including memory and i/o reads and writes, can be inserted between the two halves of the key or between the key and the writing of data as long as they do not read or write the wdtcon register. the write key sequence must be repeated for each single write. 2. after enabling the watchdog timer, periodically reset it by writing the keyed sequence of aaaah followed by 5555h to the wdtcon register address. as with the write key, any number of processor cycles, including memory and i/o reads and writes, can be inserted between the two halves of the key as long as they do not access the wdtcon register. the key itself resets the counter; no further writes are necessary. note that the clear-count key cannot be initiated while the write key is active. this would result in the value of aaaah being written to the wdtcon register. table 11-2 watchdog timer register summary offset register mnemonic register name description 3e0h wdtcon watchdog timer control controls the watchdog timer. ena = 1 timer enabled (after external or internal reset); software can use write key to write any value ena = 0 timer disabled; software can use write key to write any value notes: only one write is allowed to the wdtcon register after each write key sequence of 3333h followed by cccch. ena = 1 timer enabled; software can use write key to clear rstflag and nmiflag bits only write key plus rstflag = 0 or nmiflag = 0 only write key plus any value with ena = 1 write key plus any value with ena = 0 write key plus any value with ena = 1 reset write key plus any value with ena = 0 reset watchdog timer 11-4 am186?cc/ch/cu microcontrollers users manual 11.5.2 overview because the watchdog timer is enabled after reset, it is important for start-up code to program the watchdog timer before the initial time-out period expires. the time-out period after a watchdog timer reset is 2 26 clock cycles. all writes to the wdtcon register must be preceded by the write key sequence. the write key is a special two-write sequence to the wdtcon register address. the value of the key is not written to the wdtcon register but is used by internal logic to open the register for a single write. if a read-modify-write sequence is desired, the read must take place before the key is written because a read of wdtcon resets the keyed sequence. the systems start-up code can either enable or disable the watchdog timer. when enabled, the watchdog timer cannot be disabled until a reset occurs. if disabled, it can be enabled later by software. the reset start-up code should check the wdtcon register to see if the rstflag bit is set. if set, then the last reset was due to a watchdog timer time-out. what actions are taken is system dependent; however, possible actions include signaling another device that there is a problem, performing a more extensive test of hardware systems, or requesting reset of remote devices. debug monitor software (such as amds e86mon? software) can disable the watchdog timer, allowing the user to interact with the monitor without having to refresh the watchdog timer. the application code can then enable or disable the watchdog timer in its own start- up routine. in systems that program the watchdog timer to generate an nmi, the nmi service routine should check the wdtcon register to see if the nmiflag bit is set. if this bit is set, it indicates that an nmi due to a watchdog timer time-out occurred. software should clear this bit so that subsequent external nmis are not confused with watchdog timer nmis. what actions are taken are system dependent; however, possible actions include examining the state of the dma controller to determine whether dma usage is preventing instruction execution, polling external devices for status, or re-execution of all or part of the system start-up code. code that supports the watchdog timer should be divided into two parts. the main loop of the application, or some section of code that is periodically executed but not interrupt driven, should set a flag indicating that execution has passed through this code loop. a second piece of code that is interrupt driven, typically a timer interrupt, should check the value of the flag. if the flag is set, the interrupt service routine (isr) should write the watchdog timer clear-count key, resetting the time-out counter to zero. if the flag is not set, the isr has several options: wait for a watchdog timer time-out to let the reset or nmi code handle the problem; attempt to determine what the problem is; or continue normal execution with the expectation that the flag may be set at some later iteration. because transfer of control to an isr does not require non-isr code to be executing correctly, it is important that the isr code not reset the time-out counter unless the flag is set. 11.5.3 hardware-related considerations n pins that are latched on reset (pinstraps) are not resampled during a watchdog-timer reset. n if the external reset (res ) signal is asserted while the watchdog timer is performing a watchdog-timer reset, the external reset takes precedence over the watchdog-timer reset. this means that the resout signal asserts as with any external reset and the wdtcon register does not have the rstflag bit set. in addition, the part exits reset based on the external reset timing (i.e., 4.5 clocks after the deassertion of res rather than 2 16 clocks after the watchdog timer time-out occurred). watchdog timer am186?cc/ch/cu microcontrollers users manual 11-5 11.5.4 software-related considerations n even if the watchdog-timer default configuration is appropriate for the application, software should always perform an enabling write to the watchdog timer. this write causes most of the fields of the wdtcon register to become read-only, preventing run- away code from disabling or otherwise modifying the watchdog timer behavior. n if a watchdog-timer time-out occurs when the timer is programmed with wrst cleared, an nmi is generated, the time-out counter is reset, and the nmiflag bit is set. if the nmiflag bit is not cleared before a second watchdog timer time-out, a reset is generated regardless of the setting of wrst. n the watchdog timer can generate a nonmaskable interrupt (nmi). this interrupt can be taken at any time. unlike the maskable interrupts, the controller is not inhibited from taking a second nmi request while the nmi isr is executing. therefore, a watchdog timer nmi can interrupt, or be interrupted by, an externally generated nmi. 11.5.5 comparison to other devices the watchdog timer is based on the watchdog timer in the am186es and am186ed microcontrollers, with the following enhancements: n multiple writes are allowed to the wdtcon control register following reset as long as these writes have the enable bit cleared. when a write is detected with the enable bit set, the control register becomes read-only except for the nmi flag (nmiflag) bit and the reset flag (rstflag) bit. n the time-out counter is automatically reset by a write that enables the watchdog timer. n a read to the wdtcon register does not clear the nmiflag or rstflag bits. software must write a 0 value to each of these bits to clear them. writing a 1 to these bit positions has no effect. n the watchdog timer can generate an external signal when a watchdog-timer reset event occurs. 11.6 initialization at reset, the following occurs: n after an external reset, the watchdog timer is enabled and programmed to generate a reset including generation of the resout signal on time-out, the rstflag bit is cleared, and the time-out value is 2 26 clock cycles. n after a watchdog-timer reset, the watchdog timer is enabled and programmed to generate a reset on the time-out, the rstflag bit is set, and the time-out value is 2 26 clock cycles. the exrst bit, which determines whether resout is asserted for watchdog timer resets, retains its previously programmed value. n a watchdog-timer reset affects the microcontroller the same as an external reset, except for the following: C pinstraps are not sampled. C the rescon register is not reset. C the rstflag bit is cleared by an external reset, and set in an internal reset. C the exrst bit is set by an external reset, and unchanged by an internal reset. watchdog timer 11-6 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 12-1 chapter 12 serial communications overview 12.1 overview the am186cc/ch/cu microcontrollers support both asynchronous and synchronous serial communications. these features are described in the chapters indicated in the bullets below. the remainder of this chapter shows some of the trade-offs of using the various serial communications features available on the microcontroller and provides a brief overview of serial communications. n two asynchronous serial ports, the universal asynchronous receiver/transmitter (uart) and high-speed uart, provide full-duplex, bidirectional data transfer in rs-232 format using several industry-standard protocols: cts/rtr and 9-data-bit (multidrop). the uart supports data transfer speeds of up to 115.2 kbaud; the high-speed uart supports speeds up to 460 kbaud. see chapter 13, asynchronous serial ports (uarts). n one synchronous serial port provides half-duplex, bidirectional data transfer using the synchronous serial interface (ssi). the microcontroller can operate as the master for multiple slave peripheral devices. the ssi supports data transfer speeds of up to 25 mbit/s with a 50-mhz cpu clock. see chapter 14, synchronous serial port (ssi). n four high-level data link control (hdlc) channels on the am186cc and am186ch microcontrollers provide 8-bit element (byte or character) or frame full-duplex synchronous serial data transmission. the clock is provided by the time slot assigner (tsa) for that channel. for the most part, the tsa muxing logic controls the path data takes from an hdlc to an external communication interface (or vice versa). external interfaces supported are: raw data communications equipment (dce), pulse code modulation (pcm) highway, and on the am186cc microcontroller only, general circuit interface (gci). each tsa channel can support a burst data rate to or from an hdlc channel of up to 10 mbit/s in both raw dce and pcm highway modes, and up to 768 kbit/s in gci mode. see chapter 15, high-level data link control (hdlc), chapter 16, hdlc external serial interface configuration (tsas), and chapter 17, general circuit interface (gci). n the am186cc and am186cu microcontrollers both provide a universal serial bus (usb) peripheral controller, which supports full-speed (12 mbit/s) usb bulk, isochronous, interrupt, and control transfers as defined in the universal serial bus specification, revision 1.0 . the microcontroller acts as a usb peripheral device. the usb is a half-duplex, master/slave, polled bus. in other words, the microcontroller only transmits on the usb in response to a request from the usb host, usually a personal computer. there can be only one transmitter on the usb at a time. see chapter 18, universal serial bus (usb). ch cc cu cc serial communications overview 12-2 am186?cc/ch/cu microcontrollers users manual 12.2 system design 12.2.1 multiplexed signals the serial interfaces in the am186cc/ch/cu microcontrollers are multiplexed as shown in table 12-1. because of the multiplexing, there are some design trade-offs, as shown in the table. the figures that follow the table show how the microcontrollers serial communications features could be used in typical applications. table 12-1 multiplexed signal trade-offs for serial interfaces function used functions lost inter- face name pin inter- face name inter- face name inter- face name inter- face name synchronous communications interfaces dce channel a dce_rxd_a 118 pcm channel a pcm_rxd_a gci channel a gci_dd_a pio dce_txd_a 119 pcm_txd_a gci_du_a dce_rclk_a 117 pcm_clk_a gci_dcl_a dce_tclk_a 116 pcm_fsc_a gci_fsc_a dce_cts_a 123 pcm_tsc_a pio17 dce_rtr_a 122 pio18 dce channel b dce_rxd_b 138 pcm channel b pcm_rxd_b pio pio36 dce_txd_b 139 pcm_txd_b pio37 dce_rclk_b 135 pcm_clk_b pio40 dce_tclk_b 134 pcm_fsc_b pio41 dce_cts_b 137 pcm_tsc_b pio38 dce_rtr_b 136 pio39 dce channel c dce_rxd_c 153 pcm channel c pcm_rxd_c gci to pcm con- version pio pio42 dce_txd_c 154 pcm_txd_c pio43 dce_rclk_c 150 pcm_clk_c pcm_clk_c pio22 dce_tclk_c 149 pcm_fsc_c pcm_fsc_c pio23 dce_cts_c 152 pcm_tsc_c pio44 dce_rtr_c 151 pio45 dce channel d dce_rxd_d 158 pcm channel d pcm_rxd_d low- speed uart rxd_u high- speed uart (flow control) pio pio26 dce_txd_d 159 pcm_txd_d txd_u pio20 dce_rclk_d 156 pcm_clk_d rtr_u pio25 dce_tclk_d 157 pcm_fsc_d cts_u pio24 dce_cts_d 24 pcm_tsc_d cts_hu pio46 dce_rtr_d 23 rtr_hu pio47 pcm channel a pcm_rxd_a 118 dce channel a dce_rxd_a gci channel a gci_dd_a pio pcm_txd_a 119 dce_txd_a gci_du_a pcm_clk_a 117 dce_rclk_a gci_dcl_a pcm_fsc_a 116 dce_tclk_a gci_fsc_a pcm_tsc_a 123 dce_cts_a pio17 pcm channel b pcm_rxd_b 138 dce channel b dce_rxd_b pio pio36 pcm_txd_b 139 dce_txd_b pio37 pcm_clk_b 135 dce_rclk_b pio40 pcm_fsc_b 134 dce_tclk_b pio41 pcm_tsc_b 137 dce_cts_b pio38 pcm channel c pcm_rxd_c 153 dce channel c dce_rxd_c gci to pcm con- version pio pio42 pcm_txd_c 154 dce_txd_c pio43 pcm_clk_c 150 dce_rclk_c pcm_clk_c pio22 pcm_fsc_c 149 dce_tclk_c pcm_fsc_c pio23 pcm_tsc_c 152 dce_cts_c pio44 cc ch cc ch cc cc ch cc ch cc cc cc cc cc cc ch cc ch cc cc ch cc ch cc cc cc serial communications overview am186?cc/ch/cu microcontrollers users manual 12-3 12.2.2 sample applications for the am186cc communications controller figure 12-1 on page 12-4 shows an hdlc control application that uses all four hdlc channels of the am186cc microcontroller configured as nonmultiplexed raw dce external interfaces, in addition to the high-speed uart port for debugging. figure 12-2 on page 12-4 shows a pots linecard application that uses all four hdlc channels of the am186cc microcontroller multiplexed to external interface a for linecard control. in addition, this application uses the uart interfaced to external interface d for debugging, and the ssi port to control the linecard voice integrated circuits. unused external interfaces b and c are used as pios. figure 12-3 on page 12-5 shows an isdn application for the am186cc microcontroller that uses three hdlc channels multiplexed off external interface a, the high-speed uart port for a serial at modem connection to the host pc (or a usb connection to the pc can be used instead), the uart port on external interface d for debugging, and the ssi port to control the pots interface integrated circuits. (flow control on the high-speed uart is also multiplexed to external interface d.) figure 12-4 on page 12-5 shows an isdn application that uses the gci-to-pcm highway conversion feature of the am186cc microcontroller. this application uses three hdlc channels multiplexed off external interface a, the high-speed uart port for a serial at modem connection to the host pc, and the debug uart port on external interface d (flow control on the high-speed uart is also multiplexed to external interface d). external interface c is used for the converted gci-to-pcm highway frame sync and clock required by pcm highway codecs. external interface b is unused. pcm channel d pcm_rxd_d 158 dce channel d dce_rxd_d low- speed uart rxd_u high- speed uart pio pio26 pcm_txd_d 159 dce_txd_d txd_u pio20 pcm_clk_d 156 dce_rclk_d rtr_u pio25 pcm_fsc_d 157 dce_tclk_d cts_u pio24 pcm_tsc_d 24 dce_cts_d cts_hu pio46 low- speed uart rxd_u 158 dce channel d dce_rxd_d pcm channel d pcm_rxd_d pio pio26 txd_u 159 dce_txd_d pcm_txd_d pio20 rtr_u 156 dce_rclk_d pcm_clk_d pio25 cts_u 157 dce_tclk_d pcm_fsc_d pio24 high- speed uart rxd_hu 25 dce channel d pcm channel d pio pio16 txd_hu 26 rtr_hu 23 dce_rtr_d pio47 cts_hu 24 dce_cts_d pcm_tsc_d pio46 gci channel a gci_dd_a 118 dce channel a dce_rxd_a pcm channel a pcm_rxd_a pio gci_du_a 119 dce_txd_a pcm_txd_a gci_dcl_a 117 dce_rclk_a pcm_clk_a gci_fsc_a 116 dce_tclk_a pcm_fsc_a gci to pcm con- version pcm_clk_c 150 dce channel c dce_rclk_c pcm channel c pcm_clk_c pio pio22 pcm_fsc_c 149 dce_tclk_c pcm_fsc_c pio23 table 12-1 multiplexed signal trade-offs for serial interfaces (continued) function used functions lost inter- face name pin inter- face name inter- face name inter- face name inter- face name cc cc cc cc cc cc cc cc ch cc ch cc cc cc cc serial communications overview 12-4 am186?cc/ch/cu microcontrollers users manual figure 12-1 hdlc control application figure 12-2 pots linecard uarts high- speed uart uart external interface hdlc channels channel d channel c channel b channel a debug or console uart raw dce external interface d raw dce external interface c raw dce external interface b raw dce external interface a cc uarts high- speed uart uart external interface hdlc channels channel d channel c channel b channel a external interface d is used for debug uart external interfaces b and c are used as pios external interface a for linecard control tsa channels channel d channel c channel b channel a ssi ssi to linecard voice ics cc serial communications overview am186?cc/ch/cu microcontrollers users manual 12-5 figure 12-3 isdn application figure 12-4 isdn application with gci-to-pcm highway conversion optional usb connection to host pc (instead of high-speed uart connection) uarts high- speed uart uart hdlc channels channel d channel c channel b channel a external interface d is used for debug uart and flow control for high- speed uart external interfaces b and c are used as pios external interface a tsa channels channel d channel c channel b channel a ssi ssi to pots ics usb connection to host pc gci external interface cc uarts high- speed uart uart external interface hdlc channels channel d channel c channel b channel a external interface d is used for debug uart and flow control for high- speed uart tsa channels channel d channel c channel b channel a connection to host pc gci clk fsc clk fsc pcm highway codec external interface c is used for converted gci-to-pcm highway frame sync and clock clk fsc gci transceiver external interface a dd du clk fsc dd du tx rx cc serial communications overview 12-6 am186?cc/ch/cu microcontrollers users manual 12.3 serial communications introduction in serial communications, one data bit at a time is transmitted through a single wire or communication channel. because a processor data bus uses parallel communications (more than one data bit is transmitted at the same time through more than one wire), the communications channel must convert data to serial at the transmitter and then back to parallel at the receiver. in addition, the timing of long streams of bits must be the same for the transmitter and the receiver, or errors result. 12.3.1 asynchronous and synchronous communications in asynchronous serial communications, the receiver and transmitter have independent clocks. synchronization problems are avoided by not sending long, uninterrupted streams of bits. instead, data bits are transmitted one character at a time. each character can be from four to nine data bits, and is preceded by a start bit and followed by a stop bit. the start bit, character, and stop bit together are called a frame . asynchronous communication does not require continuous data so timing must only be maintained within each character; the receiver can resynchronize between frames. in addition, frames can be sequenced to form packets of data. in synchronous serial communications, timing is determined by transmitting a clock signal along with the data. the channel transmits blocks of bits or characters without a start or a stop bit; the clock ensures the transmitter and receiver are synchronized. while this addresses the timing problem, the receiver must also be able to determine the beginning and end of a block of data. to achieve this, each block of data has some start and end bits. other control information may be included. the data plus the control information is called a frame . the start-bit and end-bit patterns vary based on the protocol, and are sometimes called preamble and postamble bits, or flags . asynchronous communications is simpler to use but has a higher overhead than synchronous communications, and as such is better suited for small blocks of data that transmit in bursts (e.g., a keyboard or terminal). synchronous communications is better suited for continuous large data blocks and higher speeds (e.g., hdlc frames), as many bytes of data are sent without overhead. 12.3.2 hardware flow control both synchronous and asynchronous communications can have problems when a transmitter sends the data faster than the receiver is ready for it. typically, a receiver allocates a data buffer with a certain length. after the data is processed, the receiver clears the buffer so it can receive more data. however, the receiver buffer can overflow if new data is received before the last received data is read. hardware flow control is a method to eliminate the possibility of overrun errors. the am186cc/ch/cu microcontrollers support the clear-to-send/ready-to-receive (cts/rtr) protocol on the uart and high-speed uart. the am186cc and am186ch microcontrollers also support the clear-to-send/ready-to- receive (cts/rtr) protocol on the hdlc ports. the cts/rtr protocol is a symmetrical interface between two serial ports, and provides flow control when both ports are sending and receiving data, as shown in figure 12-5. ch cc serial communications overview am186?cc/ch/cu microcontrollers users manual 12-7 figure 12-5 cts /rtr protocol 12.3.3 fifos another way to reduce data overflow is to use a hardware fifo (first in first out data buffer). a hardware fifo queues up the bytes until the receiver is ready for them. a fifo is classified by its width and depth. the width specifies the number of bits in a word; the depth, the number of those words that can be queued. so, a 9x16 fifo can queue 16 9-bit words before overflowing. fifos can also be useful when data arrives during an interrupt. in the am186cc microcontroller, fifos are available for the high-speed uart, hdlc, and usb ports. in the am186ch hdlc microcontroller, fifos are available for the high-speed uart and hdlc ports. in the am186cu usb microcontroller, fifos are available for the high-speed uart and usb ports. 12.3.4 polled, interrupt, and dma modes serial communications can occur in polled, interrupt, or dma modes. polled mode disables interrupts and the dma controller. the software loops on a status register, reading in all wait situations. in interrupt mode , interrupts are enabled. software does other tasks while waiting for the interrupt. in dma mode , hardware performs the entire transfer, with no software intervention except for errors. for information about interrupts, see chapter 7, interrupts. for information about dma, see chapter 8, dma controller. in the am186cc/ch/cu microcontrollers, the serial communications peripherals support the three modes as follows: n the uart and high-speed uart support polled, interrupt, and dma modes. n the ssi only supports polled mode. n in the am186cc and am186ch microcontrollers, the hdlc channels support polled, interrupt, and dma modes. n in the am186cc microcontroller, gci supports polled and interrupt modes but not dma mode. n in the am186cc and am186cu microcontrollers, usb supports polled, interrupt, and dma modes. transmitter cts rtr cts rtr cts = input signal to the transmitter; clear to send input port 1 port 2 transmitter receiver receiver rtr = output signal from the receiver; ready to receive output cc ch cu ch cc cc cu cc serial communications overview 12-8 am186?cc/ch/cu microcontrollers users manual 12.3.5 simplex, half-duplex, and full-duplex systems in serial communications, a simplex system can transmit data in only one direction; a half- duplex system can send data in either direction, but not both at the same time; a full-duplex system can send data in both directions simultaneously. in the am186cc/ch/cu microcontrollers, the ssi supports half-duplex transfers, and the uart and high-speed uart support full-duplex transfers. in the am186cc and am186ch microcontrollers, the hdlc channels support full-duplex transfers. in the am186cc and am186cu microcontrollers, usb supports half-duplex transfers. ch cc cu cc am186?cc/ch/cu microcontrollers users manual 13-1 chapter 13 asynchronous serial ports (uarts) 13.1 overview the am186cc/ch/cu microcontrollers each provide two independent asynchronous serial ports: a universal asynchronous receiver/transmitter (uart) and a high-speed uart. the uarts support the following features: n up to 115.2 kbaud rate (uart) or up to 460 kbaud rate (high-speed uart) n automatic baudrate detection with enhancements to compensate for distortion of start bit (high-speed uart only) n 32-byte receive and 16-byte transmit fifos with threshold at half full (high-speed uart only) n receive-character-matching for up to six characters including address-bit matching (high-speed uart only) n 7-, 8-, or 9-bit data transfers n address bit generation and detection in 7- and 8-data-bit frames n extended read and write modes that allow word-wide dma transfers n multidrop protocol (9-data-bit) support n use of processor clock or external clock signal for generation of baud clock n full-duplex operation n one or two stop bits n even, odd, or no parity n break generation and detection n programmable to drive either high or low on txd line during break n automatic hardware flow control using the clear-to-send/ready-to-receive (cts/rtr) protocol n dma to and/or from the serial ports using the general-purpose dma channels n double-buffered transmit and receive n individually maskable interrupt requests for the following conditions: C receive fifo threshold reached (high-speed uart only) C transmit fifo threshold reached (high-speed uart only) C receive fifo overflow (high-speed uart only) C receive data character match (high-speed uart only) C transmit fifo empty (high-speed uart only) C break detected C received character with address bit set C receive data available C transmitter able to accept new data C framing error detected asynchronous serial ports (uarts) 13-2 am186?cc/ch/cu microcontrollers users manual C receive overflow error detected C parity error detected C transmitter empty C receive line idle the high-speed uart interface has been designed so that code written to run on the uart runs on the high-speed uart with no modification other than adjusting the register offsets. the high-speed uart interface maintains all bits and bit positions in the uart interface. the high-speed serial port status (hsptat) register contains additional status bits, but these bits read as zeros unless the associated function is enabled. code written for the uart that writes zeros to reserved bits should run identically on the high-speed uart. 13.2 block diagram figure 13-1 shows the uart and high-speed uart block diagram. features specific to the high-speed uart are marked high-speed uart only. uart signal names begin with sp; high-speed uart signal names begin with hsp. signals for both start with (h)sp. figure 13-1 uarts block diagram character match (high- speed uart only) write data15Cdata0 read data15Cdata0 block_select ad4Cad1 wr rd (h)sp_txdrq (h)sp_rxdrq interrupt request pad signals co_txd_(h)u ci_cts_(h)u_l ci_uclk external clock ci_rxd_(h)u co_rtr_(h)u_l baud clock derived rx clock receiver tx clock enable interrupt transmit control transmit data transmit status baud control baud divisor autobaud registers (high-speed uart only) new baud value (high-speed uart only) receive control receive data receive status char match regs (high-speed uart only) status register interrupt mask register configuration bits (h)sp_reg hsp_txfifo (high-speed uart only) hsp_rxfifo (high-speed uart only) autobaud (high- speed uart only) transmitter generator request transmit data clear-to- send receive data ready- to- receive generator asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-3 13.3 system design table 13-1 lists the uart signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. . 13.4 registers the registers listed in table 13-2 program the uarts: 8 for the uart and 15 for the high- speed uart. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. in addition to these registers, the itf4 bit field in the system configuration (syscon) register of the am186cc microcontroller configures external interface 4 for the hdlc or the uarts. in the am186ch and am186cu microcontrollers, the itf4 bit field should be set to 10b. table 13-1 uarts multiplexed signals signal function multiplexed signal(s) default signal uart rxd_u receive data uart dce_rxd_d pcm_rxd_d pio26 pio26 txd_u transmit data uart dce_txd_d pcm_txd_d pio20 pio20 cts_u clear-to-send uart dce_tclk_d pcm_fsc_d pio24 pio24 rtr_u read-to-receive uart dce_rclk_d pcm_clk_d pio25 pio25 high-speed uart rxd_hu receive data high-speed uart pio16 pio16 txd_hu transmit data high-speed uart txd_hu cts_hu clear-to-send high-speed uart dce_cts_d pcm_tsc_d pio46 pio46 rtr_hu read-to-receive high-speed uart dce_rtr_d pio47 pio47 cc ch cu asynchronous serial ports (uarts) 13-4 am186?cc/ch/cu microcontrollers users manual 13.5 operation 13.5.1 usage note: before using the uarts, ensure multiplexed pins are configured to reflect the use of the uarts and not other functionality (see table 13-1 on page 13-3). to use the uart and the high-speed uart, software must program the bits described in the following procedures. the procedures include transmit, receive, and autobaud mode (high-speed uart only). the high-speed uart has the same basic registers as the uart (plus some additional ones). these registers are named the same except for an h in front of the high-speed uart register name. throughout this chapter, an (h) in front of the table 13-2 uarts register summary offset register mnemonic register name description high-speed uart 260h hspcon0 high-speed serial port control 0 configures and enables serial port. 262h hspcon1 high-speed serial port control 1 configures serial port. 264h hspstat high-speed serial port status provides information about the current status of the serial port. 266h hspimsk high-speed serial port interrupt mask enables interrupts based on condition of status bits. 268h hsptxd high-speed serial port transmit data provides data to transmitter. 26ah hsprxd high-speed serial port receive data contains data read over serial line. 26ch hsprxdp high-speed serial port receive data peek reads data in receive data register without changing condition of serial port. 26eh hspbdv high-speed serial port baud rate divisor specifies a clock divisor for generation of the serial clock. 270h hspm0 high-speed serial port character match 0 each register can be programmed with two characters for use with automatic character matching. 272h hspm1 high-speed serial port character match 1 274h hspm2 high-speed serial port character match 2 276h hspab0 high-speed serial autobaud 0 each register contains values used as baud divisors during autobaud. 278h hspab1 high-speed serial autobaud 1 27ah hspab2 high-speed serial autobaud 2 27ch hspab3 high-speed serial autobaud 3 uart 280h spcon0 serial port control 0 behaves the same as the high-speed uart registers but for the uart port. 282h spcon1 serial port control 1 284h spstat serial port status 286h spimsk serial port interrupt mask 288h sptxd serial port transmit data 28ah sprxd serial port receive data 28ch sprxdp serial port receive data peek 28eh spbdv serial port baud rate divisor asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-5 register name indicates that both the uart and the high-speed uart registers are being described. 13.5.1.1 transmit this section describes the procedure for programming a transmit. to program a receive, see page 13-6. to use autobaud mode, see page 13-7. transfers can be done in polled, interrupt, or dma modes. 13.5.1.1.1 initializing the transmitter initialize the transmitter with the following steps: 1. disable the uart by clearing the tmode bit of the (h)spcon0 register to 0. software can change interrupt masks without disabling the tmode bit. 2. set the baud rate with the (h)spbdv register. for information about detecting the baud rate automatically, see autobaud mode (high- speed uart only) on page 13-7. 3. set the applicable configuration options in the (h)spcon1 register: break value, extended write, external/internal clock, and fifos (high-speed uart only). if software enables fifos with the tfen bit, it should also set the tflush bit at the same time (or before) to flush the fifo. 4. set the interrupts to be taken with the (h)spimsk register. bits in this register are second-level interrupt enables based on status bits in the (h)spstat register. set first- level interrupt enables in the (h)spcon0 register (see step 5). note that corresponding bits must be set in both registers for the interrupt to be taken. if software disables an interrupt in (h)spimsk, it can still read the status from the (h)spstat register. 5. set the applicable configuration options in the (h)spcon0 registerinterrupts, breaks, cts/rtr hardware flow control, parity (odd, even, or none), address bit enable, number of data bits in serial frame (7 or 8), and stop bit length (one or two)and enable the transmit by setting the tmode bit to 1. all of these bits can be set simultaneously, but the tmode bit cannot be set before any of the other bits described in steps 2C5. 13.5.1.1.2 transmitting data when the transmitter is initialized, to send data: 1. verify that the thre bit in the (h)spstat register is set to 1 to ensure the transmit register can be written without loss of data. 2. if fifos are being used (high-speed uart only), instead of polling the thre bit, verify that the fifo is not yet full (tthrsh bit in the hspstat register is set to 1). 3. to send an address bit with a particular frame w hen extended writes are disabled (exdwr in (h)spcon1 is 0): a. verify that temt = 1 to ensure any other transmissions have completed (the transmitter and the transmit shift register are both empty). b. set the transmit ab bit in the (h)spcon0 register to 1 if this address bit should be sent as the msb of tdata for this frame. when extended writes are enabled, write the value of the address bit with the data. in this situation, the value of temt does not matter. 4. write data to the (h)sptxd register (this sets the thre bit to 0). asynchronous serial ports (uarts) 13-6 am186?cc/ch/cu microcontrollers users manual when extended writes and address bits are enabled , 9-bit data should be written to the (h)sptxd register. the first word should include the ab bit value (set the transmit ab (ab) bit in the (h)sptxd register to 1 followed by the address bits in the tdata field). then the following words should contain ab = 0 and the data for the designated address point. hardware stops writing to the (h)sptxd register when txdrq goes to 0; when txdrq = 1, hardware continues writing the data. in the case of dma, the hardware handles the data flow from the dma unit to the sptxd register automatically using an internal dma signal. 5. wait for the temt bit in the (h)spstat register to go to 1 to indicate the on-line transfer has completed. 13.5.1.2 receive the procedure to program a receive is described below. to program a transmit, see page 13-5. to use autobaud, see page 13-7. transfers can be done in polled, interrupt, or dma modes. 13.5.1.2.1 initializing the receiver the following procedure initializes the receiver. before reconfiguring any options (including the baud rate), disable any receives. to do this, check that rdr=0 and idled=1 in the (h)spstat register to ensure no data is in the receiver, and then clear the rmode bit to 0. interrupt masks can be changed without disabling the receiver (clearing rmode to 0). 13.5.1.2.2 setting the baud rate with the (h)spbdv register 1. if character matching is desired (high-speed uart only), load the high speed serial port character match (hspm0, hspm1, and hspm2) registers with the characters to be matched. each match register contains two character fields. note that 00h is a valid value so if you do not want the 00h character to be matched, all six character fields should be initialized, even if it is with the same value. 2. set the applicable configuration options in the (h)spcon1 register: break value, extended read, external/internal clock, and, on the high-speed uart only, fifos and character matching. if fifos are enabled with the rfen bit, the rflush bit should also be set at the same time (or before) to flush the fifo. if comparing characters in frames with address bits, the three mab bits should be configured. each mab bit setting (1 or 0) is used as the address bit for both characters in the corresponding match register. as with the character match registers, all three bits should be set. 3. set the interrupts to be taken with the (h)spimsk register. bits in this register enable interrupts based on interrupts set in the (h)spcon0 register. note that corresponding bits must be set in both registers for the interrupt to be taken. if an interrupt is disabled in (h)spimsk, the status can still be read. 4. write all the bits in the (h)spstat register to 0 to clear any status. 5. set the applicable configuration options in the (h)spcon0 registerinterrupts, breaks, cts/rtr hardware flow control, parity (odd, even, or none), address bit enable, number of data bits in serial frame (7 or 8), and stop bit length (one or two)and enable the receive by setting the rmode bit in the (h)spcon0 register to 1. all of these bits can be set simultaneously but rmode cannot be set before any of the other bits described in steps 1C5. asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-7 13.5.1.2.3 receiving data when the receiver is initialized, to receive data: 1. read the (h)spstat register: a. verify that the rdr bit is set to 1 to ensure the rdata field contains valid data. b. read the other status bits to check the status on the last byte received and clear any status bits that were set. 2. read data from the (h)sprxd register (this clears the rdr bit to 0). the (h)sprxdp register is also available to peek at the data. this register is a duplicate of the receive register; however, reading it does not clear the rdr bit. 13.5.1.3 autobaud mode (high-speed uart only) the procedure to program autobaud mode is described here. to program a transmit, see page 13-5; to program a receive, see page 13-6. 1. verify that the tmode and rmode bits in the hspcon0 register are cleared to ensure there are no transfers in progress. 2. set the baud rate with the hspbdv register. the register value cannot be 0; a value must be written into this register before enabling a transmit or receive. 3. set the autobaud enable (abaud) bit in the hspcon1 register to 1. 4. optionally, to address errors in computing autobaud, program the high speed serial port autobaud (hspab0, hspab1, hspab2, and hspab3) registers with thresholds and divisors. this method compensates for distortion of start bit width resulting from external effects. 5. clear all the bits in the hspstat register to 0. 6. set the applicable configuration options in the hspcon0 registerinterrupts, breaks, cts/rtr hardware flow control, parity (odd, even, or none), address bit enable, number of data bits in serial frame (7 or 8), and stop bit length (one or two)and enable the receive by setting the rmode bit in the hspcon0 register to 1. these bits can be set simultaneously, but rmode cannot be set before any of the other bits described in steps 2C6. if no information is known about the data to be received, set the options to 8 bits, no parity, and no address bit. the tmode bit must be 0; a transmit cannot be occurring while the receiver is computing autobaud. 7. wait for the abaud bit in the hspcon1 register to go to 0 to indicate that the autobaud operation is complete. the computed baud divisor is automatically copied into the hspbdv register, and the autobaud (abaud) bit in the hspcon1 register is cleared. 8. read the new baud divisor value from the hspbdv register and check that it is a valid divisor value or is acceptable. 9. wait for the rdr bit in the hspstat register to be set to 1 to ensure the rdata field contains valid data. 10.read data from the hsprxd register (this clears the rdr bit to 0). in autobaud mode, the receiver is expecting a 1 in the least significant bit of the data (i.e., a valid autobaud character such as an ascii a). software must check that this value is valid. this procedure sets the autobaud rate for both the transmitter and the receiver. the receiver can continue to receive data unless there is a need to reconfigure the options (see receive on page 13-6). the transmitter can now be enabled by setting the tmode bit to 1. asynchronous serial ports (uarts) 13-8 am186?cc/ch/cu microcontrollers users manual 13.5.2 data in asynchronous serial port communication, data is transmitted in frames . each frame begins with a start bit (low) and ends with one or two stop bits (high). after the start bit is transmitted, the data bits are transmitted serially, least significant bit first. data can be 7 or 8 bits, plus an optional address bit. for more information, see address bits on page 13-9. the data bits may be followed by an optional parity bit. a parity bit ensures there is an even or odd number of bits in the transmission. the uarts support even, odd, or no parity. even parity forces an even number of 1s in the data field by changing the parity bit as needed; odd parity forces an odd number of 1s. parity checking allows the detection of single bit errors in each frame. the uarts also support transmission of either one or two stop bits. a second stop bit increases the spacing between back-to-back serial frames and can be useful in reducing frame errors due to clock frequency inconsistencies between devices. all these options are configured by bits in the (h)spcon0 register. the txd line is always held high between frames. in asynchronous serial communication, an idle line can be differentiated from an active receive line by the absence of start bits in the data stream. in other words, a transmission of a data stream of ffh in n-8-1 mode (no parity, eight data bits, one stop bit) results in a low bit, the start bit, every tenth bit time. when the line is truly idle, there are no low bits. the uarts set the idled bit in the (h)spstat register when 40 bit times have elapsed without a low bit and there is unread data in the receiver. figure 13-2 shows the frame configuration and the bit stream sequence for the uarts. figure 13-3 shows the timing for a transmission or a receive. figure 13-2 uarts frame figure 13-3 uarts timing 13.5.2.1 data overflow the uart registers contain two bits to handle receiver overrun errors: oer and oerim. an overrun error occurs when the serial port overwrites valid, unread data in the receive data register or receive fifo, resulting in a loss of data. stop bit 7 data bits optional 8th data bit optional address bit optional parity bit optional 2nd stop bit start bit serial clock txd or rxd idle 0 1 0 1 1 0 0 idle asynchronous transmission of 03ah as 8 bits of data (lsb first), even parity, one stop bit 1 stop parity start asynchronous serial frame serial data asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-9 the oer bit in the (h)spstat status register is set to 1 when the receiver has a data overrun error. when extended reads are enabled, the oer bit in the (h)sprxd receive data register is set to 1, and then a 1 is written to the oer bit in the status register. when fifos are enabled, the oer bit in the receive data register is passed through the fifo with the last character of overrun data (i.e., the first data character after the overrun loss). the oerim bit was added to provide an immediate interrupt. this bit bypasses the fifo; oerim is set immediately after the overflow occurs. both the oer and oerim bits must be cleared by software. 13.5.2.2 address bits when set, an address bit indicates that the present frame is a special frame. on the microcontroller, address bit generation and detection are supported in 7- or 8-data-bit frames. when the address bit is set, the other 7 or 8 bits of data in the frame are interpreted as a code; which type of code depends on the configuration. all transmissions that follow this address frame are directed as specified until another frame is received with the address bit enabled and with a different code. one possible use for the code following the address bit (resulting in its name) is for the address of a slave peripheral device on a multidrop (also called multipoint ) serial line, where one master device is talking to multiple slave devices. although named an address bit, this bit actually behaves as an extended bit that may set an interrupt; the data bits that follow the bit do not need to be used as an address. another possible use is for encoded discrete commands (e.g., sending a hang-up command to a modem). what the code is used for, and how, is determined by software. to use the address bit in the microcontroller, the aben and d7 bits in the (h)spcon0 register must be configured. in addition, the transmit ab bit must be set for a transmit; the received ab bit is set by hardware for a receive. when the aben bit is set to 1, address bits are enabled. if the d7 bit is 0, serial frames contain a low start bit, eight data bits, an optional address bit, then one or two high stop bits (transmitted least significant bit first). if the d7 bit is set to 1, serial frames contain a low start bit, seven data bits, an optional address bit, and one or two stop bits. 13.5.2.2.1 transmitting with address bit set when aben is set in a transmit, the transmit ab field of the (h)spcon0 register is sent as the msb bit after the 7 or 8 data bits in tdata. when extended writes are enabled (exdwr = 1), the transmit ab bit in the (h)sptxd register is used instead. because this register also contains the data to be transmitted, this allows a single write to replace the two writes needed when extended writes are not enabled. when extended writes are enabled, the (h)sptxd register supports word-wide dma transfers. when extended writes are not enabled, the value of the transmit ab field is sampled during the transmission of the final data bit and is used to determine the value of the txd signal for one bit time following the last data bit and before the transmission of the stop bit. the transmit ab field is cleared by the uarts after reading its value. because the transmit ab bit is not double buffered, software that intends to send a frame with the address bit set must wait until the transmitter is empty (temt=1) before setting the transmit ab bit and writing the data for the next frame into the transmit data register. asynchronous serial ports (uarts) 13-10 am186?cc/ch/cu microcontrollers users manual 13.5.2.2.2 receiving with address bit set in a receive, when aben is set in the hspcon0 register, the most significant bit of received data can be read in the ab bit in the (h)spstat register. the received ab bit can optionally generate an interrupt (if the ab bit is set in the hspimsk register and the rsie bit is set in the hspcon0 register). the received ab field must be cleared by software after reception of a frame for which the address bit was set. when using extended reads (the exdrd bit is set in the (h)spcon1 register), the ab bit in the (h)sprxd register is used instead. this allows reads from a single register, rather than requiring an additional read of the (h)spstat register. in addition, the ab bit in the (h)sprxd register is updated automatically; however, software must clear the ab bit in the (h)spstat register. 13.5.2.3 receive status and data the exdwr and exdrd bits in the (h)spcon1 register enable the programmer to use the upper bytes of the transmit data ((h)sptxd) and receive data ((h)sprxd) registers for transmitted data (the transmit and receive address bits and receive data status). receive status bits are set in the high-speed serial port status (hspstat) register when the associated data byte is available to be read from the receive data register. when fifos are enabled, this occurs when the byte reaches the top of the fifo. the read-only receive data ready (rdr) bit in the (high-speed) serial port status (h)spstat register reports when received data is available. this bit is cleared by hardware when there is no valid data waiting to be read from the (h)sprxd register. if fifos are enabled, the fifo is advanced and the next byte reaches the top of the fifo when the previous data is read. under some conditions, such as when the dma interface is being used, it may be useful for software to be able to examine the received character without affecting the status register or removing the data from the fifo. the uarts support this through the use of an alternate address for the receive data register (in the (h)sprxdp register). this address allows software to peek at the value of the receive data register. 13.5.2.4 extended reads and writes both serial ports on the microcontroller support extended reads of the receive data register and extended writes of the transmit data register. when extended reads are enabled, by setting the exdrd bit in the (h)spcon1 register to 1, the serial port receive register supports 16-bit reads. the low byte of the register contains the normal receive data while the high byte contains status associated with the current frame, including the value of the address bit. see the am186?cc/ch/cu microcontrollers register set manual , order #21916, for a full description. unlike the serial port status register, the high byte of the receive data register in extended reads reflects only the current frame. the accumulated status can be read from the status register normally and bits set in the status register must be cleared by software. when extended writes are enabled, by setting the exdwr bit in the (h)spcon1 register to 1, the serial port transmit register supports 16-bit writes. unlike extended reads which have a broad application, extended writes are useful only for applications that are using the address bit. when extended writes are enabled, the value of the address bit is written directly to the transmit register. this eliminates the need to write the address bit value to the (h)spcon0 register. both extended reads and extended writes support word-wide dma transfers. this allows full automation of the transmission of data streams containing address bits. if dma is enabled with extended reads, status for each frame is stored along with the data for that asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-11 frame. at the end of the receipt of a sequence of frames, software can examine the value of the (h)spstat register to determine if any significant status bits have been set. if the accumulated status does not reflect action required by software, the status bytes can be ignored, otherwise software can traverse the buffer searching for the status of interest and its associated data byte. the microcontroller's general-purpose dma channels support compression and decompression of data streams in part to support the extended read and write features of the serial ports. status can be removed from a data stream through data compression using the dma. for more information, see chapter 8, dma controller. 13.5.3 fifos (high-speed uart only) the high-speed uart provides a 32-byte fifo for receive data and a 16-byte fifo for transmit data. the use of the fifos can be enabled or disabled by software. the fifos can be operated in polled or interrupt mode, or they can be serviced using the general- purpose dma channels. the high-speed uart status register provides the rthrsh and tthrsh bits, which reflect the state of the receive and transmit fifos, respectively. when the rthrsh bit is set, the receive fifo has reached its threshold value (i.e., the receive fifo is at least half full). when the thrsh bit is set, the transmit fifo has reached its threshold value (i.e., the transmit fifo is at least half empty). the hspimsk register contains bits that enable or disable interrupt generation based on the rthrsh and tthrsh bits. in this case, interrupt generation on the rdr (receive data ready) and thre (transmit holding register empty) bits should be disabled. fifos are initialized to the empty condition on reset. for subsequent transfers, the transmit fifo and the receive fifo should be flushed by software by setting the tflush and rflush bits in the hspcon1 register. all transmit data is written to a single address, which is addressable as the transmit data register (hsptxd) in both fifo and non-fifo modes. when the fifo is not full, the high- speed uart status register has the thre bit set, indicating that data can be written to the fifo without overwriting previously written data. receive data is read from a single address, which is addressable as the high-speed uart receive data (hsprxd) register in both fifo and non-fifo modes. when the fifo is not empty, valid data can be read from hsprxd; this is indicated by the receive data ready (rdr) bit in the hspstat status register. when the last bit of data has been removed from the fifo, the rdr bit reads 0. the status associated with each of the fifo entries can be determined by reading the serial port status (hspstat) register before the associated data is read from the fifo. when a byte is read from the fifo, the next received character and its status move to the top of the fifo and can be read from the receive data and status registers. the status must be read before the data is read. alternatively, extended reads can be enabled. extended reads allow status to be read with data as it moves to the top of the fifo. reading the status using extended reads differs from what is shown in the serial port status register in that it reflects the current frame only. the serial port status register functions normally during extended reads and continues to reflect accumulated status and to generate interrupts based on that status as configured. 13.5.3.1 transmit fifo the transmit fifo provides for up to 16 bytes of transmit data plus the value of the associated address bit, if applicable. asynchronous serial ports (uarts) 13-12 am186?cc/ch/cu microcontrollers users manual when both the fifo and a transmit have been enabled (with the tfen and tmode bits), hardware immediately checks the transmit fifo threshold reached (tthrsh) bit in the status register. the transmit fifo threshold value is set to half-empty (fifo contains eight bytes of data) and is not programmable. the high-speed uart can be programmed to generate a maskable interrupt when the transmit fifo reaches the threshold value. software must clear the tthrsh bit, but hardware can set it again immediately if the fifo contains less than eight entries. fifo underflow occurs when the transmit fifo becomes completely empty. the high- speed uart can be programmed with the temt bit to generate an interrupt on fifo underflow. 13.5.3.2 receive fifo the receive fifo provides for up to 32 bytes of receive data along with status associated for each byte, including special-character matching, framing and parity error flags, and the value of the address bit, if applicable. when both the receiver and the receive fifo have been enabled, through the rmode bit for the receiver and the rfen bit for the receive fifo, the serial port hardware immediately checks for a receive fifo threshold reached condition. the receive fifo threshold value is not programmable and is set at half full or 16 bytes of data present in the fifo. the high- speed uart can be programmed to generate a maskable interrupt when the receive fifo reaches the threshold value. software must clear the rthrsh bit, but hardware sets it again immediately if the fifo contains 17 or more entries. as data moves to the top of the fifo, the associated status is placed in the serial port status (hspstat) register. status bits are set by the hardware and must be cleared by software. the serial port can be configured to generate an interrupt based on serial port status. each status bit is individually maskable. if an interrupting status condition is detected in the serial port, dma requests from the receiver are disabled. this allows the interrupt service routine to read the data from the receiver (or to peek at the data through the hsprxdp register) and take appropriate action. enabling extended reads allows the status to be read in a word-wide read from the serial port receive data (hsprxd) register. the status data in the upper byte of an extended read reflects only the current frame. however, the hspstat register continues to be updated normally and set bits must be cleared by software. the idled bit in the hspstat register indicates instances where the threshold is never reached because less than 16 bytes of data were sent. the idled bit is set (and can be used to generate an interrupt with the hspimsk register) when the receive data line has been idle for 40 bit times and receive data is available. this bit must be cleared by software. fifo overflow occurs when the receive fifo is completely full and another character is received, resulting in the loss of data. in a fifo overflow condition, the last location of the fifo is overwritten with the last byte received. the high-speed uart can be programmed to generate a maskable interrupt on fifo overflow with the oerim bit. 13.5.3.3 using the fifos in polled, interrupt, or dma mode the high-speed uart fifos can be used in polled, interrupt, or dma modes. interrupt and dma modes are described in interrupt sources on page 13-19 and interface to general-purpose dma channels on page 13-21. when in polled mode, the high-speed uart behavior is similar to the non-fifo mode. in polled mode, software reads the received data by reading the hsprxd register. the hspstat register is updated with the status of the next frame after each read of the receive asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-13 data register. the new status is ored with the previous status, possibly accumulating status over multiple frames. for this reason, the status register must be read before the receive data register to ensure that the status being read is for the current frame. set status bits must be cleared by software. when extended reads are enabled, the high byte of the hsprxd register contains the status associated with the current frame; however, status continues to accumulate in the hspstat register. the rdr bit is set when data is available in the receive fifo (the value of this bit can be read from the hspstat register or from the high-byte of an extended read). when the rdr bit is set, valid data is present in the fifo. if receive status interrupts are enabled, an interrupt can be generated at the time an error is detected. the interrupt service routine must read data out of the fifo until the data which generated the interrupt reaches the top of the fifo. at this point, the status register reports the error condition. data to be transmitted is written to the transmit data register as in non-fifo mode. however, the transmit status reflects the disposition of the fifo. when the fifo is not full, the transmit holding register empty (thre) bit is set, indicating that the transmitter can accept more data. when the fifo is completely full, the thre bit is 0. when the transmit fifo and the transmit shift register are completely empty, the transmitter empty (temt) bit is set. at this point, the transmitter or fifo can be disabled without loss of data. 13.5.4 cts/rtr hardware flow control the microcontroller supports cts/rtr hardware flow control. each uart port is provided with two data signals (txd_u and rxd_u for the uart, and txd_hu and rxd_hu for the high-speed uart) and two flow control signals (cts_u and rtr_u for the uart, and cts_hu and rtr_hu for the high-speed uart). hardware flow control is enabled when the fc bit in the (h)spcon0 register is set to 1. in the cts/rtr protocol, the receiver asserts clear-to-send (cts) whenever there is room in the receiver for more data. the transmitting device should sample cts before beginning transmission of each frame. cts is deasserted when the start bit is detected for the last frame that can be read without data loss. when fifos are disabled, cts is deasserted after the start bit for each frame is detected and remains deasserted until the data is read from the receive data register. when the receive fifo is enabled, cts is deasserted after the start bit is received for the last frame that will fit in the fifo. the transmitter samples ready-to-receive (rtr) before transmitting the start bit of each frame. the rtr signal is not sampled during frame transmission. this allows the receiving device to deassert rtr any time before the end of the stop bit. the transmitter does not begin transmitting the start bit for the next frame while rtr is deasserted. the use of hardware flow control can eliminate the possibility of overrun errorsdata loss due to reception of new data before the last received data has been read. however, there can be an adverse effect on data throughput. for example, in the case where there is no receive fifo, transmission of a second data frame cannot begin until the previous frame's data has been read. without hardware flow control, transmission of the next frame may begin immediately, providing the receiver with one frame time to read the previous frame's data without data loss. use of fifos or dma reduces the impact of hardware flow control on data throughput. in multidrop systems, typically using the address bit feature of the microcontroller's serial ports, hardware flow control should not be enabled, or must be restricted to a single pair of active uarts. asynchronous serial ports (uarts) 13-14 am186?cc/ch/cu microcontrollers users manual figure 13-4 illustrates the behavior of the rtr_u signal. figure 13-5 illustrates the behavior of the rtr_u signal with the fifo. note that the rtr_u signal is deasserted as soon as the serial port begins receiving a character and is reasserted when the data is read from the receive data register. figure 13-4 rtr_u signal behavior figure 13-5 rtr_hu signal behavior with receive fifos 13.5.5 clock sources and baud rate the uarts have two possible clock sources, the processor clock or the uclk input signal. the possible clock configurations are shown graphically in figure 13-6. the xtrn bit in the (h)spcon1 register selects the clock source. the baud clock is generated by dividing the clock source by the value of the baud rate divisor ((h)spbdv) register. in addition, the high-speed uart supports automatic baud rate detection. the uarts select the clock from either the cpu clock or the uclk signal, independent of any other settings. in the am186cc and am186cu microcontrollers, the usbsof signal must not be enabled at the same time as uclk. rxd_u rtr_u rdr set rdr set received data read rdr cleared rxd_hu rtr_hu fifo byte 32 receiving byte 32 in fifo receiving byte 31 receiving byte 30 fifo read fifo full start bit for byte 32 cu cc asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-15 figure 13-6 uarts clock 13.5.5.1 programming the baud rate the formula for determining the baud divisor register value is: bauddiv = (clock frequency / (16 ? baud rate)) the maximum baud rate is 1/16th of the cpu clock. the processor clock frequency is the maximum clock frequency supported on the uclk input. table 13-3 shows the baud divisors for various baud rates and clock speeds. note that the baud divisor value (bdv) is shown in both decimal and hexadecimal. table 13-3 baud rate table for uarts serial port clock frequency (processor frequency or uclk frequency) 24 mhz 25 mhz 40 mhz 44.2 mhz 48 mhz 50 mhz baud rate divisor % error divisor % error divisor % error divisor % error divisor % error divisor % error 300 5000d 1388h 0 5208d 1458h 0 8333d 208dh 0 9208d 23f8h 0 10000d 2710h 0 10417d 28b1h 0 600 2500d 09c4h 0 2604d 0a2ch 0 4167d 1047h 0 4604d 11fch 0 5000d 1388h 0 5208d 1458h 0 1200 1250d 04e2h 0 1302d 0516h 0 2083d 0823h 0 2302d 08feh 0 2500d 09c4h 0 2604d 0a2ch 0 2400 625d 0271h 0 651d 028bh 0 1042d 0412h 0 1151d 047fh 0 1250d 04e2h 0 1302d 0516h 0 9600 156d 9ch 0.2 163d a3h -0.1 260d 0104h 0.2 288d 0120h -0.1 313d 0139h -0.2 326d 0146h -0.1 19200 78d 4eh 0.2 81d 51h 0.5 130d 82h 0.2 144d 90h -0.1 156d 9ch 0.2 163d a3h -0.1 38400 39d 27h 0.2 41d 29h -0.8 65d 41h 0.2 72d 48h -0.1 78d 4eh 0.2 81d 51h 0.5 57600 26d 1ah 0.2 27d 1bh 0.5 43d 2bh 0.9 48d 30h -0.1 52d 34h 0.2 54d 36h 0.5 115200 13d 0dh 0.2 14d 0eh -3.2 22d 16h -1.4 24d 18h -0.1 26d 1ah 0.2 27d 1bh 0.5 230400 7d 07h -7.5 7d 07h -3.2 11d 0bh -1.4 12d 0ch -0.1 13d 0dh 0.2 14d 0eh -3.2 460800 3d 03h 7.8 3d 03h 11.5 5d 05h 7.8 6d 06h -0.1 7d 07h -7.5 7d 07h -3.2 baud divisor cpu clock uclk divide autobaud clock (high-speed uart only) (hs)uart clock select clock for oversampling stage 1 oversample baud clock asynchronous serial ports (uarts) 13-16 am186?cc/ch/cu microcontrollers users manual 13.5.5.2 receiver bit sampling whenever the receiver is enabled and is not in-frame (i.e., no data frame is currently being received), it remains in a search-for-start-bit mode. in this mode, the receiver looks for a high to low transition of the rxd input. this sampling is done based on the divided baud clock. when a transition is detected, the receiver waits one-half bit-time, until the expected midpoint of the start bit, then resamples the rxd input. if rxd is sampled low, a valid start bit has been detected and the receiver enters in-frame mode. if rxd is sampled high, it is assumed that the initial transition was a glitch and the receiver remains in search-for- start-bit mode. while in in-frame mode, the receiver samples each bit one time at the expected midpoint for that bit. when the high-speed uart is configured in autobaud mode, the high-speed uart uses the undivided autobaud clock during the search for the high-to-low transition while in search-for-start-bit mode. when the transition is detected, the receiver enters start-bit- calibration mode. in this mode, the undivided autobaud clock is used to time the duration from the detection of the initial falling edge to the next rising edge of rxd. the number of autobaud clocks is divided by 16 and written to the baud divisor register. if the autobaud registers (hspab3Chspab0) are active, the value written to the baud divisor register may be provided by one of these registers. in either case, the receiver enters normal in-frame mode, as with frames that do not use autobaud, and the new value of the baud divisor is used to generate the baud clock for the next and subsequent bits. 13.5.5.3 detecting the baud rate automatically (high-speed uart only) the high-speed uart supports automatic baud rate detection (autobaud) by setting the abaud bit in the hspcon1 register to 1. when in autobaud mode, the detection of a transmission from high to low on the receive data signal causes the baud rate timer to begin counting. a transition from low to high stops the baud rate timer and causes the serial port to exit autobaud mode. the baud rate timer runs at the processor clock or at the external serial port clock rate if enabled (via the xtrn bit in the hspcon1 register). the closest possible baud-rate divisor is determined (rounded) and automatically programmed into the baud rate divisor (hspbdv) register. the data is reported in the receive data (hsprxd) register and can be read by software. for automatic baud rate detection to function correctly, the first data sent must be a low bit (the start bit) followed by a high bit (the least significant bit of the data). this allows the use of the hayes at interface, which requires the initial character to be an ascii character a. although a framing error may result, software should check the value of the initial character to verify that it matches the expected character. there is no automatic determination of parity use or sense, word length, or number of stop bits. figure 13-7 shows the possible error ranges that exist over 167 implied baud divisors. the worst-case % error occurs when the baud rate expected requires a real number baud divisor that lies halfway between two integer baud divisors and is rounded up. assuming 0.3% error is an acceptable error per bit, autobaud mode that selects a divisor above 166 should always yield acceptable results. for baud rates that require a baud divisor of less than 166, the end user must determine whether the high-speed uart autobaud capability is appropriate for the application. figure 13-8 illustrates autobaud detection under various frequencies. asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-17 figure 13-7 worst case % error per bit vs. baud divisor without autobaud enhancement figure 13-8 detectable baud ranges for various frequencies the microcontroller also offers an enhancement to autobaud detection. start bit width distortion can result in calculation errors. in instances where there is some system knowledge, baud divisor and threshold values can be programmed to allow for a 25C30% distortion in the width of the start bit.this method greatly increases the probability that the correct valid baud rate divisor is selected for higher baud rates, which are at highest risk. the microcontroller method makes use of the fact that, in most cases, valid baud divisor values used in a particular application are separated by several integers. four high-speed serial port autobaud registers are provided for this enhancement: hspab0, hspab1, hspab2 and hspab3. each register contains a divisor value and a threshold value. the hspab3 register must contain the largest programmed divisor value and threshold value, then hspab2, etc. when using fewer than four valid divisor values, software must clear the unused hspabx registers or leave them at their default values (00h). when the registers have been programmed, the high-speed uart compares the autobaud calculated baud rate divisor to the threshold values and selects one of the programmed valid baud rate divisors to use in subsequent data transfers. a calculated value less than 5 10 15 20 25 30 35 40 12345 67891011 166 167 worst case % error per bit = 1 C baud div baud div + .5 worst case % error per bit baud divisor 33% .3% .29% 4.3% error range worst case % error 50 45 20 25 30 35 40 baud rates (kbaud) frequency (mhz) 2 4 6 8 10 12 14 16 18 questionable (baud divisors < 166) autobaud detection baud divisor = 166 guaranteed (baud divisors > 166) autobaud detection asynchronous serial ports (uarts) 13-18 am186?cc/ch/cu microcontrollers users manual or equal to threshold 1 and greater than threshold 0 selects the divisor 1 value, and so on. a value greater than threshold 3 uses the calculated divisor value. if the registers are not programmed (are in reset state), the high-speed uart uses the autobaud calculated baud divisor value. figure 13-9 illustrates this concept. table 13-4 shows two examples of using the autobaud registers to enhance autobaud detection. figure 13-9 autobaud enhancement in autobaud mode, the receiver determines a value for the baud divisor register based on the sampled duration of the start bit. the start bit duration in clocks is converted to a value to be written to the baud divisor register by dividing by 16, as shown in programming the baud rate on page 13-15. the configuration in example a does not support a baud rate of 57600 since this baud rate is not represented in the table and requires a baud divisor less than that programmed in hspab3. in general, any baud divisor below the maximum divisor programmed in the table 13-4 examples of autobaud enhancement range example register abdiv abthrsh baud rate # of clocks in start bit baud divisors a) @24mhz hspab3 9ch a0h 9600 810hCa0fh 81hCa0h hspab2 4eh 80h 19200 350hC80fh 35hC80h hspab1 27h 35h 38400 190hC34fh 19hC34h hspab0 0dh 18h 115200 010hC18fh 01hC18h b) @48mhz hspab3 34h 32h 57600 310hC32fh 31hC32h hspab2 1ah 30h 115200 190hC30fh 19hC30h hspab1 0dh 18h 230400 010hC18fh 01hC18h hspab0 00h 00h abdiv0 abthrsh0 abthrsh1 abthrsh2 abthrsh3 abdiv1 abdiv2 abdiv3 smallest number programmed largest number programmed calc. divisor asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-19 hspabx registers, which is not programmed in the abdiv field for one of the hspabx registers, is unattainable for that system. in example b, the hspab0 register is not being used. the value of the abdiv field for hspab3 is greater than the abthrsh field for that register. although this is not the case for most systems, it is possible for the replacement divisor to fall outside of the range of sampled baud rates that generate that divisor. 13.5.6 interrupt sources all uart and high-speed uart interrupt sources require two interrupt enable bits to be set before that source is enabled to generate interrupts. the first level consists of three main interrupt enable bits in the (h)spcon0 control register. the receive interrupt enable (rxie) bit enables interrupts that indicate receive data is available (the rdr bit in the status register is 1). the receive status interrupt enable (rsie) bit enables interrupts on the condition or status of the received data. the transmit interrupt enable (txie) bit enables interrupts based on the status of the transmit data (whether the temt bit in the status register is 0 or 1). the (h)spimsk register contains the second-level interrupt bits. even if these bits are set to 1, interrupts are disabled if the corresponding first-level enable bit is not also set to 1. table 13-5 shows the interrupt sources for the uarts. all first-level enable bits default to off (0). the defaults for the second-level bits vary and are listed. note that when a receive status bit has generated an interrupt condition and extended reads are disabled, receive dma requests are inhibited. table 13-5 uarts interrupt sources interrupt enable 1 notes: 1. when the fifos are in use, high-speed uart rdr and thre should be disabled from generating interrupts. when using the fifos, high-speed uart rthrsh is the logical replacement for rdr, and tthrsh is the logical replacement for thre. (h)spcon0 1st-level enable bit (default) (h)spimsk 2nd-level enable bit (default) receive data ready rxie (off) rdr (on) receive fifo threshold reached rxie (off) rthrsh (off) overrun error on receive fifo rsie (off) oerim (off) transmit holding register empty txie (off) thre (on) transmit fifo threshold reached txie (off) tthrsh (off) transmitter empty, transmit fifo empty on high-speed uart txie (off) temt (off) parity error rsie (off) per (on) overrun error rsie (off) oer (on) framing error rsie (off) fer (on) break detected rsie (off) brk (on) address bit set on receive rsie (off) ab (off) character match on receive rsie (off) match (off) receive line idle detected rxie (off) idled (off) receive line idle rsie (off) idle (off) asynchronous serial ports (uarts) 13-20 am186?cc/ch/cu microcontrollers users manual 13.5.7 break detection and generation the uarts support detection of break characters. a break is defined as a constant low signal on the receive data line for one frame time or greater. this is reported as a zero character with the framing error (fer) and break (brk) status bits set in the (h)spstat register. (a framing error is the detection of a low signal during the stop bit time.) when a break is being transmitted, it only affects the output on the txd signal; it does not affect the timing of the transmit section of the serial port. in other words, the transmitter can be used to time the break by setting the brk bit when the transmitter is empty (temt=1), writing the transmit register with data, then waiting until the temt bit is set again before resetting the brk bit. note: the transmitter can only be used to time the break if hardware flow control is disabled. if flow control is enabled, setting the brk bit will still force the txd line low, but the receiving device may deassert the cts input, inhibiting the clocking out of the character in the transmit data register. the microcontroller also supports timing of idle frames (txd signal high) through use of a software configurable bit (brkval in the hspcon1 register), which controls whether to hold the txd line high or low when a break is being transmitted. receive status information is reported at the end of the frame time. figure 13-10 provides an example data stream (assuming no parity, 8 data bits, one stop bit). figure 13-10 break character example in this stream, the leading 1s are assumed to be an idle indication on the line. the first low bit is interpreted as the start bit of a frame, resulting in the first frame consisting of the stream 0 0100 0000 0, including start and stop bits. this is reported as a 02h character with a framing error. the stop bit for the first frame also acts as the start bit for the next frame, which is 0 0000 0000 0. this is reported as a 00h character with a framing error and a break character (the brk bit is set to 1). low bits following a break are ignored until the line returns to the high state. therefore, the next frame would be 0 0000 0000 1, which is a 00h character with no error status. 11111 0 0100 0000 0 0000 0000 0 001111 0 0000 0000 1 111111 line start bit data bits stop and idle frame 1 start bit data bits stop bit frame 2 line idle (sets break) sign. frame 3 asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-21 13.5.8 receive special-character matching (high-speed uart only) the high-speed uart provides a method of generating interrupts on special characters. up to six special characters can be matched. special-character matching is enabled by the men bit in the hspcon1 register. the special characters are written by software into three 16-bit character match registers (hspm0, hspm1, and hspm2). when character matching is enabled with the men bit, the incoming character is compared against all six special characters. applications using fewer than six special characters should program the extra compare registers with duplicates of valid special characters, as the default 0 is considered a valid character. if address bits are used, three bits (mab0, mab1, and mab2) in the hspcon1 register must also be used, one for each special-character register. when the mab bit and the address enable (aben) bit are both set, a received character must have the address bit set in order to match characters in the corresponding character match register. both the character and the address bit must match in order for a special character to be detected. if address bit detection and generation is not enabled, the value of the address-match bit is ignored during the comparison. for 7-bit character matching, the high bit of each byte in the character match registers should be cleared to zero. if address matching is enabled for 7-bit characters, the three match-address bits in the control register are used to determine the match, not the high bit of each byte in the character match register. when a special character is detected, the address match detected (match) bit is set in the status register. a maskable interrupt can be generated on this condition, using the hspimsk register. special-character matching has several possible applications, including the following: n use special character matching to implement software flow control using the xon/xoff protocol. n in a multidrop system, use special character matching to determine if a device's address has been broadcast. n once the address has been enabled in a multidrop system and a data stream is being received, use special-character matching to detect the flag that signals the end of a data packet. 13.5.9 interface to general-purpose dma channels the general-purpose dma channels can access either uarts receivers and transmitters. the receiver generates a dma request when the receive data ready (rdr) bit is set. the transmitter generates a dma request when the transmit holding register (thre) bit is set. this behavior is independent of the use of the high-speed uart fifos and the fifo thresholds. when a receive status condition that is configured to generate an interrupt request is detected, dma requests from the receiver are disabled. this leaves the data with the interrupting condition in the (h)sprxd register for easy examination by software in the interrupt service routine. when the receive fifo is enabled on the high-speed uart, the interrupt request is generated, and the dma requests are suspended when the data reaches the top of the fifo. dma requests are resumed when the interrupting condition is cleared by software. when extended reads are enabled, dma requests from the receiver are not disabled when an interrupting status condition is detected. in this situation, the status is maintained with asynchronous serial ports (uarts) 13-22 am186?cc/ch/cu microcontrollers users manual data in memory so that the association of status and data is not lost. this behavior is not affected by enabling or disabling the receive fifo on the high-speed uart. unlike the other status interrupts that move through the receive fifo with their associated data, the oerim bit provides immediate notification of an overrun error condition. software can determine where the overrun occurred since the oer status bit travels through the fifo with the associated data. the oerim error bypasses the fifo and does an immediate interrupt. when extended writes are enabled, the value of the address bit is written to the high byte of the (h)sptxd register. when extended writes are not enabled, the value of the address bit is taken from the value of the transmit address bit (ab) field in the serial port control register at the time that the data is written to the transmit holding register. this bit is cleared after each transfer of the data out of the holding register into either the transmit shift register or the high-speed uart fifo. when extended reads are enabled, the value of the address bit is read from the high byte of the (h)sprxd register, and also sets the ab bit in the status register. when extended reads are not enabled, the value of the received address bit is placed in the received address bit (ab) field of the (h)spstat status register and must be cleared by software. this means that applications needing to send or receive a string of characters with the address bit cleared can use dma to transfer the data to or from the serial port. applications that require the address bit set, or a mixture of the bit set and cleared, may use the dma but must take an interrupt each time the address bit is set. this is true regardless of the use of the fifo. for information about the use of the cts/rtr protocol with dma, see cts/rtr hardware flow control on page 13-13. for more information about using the uarts and dma, see chapter 8, dma controller. 13.5.10 hardware-related considerations the signals for the uart and flow-control for the high-speed uart are multiplexed with hdlc channel d. for more information, see table 13-1 on page 13-3. 13.5.11 software-related considerations n always program the configuration registers before setting the tmode or rmode bit to 1. n the most efficient data transfer operation (least software intervention, highest average data transfer rate, and least opportunity for fifo overrun) is when using fifos, dma, and cts/rtr flow control. n in a multidrop system, hardware flow control must be enabled for only a single pair of devices at any one time. n always flush fifos before new data transfers. n the uarts are multiplexed with hdlc. the interface 4 select (itf4) bits in the system configuration (syscon) register must be configured for the uart interface. asynchronous serial ports (uarts) am186?cc/ch/cu microcontrollers users manual 13-23 13.5.12 comparison to other devices the uarts are similar to those of the other am186 family microcontrollers and are most closely related to those of the am186es and am186ed microcontrollers. however, the functionality provided by the serial port modes of those devices have been replaced by individual enables that allow for more flexibility on the uarts and the configuration of the dma interface has been modified. in addition, both the uart and the high-speed uart of the microcontroller provide significant enhancements over previous uarts, including extended reads and writes, support for address bits on 7-data bit frames, and two stop bits. the high-speed uarts enhancements additionally include autobaud detection, receive and transmit fifos, and special character matching. 13.6 initialization on both external and internal reset, the following occurs: n all register bits are cleared to 0 except for the following second-level interrupt enable bits in the (h)spimsk registers: brk, rdr, thre, fer, oer and per. this provides compatibility with the am186es and am186ed microcontroller serial ports. n all uart and high-speed uart signals, except for txd_hu, default to that signals pio function. see table 13-1 on page 13-3. n the itf4 bit field in the syscon register is cleared, which defaults external interface d to hdlc with flow control. asynchronous serial ports (uarts) 13-24 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 14-1 chapter 14 synchronous serial port (ssi) 14.1 overview the am186cc/ch/cu microcontrollers each include one synchronous serial port, which uses the ssi to provide a half-duplex, bidirectional communications interface between the microcontroller and other system components (i.e., integrated circuits). this interface is typically used by the microcontroller to monitor the status of other system devices or to configure these devices under software control. in a communications application, these devices could be system components such as transceivers or audio coder-decoders (codecs). the ssi supports data transfer speeds of up to 25 mbit/s. the ssi provides the following features: n three i/o signals: sclk, sdata, and sden, multiplexed with pios n programmable data order: normal (least-significant bit first) or reverse (most- significant-bit first) n programmable ssi clock divisor: divides the cpu clock from 2 to 256 in power of 2 increments n programmable polarity of the sclk and sden signals n bidirectional transmit/receive shift register 14.2 block diagram figure 14-1 shows the block diagram for the ssi. synchronous serial port (ssi) 14-2 am186?cc/ch/cu microcontrollers users manual figure 14-1 ssi block diagram 14.3 system design table 14-1 lists the ssi signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. figure 14-2 illustrates a sample ssi application for the am186cc/ch/cu microcontrollers. . table 14-1 ssi multiplexed signals signal function multiplexed signal(s) default signal sden serial data enable pio10 pio10 sclk serial clock pio11 pio11 sdata serial data pio12 pio12 block select register offset read read data read data enable write data write data enable internal register control 5 registers/ control state machine bidirectional shift register synchronous clock register pad pad pads block decode transmit data receive data shift control clock control internal sdata drv_sdata sclk (feedback from pads) internal internal sden sden read data 16 x 5 register selects status state 4 16 control 16 8 8 sclk sdata sdata sclk synchronous serial port (ssi) am186?cc/ch/cu microcontrollers users manual 14-3 figure 14-2 synchronous serial interface system application example 14.4 registers the registers listed in table 14-2 program the ssi. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ ch/cu microcontrollers register set manual , order #21916. table 14-2 ssi register summary offset register mnemonic register name description 2f0h ssstat ssi mode/status defines ssi modes of operation and reports the port status. 2f2h sscon ssi control enables ssi and programs the data order, clock divisor, and polarity. 2f4h sstxd1 ssi transmit 1 contain the data to be transmitted. a write to either register initiates a transmit transaction if either of the de bits in sscon is set to 1. 2f6h sstxd0 ssi transmit 0 2f8h ssrxd ssi receive contains the data received over the ssi. a read from this register initiates a receive transaction if either of the de bits in sscon is set to 1. synchronous serial interface peripheral (multiplexed data in/out pin) synchronous serial interface peripheral (dedicated data in/out pins) am186cc/ch/cu microcontroller enable clk data enable clk data_in data_out sden sclk sdata pio synchronous serial port (ssi) 14-4 am186?cc/ch/cu microcontrollers users manual 14.5 operation 14.5.1 usage note: before using the ssi port, ensure multiplexed pins are configured to reflect the use of ssi and not other functionality (see table 14-1 on page 14-2). 1. set the enhctl bit in the ssstat register to 1 so that all bits in the sscon register are operational (unless am186em-backwards compatibility is required). 2. if using the sden signal, initialize the ssi port with the sscon register: clock polarity (clkp bit), device polarity (denp bit), transmit bit orderlsb or msb first (msbf bit), and the cpu clock divisor (clkexp bit field). if not using sden (but using a pio output as an external enable), use the pio set and pio clear registers to provide the external signal while using the de1 bit of the sscon register to provide internal enable. be sure the corresponding mask bit in the shmask register is set to disable the interrupt. 3. enable transmit or receive by setting the de0 or de1 bit in the sscon register to 1. 4. write data with the sstxd1/sstxd0 registers or read data with the ssrxd register (this sets the port busy (pb) bit in the ssstat register to 1). 5. wait for the dr/dt bit in the ssstat register to go to 0 to indicate the transmit or receive has completed. 6. disable the transmit or receive by clearing the de0 or de1 bit in the sscon register to 0. 14.5.2 master/slave configuration unlike the asynchronous serial ports described in chapter 13, asynchronous serial ports (uarts), the ssi port operates in a master/slave configuration, where the microcontroller operates as the master port. all other devices that communicate with the microcontroller through this interface are slave devices. the master initiates a transaction by transmitting a single byte. this byte tells the slave device whether the transaction is a read or a write and contains the device address. the microcontroller always drives the interface clock when an active communication transaction is present on the interface. slave devices cannot drive this clock. because pios can be used as external device enables, the microcontroller can support a number of peripheral devices. 14.5.3 signal interface the ssi port consists of three i/o signals: data (sdata), clock (sclk), and enable (sden). the three ssi signals are multiplexed with three programmable i/o signals (pio12Cpio10). these pins are pios by default, and can be individually reconfigured as ssi pins with the pio mode and pio direction registers. 14.5.3.1 sclk the sclk output synchronizes transmit and receive operations between the master (microcontroller) and slave (peripheral). based on the selected polarity of the sclk signal in the sscon register, sclk is at a constant high (default) or low (when inverted polarity is selected) level when a transmit or receive operation is not active on the interface. sclk derives from the internal cpu clock divided by 2, 4, 8, 16, 32, 64, 128, or 256. software specifies the divisor with the clkexp bit field of the sscon register. when a transfer is started, the microcontroller toggles this clock for the entire transaction. each individual transaction transfers eight data bits. the clock edge on which data is transmitted and received is programmable with the clkp bit in the sscon register. in the default condition, data is transmitted on the sdata pin on synchronous serial port (ssi) am186?cc/ch/cu microcontrollers users manual 14-5 the falling edge of the sclk signal and is received (latched into the microcontroller) on the rising edge of the sclk signal. in the inverted clock mode, data is transmitted on the sdata pin on the rising edge of the sclk signal and is received (latched into the microcontroller) on the falling edge of the sclk signal. when no transmit or receive transaction is active on the ssi, the sdata signal is three- stated (although it has a weak keeper to hold the last value driven on the sdata signal). when data is transmitted on the ssi from the microcontroller to another device, the sdata signal is driven and is stable after the falling edge (rising edge if in the inverted clock mode) of the sclk signal, providing the appropriate setup and hold time for the receiving device if that device latches this data on the rising edge (falling edge in the inverted clock mode) of sclk. 14.5.3.2 sdata when the microcontroller receives data from another device on the ssi, it latches the level driven onto the sdata signal by the transmitting device on the rising edge (falling edge if in the inverted clock mode) of the sclk signal. the transmitting device must meet the required setup and hold times relative to this sclk rising edge (falling edge if in the inverted clock mode). software writes data to be transmitted on the ssi by the microcontroller to either of the two ssi transmit registers (sstxd0 or sstxd1). the transmit registers are 16-bit registers but only the lower eight bits can be written and the upper eight bits are ignored. when a new value is written to one of the transmit registers, and software has previously enabled ssi and the external device (see the description of the sden signal below), the ssi shifts out the data written to the transmit register on sdata. to receive data from an external device, the microcontroller must initiate the receive transaction by toggling the sclk signal and sampling the sdata input. a receive transaction is initiated if the external device has been enabled (see the description of the sden signal below) and software reads the ssi receive data (ssrxd) register. the ssrxd register is a 16-bit register but only the lower eight bits contain valid data. if the external device is enabled, reading the ssrxd register causes the sclk signal to be toggled, generating eight low-to-high transitions (high-to-low transitions if in the inverted clock mode), and the level on the sdata signal is latched eight times and stored in the receive register bits. note that the initial data read (activating the read cycle) should be discarded. the ssi data order is configurable with the msbf bit in the sscon register. two modes are available: normal (lsb first) and reverse (msb first). a single configuration bit selects the mode and the selected mode is common for transmit and receive operations. in normal mode, the least significant bit (lsb) of the transmit data byte is shifted out first. for a receive operation, the ssi stores the first data bit received in the lsb of the receive register and stores the last data bit received in the most significant bit (msb) of the receive register. in reverse mode, the most significant bit (msb) of the transmit data byte is shifted out first. for a receive operation, the ssi stores the first data bit received in the msb of the receive register and stores the last data bit received in the lsb of the receive register. 14.5.3.3 sden the sden signal enables an external device for communication on the ssi bus. the microcontroller asserts this signal, under software control, before it initiates the transmit or receive operation to or from a device on the ssi. the de0 bit controls the state of this synchronous serial port (ssi) 14-6 am186?cc/ch/cu microcontrollers users manual signal. setting de0 asserts the sden signal. asserting sden enables the external device to which this signal is connected for communication on the ssi. writing the transmit register or reading the receive register initiates a data transfer on the ssi. software can configure the sden signal to be active high or low with the denp bit in the sscon register. for a receive operation, reading the ssrxd register when the synchronous serial data enable bits de0 and de1 of the sscon register are cleared returns the data in the register to the cpu without generating a receive transaction on the ssi. it is possible to support multiple devices connected to the ssi bus simultaneously. in one scenario, it may be possible to connect all the devices to the sden signal and develop a software protocol to manage individual device communication. alternatively, pio signals can serve as external device enables in addition to the provided sden signal. in this scenario, to communicate to one of the devices using a pio as an ssi enable signal, software must configure the pin as a pio output, force the pio to be asserted, and then set the synchronous serial data enable bit (de1) in the sscon register. setting this bit and asserting the pio enables the external device to which this pio signal is connected for communication on the ssi and writing the sstxdx register or reading the register initiates a data transfer. for a receive operation, reading the ssrxd register when the de1 and the de0 bits are cleared returns the data in the receive register to the cpu without causing a receive transaction to be generated on the ssi. note that the de0 and de1 bits can be set simultaneously to achieve proper receive/transmit operation. 14.5.3.4 ssi transactions in general, the ssi hardware provides software with a polled i/o mechanism to control its operation. in addition to the transmit register, the receive register, and the control register, one status register is provided. the ssi mode/status (ssstat) register provides software with busy, receive/transmit end, and error status. these bits are called pb (busy), dr/ dt (receive/transmit end), and re/te (error). a write to either sstxd1 or sstxd0, or a read to ssrxd while pb=1, sets the re/te bit and does not generate additional data transfers. for ssi transmit and receive transaction examples, see figure 14-3Cfigure 14-5. synchronous serial port (ssi) am186?cc/ch/cu microcontrollers users manual 14-7 figure 14-3 ssi multiple transmit with sden as external device enable figure 14-4 ssi multiple transmit with pio as external device enable sden sclk sdata set de0 bit write transmit register pb=0 dr/dt=0 pb=1 dr/dt=0 pb=1 pb=0 dr/dt=1 write transmit register pb=1 pb=1 dr/dt=0 write transmit register pb=1 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 clear de0 bit pb=0 dr/dt=0 lsb (normal shift order) msb notes: sden is configured to be active high in the scenario shown above. any pios used as ssi enables should be inactive while sden is active. the ssi data order is configured to be in normal mode (lsb first). the ssi clock is configured to be in normal mode. gpio sclk set pio bit write transmit register pb=0 dr/dt=0 pb=1 dr/dt=0 pb=1 pb=0 dr/dt=1 write transmit register pb=1 pb=1 dr/dt=0 write transmit register pb=1 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 clear pio bit sdata data set de1 bit clear de1 bit pb=0 dr/dt=0 data msb(reverse shift order)lsb notes: the sden signal should be inactive (de0=0) while the pio has enabled the receiving device. the ssi data order is configured to be in reverse mode (msb first). the ssi clock is configured to be in inverted clock mode. synchronous serial port (ssi) 14-8 am186?cc/ch/cu microcontrollers users manual figure 14-5 ssi single-transmit, multiple-receive with sden as external device enable 14.5.4 software-related considerations the ssi interface allows for a variety of software and hardware protocols: n signaling a read/write: in general, software uses the first write to the ssi to transmit an address or count to the peripheral. this value can include a read/write flag in the case where the device supports both reads and writes. n using sstxd1 as an address register: the sstxd1 register can be an address register that holds the value of the last address accessed, and the sstxd0 register can be the data transmit register. in this case, the current value in the sstxd1 register can be used by software to generate the next address or to determine if the last transaction was a read or a write. n using sstxd1 and sstxd0 as transmit registers for two peripheral devices: in some systems, it may clarify the code and aid in debugging to view the two data transmit registers as unique to different peripheral devices. this allows the last value transmitted to each device to be examined by debug code. 14.5.5 comparison to other devices the ssi is mostly backward-compatible with software written for the am186em ssi. additional features have been added to the ssi implementation. in its default mode, the ssi on the am186cc/ch/cu microcontrollers is backward-compatible with the am186em with the following exceptions: n the ssi status and configuration register locations in the address map are different. sden sclk set de0 bit write transmit register pb=0 dr/dt=0 pb=1 dr/dt=0 pb=1 pb=0 dr/dt=1 read receive register pb=1 pb=1 dr/dt=0 read receive pb=1 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 clear de0 bit pb=0 dr/dt=0 sdata (dummy read) read receive register (returns data from last transaction to cpu without generating another ssi transfer) register (returns data from last transaction to cpu and generates another ssi transfer) msb(reverse shift order)lsb notes: sden is configured to be active low in the scenario shown above. any pios used as ssi enables should be inactive while sden is active. the ssi data order is configured to be in reverse mode (msb first). the ssi clock is configured to be in normal mode. synchronous serial port (ssi) am186?cc/ch/cu microcontrollers users manual 14-9 n only one dedicated ssi enable pin is available. pios can be used for additional device enables if they are required. n software written for the am186em ssi that writes to the ssi status register does not work on the am186cc/ch/cu microcontrollers. n only the /2 and /4 clock modes are available unless software sets the enhctl bit in the ssstat register. features added to the ssi are: n programmable data order: normal (least-significant bit first) or reverse (most- significant-bit first) n programmable clock divisor: divide the clock from 2 to 256 in power of 2 increments n programmable polarity: sclk and sden 14.6 initialization on both external and internal reset, the following occurs: n ssstat is set to 0000h, which clears status and disables enhanced control mode. n sscon is set to 0400h, which sets sclk to active low, sden to active high, the lsb transmitted and received first, the clock divisor to 2, and disables ssi operation. n the sstxd0, sstdx1, and ssrxd registers are set to 0000h, which clears all data. n the multiplexed serial pins default to pio functionality (see table 14-1 on page 14-2). synchronous serial port (ssi) 14-10 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 15-1 chapter 15 high-level data link control (hdlc) note: only the am186cc and am186ch microcontrollers support hdlc. 15.1 overview in the open systems interconnection (osi) model, layer two is the data link layer. this layer provides control between physical nodes: link initialization, flow control, and error control. one protocol that performs this function is high-level data link control (hdlc). in hdlc, all transmissions are in frames. the iso/iec 3309 standard specifies this frame structure. the am186cc and am186ch microcontrollers provide hdlc channels, which are used to transmit and receive frames based on hdlc formats. as a layer 2 function, these channels only transmit or receive the data; upper layers in the osi model actually look at the data. an hdlc frame uses flags to determine the start and end of a frame.these flags provide frame synchronization. one flag may be used as both an end flag for one frame and the start flag for the next frame. although the am186cc and am186ch microcontrollers do not transmit such shared flags, they can receive and properly handle a shared flag. as illustrated in figure 15-1, an hdlc frame typically consists of a start flag, followed by an address field, a control field, an information field, a frame checking sequencing (fcs) field, and, finally, a closing flag. frames maintain data transparency a flag, mark, or abort embedded in the data is not recognizedby bit stuffing and bit unstuffing. bit stuffing (also called zero-bit insertion ) occurs when transmitting data; the transmitter inserts a 0 after five consecutive 1s. bit unstuffing (also called zero-bit deletion ) occurs when receiving data; between opening and closing flags, the receiver deletes any 0 received after five consecutive 1s. figure 15-1 hdlc frame in the transmit direction (data is leaving the microcontroller), you can program the hdlc controller to add the required frame checking sequencing field (crc error detection bytes) at the end of the frame, bit stuff the data as needed, and surround it with flags. (cyclic redundancy check (crc) is a method for checking errors in transmitted data.) in the receive direction (data is coming into the microcontroller), the hdlc controller searches for flags to determine the start and stop of the frame, removes any bit stuffing, and checks the crc error detection bytes. the hdlc controller can also check the address of the incoming frame and reject it if it has an incorrect address. ch cc address start-of-frame flag control information fcs flag delimiter frame header information field frame check sequence end-of-frame delimiter 8 bits 16 bits 8/16 bits 0Cn bits 8 bits 16 bits high-level data link control (hdlc) 15-2 am186?cc/ch/cu microcontrollers users manual the microcontroller uses fifos in both directions (16-byte transmit and 32-byte receive) to isolate the data requests from the system bus. the controller supports smartdma and programmed i/o for filling or emptying the fifos. each hdlc channel can connect to an external serial interface directly (nonmultiplexed mode) or can pass through a time slot assigner (multiplexed mode). an hdlc channel can connect to a raw data communications equipment (dce) interface in nonmultiplexed mode, to a pulse code modulation (pcm) highway interface in multiplexed mode, or to a general circuit interface (gci) in multiplexed mode. each hdlc channel has the same feature set but separate connections to its associated time slot assigner. for more information about how the hdlc channels can be connected externally, see chapter 16, hdlc external serial interface configuration (tsas). the hdlc channels support full-duplex data transfer at a rate of up to 10 mbit/s in raw dce and pcm highway modes, and up to 768 kbit/s in gci mode (system performance may limit total throughput). the microcontroller contains internal pcb registers for configuring the modes of operation, controlling the hdlc channels, monitoring and reporting status, and moving data. each hdlc channel consists of a transmitter, a receiver, and the interface (programmed i/o or smartdma). the am186cc microcontroller provides four hdlc channels, a through d, which support raw dce, pcm highway, and gci external interfaces. the am186ch hdlc microcontroller provides two hdlc channels, a and b, which support raw dce and pcm highway external interfaces. 15.2 block diagram figure 15-2 shows the block diagram for a single hdlc channel, including connections with the tsa and gci. cc ch high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-3 figure 15-2 hdlc, tsa, and gci block diagram transmit clock transmit data pcb registers loopback receiver transmitter pcb bus 32 x 8 fifo 16 x 8 fifo control/status interface control/status registers monitor time slot tic bus pad interface time mux clock mux data mux registers smartdma internal rtr tic bus control internal cts control control i/o out out receive data receive clock receive clk (a, b, c, d) transmit clk (a, b, c, d) receive data (a, b, c, d) transmit data (a, b, c, d) receive clk_a transmit clk_a receive data_a transmit data_a control i/o rxd rxc txc txd in in i/o i/o i/o smartdma bus pcb bus tsa gci hdlc control control/ time slot control channel channel controller controller controller status monitor control data tic bus control i/o cc cc high-level data link control (hdlc) 15-4 am186?cc/ch/cu microcontrollers users manual 15.3 system design table 15-1 lists the hdlc/tsa/gci signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. table 15-1 hdlc/tsa/gci multiplexed signals multiplexed signals function default signal ch external interface pios dce pcm gci uart a dce_rxd_a pcm_rxd_a gci_dd_a dce and pcm data input/ gci downstream pin dce_rxd_a dce_txd_a pcm_txd_a gci_du_a dce and pcm data output/ gci upstream pin dce_txd_a dce_rclk_a pcm_clk_a gci_dcl_a dce receive clock/pcm receive and transmit clock/gci receive and transmit clock dce_rclk_a dce_tclk_a pcm_fsc_a gci_fsc_a dce transmit clock/pcm frame sync clock/gci frame sync clock dce_tclk_a dce_cts_a pcm_tsc_a pio17 dce clear to send/pcm external buffer enable pio17 dce_rtr_a pio18 dce ready to receive pio18 b dce_rxd_b pcm_rxd_b pio36 dce and pcm data input pin pio36 dce_txd_b pcm_txd_b pio37 dce and pcm data output pin pio37 dce_rclk_b pcm_clk_b pio40 dce receive clock/pcm receive and transmit clock pio40 dce_tclk_b pcm_fsc_b pio41 dce transmit clock/pcm frame sync clock pio41 dce_cts_b pcm_tsc_b pio38 dce clear to send/pcm external buffer enable pio38 dce_rtr_b pio39 dce ready to receive pio39 c dce_rxd_c pcm_rxd_c pio42 dce and pcm data input pin pio42 dce_txd_c pcm_txd_c pio43 dce and pcm data output pin pio43 dce_rclk_c pcm_clk_c pcm_clk_c pio22 dce receive clock/pcm receive and transmit clock input/gci-to-pcm conversion clock output pio22 dce_tclk_c pcm_fsc_c pcm_fsc_c pio23 dce transmit clock/pcm frame sync clock input/gci-to-pcm conversion frame sync output pio23 dce_cts_c pcm_tsc_c pio44 dce clear to send/pcm external buffer enable pio44 dce_rtr_c pio45 dce ready to receive pio45 cc cc high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-5 15.4 registers table 15-2 lists the 25 unique registers that control a single hdlc channel. the x shown in the register name can be a, b, c, or d, depending on the channel selected. the table shows the offset for channel a; for channel b, add 40h to the offset shown. both the am186cc and am186ch microcontrollers support channels a and b. the am186cc microcontroller also supports channel c and d. add 80h to the offset shown for channel c, and add c0h for channel d. in addition to the registers shown in table 15-2, the system configuration (syscon) register, offset 03f0h, has two bit fields that configure hdlc: itf4 (bits 9C8) and exsync (bit 7). in the am186cc microcontroller, the ift4 bit field configures the interface of hdlc channel d. setting the exsync bit causes the clock and frame information to be driven out of hdlc channel c. in the am186ch hdlc microcontroller, there is no hdlc channel d, but the itf4 bit field default value is 00b, specifying full hdlc with flow control. therefore, software must change the value of the itf4 bit field to 10b before using the uart interface or high-speed uart with flow control. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. d dce_rxd_d pcm_rxd_d rxd_u pio26 dce and pcm data input/ uart data receive pio26 dce_txd_d pcm_txd_d txd_u pio20 dce and pcm data output/ uart data transmit pio20 dce_rclk_d pcm_clk_d rtr_u pio25 dce receive clock/pcm receive and transmit clock input/uart ready-to-receive pio25 dce_tclk_d pcm_fsc_d cts_u pio24 dce transmit clock/pcm frame sync clock input/uart clear- to-send pio24 dce_cts_d pcm_tsc_d cts_hu pio46 dce clear to send/pcm external buffer enable/high- speed uart clear-to-send pio46 dce_rtr_d rtr_hu pio47 dce ready to receive/high- speed uart ready-to-receive pio47 table 15-1 hdlc/tsa/gci multiplexed signals (continued) multiplexed signals function default signal ch external interface pios dce pcm gci uart cc cc cc cc ch high-level data link control (hdlc) 15-6 am186?cc/ch/cu microcontrollers users manual table 15-2 hdlc register summary offset 1 register mnemonic 2 register name description 00h hxcon hdlc channel control sets operating modes for both the transmitter and receiver. 02h hxtcon0 hdlc channel transmit control 0 sets operating modes for transmitter. 04h hxtcon1 hdlc channel transmit control 1 06h hxrcon0 hdlc channel receive control sets operating modes for receiver. 08h hxrcon1 hdlc channel receive max length sets maximum length for received frame. should never be set to 2 or less. 0ah hxstate hdlc channel status contains read-only status for transmitter and receiver. 0ch hxistat0 hdlc channel interrupt status 0 contains status for transmitter and receiver. all bits can generate an interrupt if not masked off in hximsk0. 0eh hximsk0 hdlc channel interrupt 0 mask mask register for hxistat0. when a mask bit is 0 (the reset value), the corresponding interrupt is masked off. 10h hxistat1 hdlc channel interrupt status 1 contains status for receiver. all bits can generate an interrupt if not masked off in hximsk1. 12h hximsk1 hdlc channel interrupt 1 mask mask register for hxistat1. when a mask bit is 0 (the reset value), the corresponding interrupt is masked off. 14h hxtd hdlc channel transmit fifo data contains data for transmission. 16h hxrd hdlc channel receive fifo data contains data from receive. after all the data has been read, this register contains the three bytes of status for the frame, as described below. h x rfs1 hdlc channel receive frame status 1 contains the first byte of status: the least significant byte of the length of the received frame. hxrfs2 hdlc channel receive frame status 2 contains the second byte of status: the most significant byte of the length of the received frame. hxrfs3 hdlc channel receive frame status 3 contains the third byte of status: the status for the frame and which address was matched. 18h hxrdp hdlc channel receive fifo data peek copy of hxrd register that does not change when read. 1ah hxsfcnt hdlc channel short frame counter contains the count of the number of frames that were discarded because they were smaller than the minimum receive length. reading this register resets it to 0. 1ch hxsfcntp hdlc channel short frame counter peek copy of hxsfcnt register that does not change when read. 1eh hxmacnt hdlc channel mismatch address counter contains the count of the number of frames that were discarded because they did not match any of the address registers. reading this register resets it to 0. high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-7 15.5 operation 15.5.1 usage note: before using the hdlc channels, configure the multiplexed pins for hdlc use (see table 15-1 on page 15-4). when using hdlc channel d on the am 186cc microcontroller, be sure to configure the itf4 bit in the syscon register correctly. the hdlc portion of the microcontroller is an extremely flexible serial communications block that can be configured to support data movement in a variety of applications. when initializing the hdlc channels for a particular operation, it is best to establish the time slot assigner and general hdlc functionality before beginning data reception or transmission. configure hdlc functionality through the hxcon, hxtcon0, hxtcon1, and hxrcon1 registers. establish address matching through the address match registers and their associated masks. finally, enable the desired interrupts by setting the corresponding bits in the appropriate mask registers. to configure the hdlc channels, use the following procedure: 1. configure the time slot assigners (tsas) as described in usage on page 16-7. 2. configure any required hdlc channel operating modes: a. configure the nrzi encoding, transparent mode, loop remote, loop local, or crc type by programming the hxcon register. b. for transmissions, configure the flag idle, multidrop mode, automatic cts, bit order, clock invert, gci (on the am186cc microcontroller only), output drive, or transmit delay by programming the hxtcon1 register. 20h hxmacntp hdlc channel mismatch address counter peek copy of hxmacnt register that does not change when read. 22h hxa0 hdlc channel address 0 contains the value to compare to the address in the received frames. the address bits can be masked with hxa0msk. 24h hxa0msk hdlc channel address mask 0 mask register for hxa0. when a mask bit is 0 (the reset value), the bit is always matched. this means all frames are accepted when none of the mask bits are set. 26h hxa1 hdlc channel address 1 address match and mask registers. see descriptions for hxa0msk and hxa0. 28h hxa1msk hdlc channel address mask 1 2ah hxa2 hdlc channel address 2 2ch hxa2msk hdlc channel address mask 2 2eh hxa3 hdlc channel address 3 30h hxa3msk hdlc channel address mask 3 notes: 1. the x shown in the register name can be a, b, c, or d, depending on the channel selected. the offset shown is for channel a; for channel b, add 40h to the offset shown; for channel c, add 80h; and for channel d, add c0h. 2. the am186cc and am186ch microcontrollers support channels a and b; the am186cc microcontroller also supports channels c and d. table 15-2 hdlc register summary (continued) offset 1 register mnemonic 2 register name description high-level data link control (hdlc) 15-8 am186?cc/ch/cu microcontrollers users manual 3. set the necessary transmit enables (hxtxon0 register) and receive enables (hxrcon0 register) for each hdlc channel. 4. do an hdlc reset. a reset flushes the fifos and clears all r/0 status bits, but does not clear the r/w0 interrupt status registers. 5. clear all pending interrupts by writing 0s to the intsts register. 15.5.2 interface the hdlc channels operate in one of two modes: smartdma data transfer or programmed i/o. smartdma data transfer provides automated data movement to the transmit fifo or from the receive fifo. programmed i/o is intended for low data rates where processor intervention is possible on a byte-by-byte basis. 15.5.2.1 smartdma interface using the smartdma interface bypasses the hdlc status registers associated with data handling (hxstate, hxistat0, hxistat1, hxrfs1, hxrfs2, hxrfs3, hxasbmsb, hxasblsb) because the smartdma interface automatically places all data and status to and from the data buffers and buffer descriptors residing in memory. some applications still require additional status such as the link status. for more information about the smartdma interface, see chapter 8, dma controller. 15.5.2.2 programmed i/o interface 15.5.2.2.1 transmit programmed i/o interface to transmit a frame using programmed i/o, first program the control registers with the appropriate mode(s), then enable the transmitter. then, either poll a status bit indicating transmit space is available or use the transmit space available interrupt to determine when space is available in the transmit fifo. just after writing the last byte of a frame to the transmit fifo, set the last byte bit in the control register. when the last byte in the frame is written to the transmit fifo, the hdlc controller knows to append the crc (if enabled) and closing flag. when the last byte of the frame has been transmitted, the transmitter generates a maskable interrupt and sets a status bit. the interrupt register indicates if there was an underflow of the transmit fifo, if cts was lost during transmission, or if the transmit frame was aborted during transmission. when one of these conditions occurs, the hdlc controller flushes the transmit fifo and stops the transmitter until the appropriate status bit is cleared. 15.5.2.2.2 receive programmed i/o interface to receive a frame using programmed i/o, first program the control registers with the appropriate mode(s) and then enable the receiver. then, either poll a status bit (one receive data byte available) or take an interrupt (receive threshold reached or data byte available) to determine that data is available in the receive fifo. this data can then be read from the receive fifo interface register. a different status bit (received end of frame) is active to indicate that frame status is now available in the receive fifo. a maskable interrupt is also generated. the status consists of three bytes: the first two bytes are the frame byte count and the last byte is the general frame status. when performing a word (16-bit) read of the fifo, the lower byte contains the data and the upper byte indicates whether the lower byte is data or status byte one, two, or three. the upper byte also indicates whether the programmed fifo threshold has been reached and if any interrupts are pending. high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-9 the receive status indicates the following information: n if there was an overflow of the receive fifo n if a non-integer number of bytes were received n if a crc error was detected n which address was matched n if the frame was too short or too long n if the receiver was turned off during the frame n if the frame ended with an abort (one zero followed by seven to 14 consecutive 1s). at the end of frame 1, software must read the status of frame 1 from the receive fifo before it can read any data from frame 2. 15.5.3 general hdlc options these options involve both the transmitter and the receiver. for transmitter-specific options, see hdlc transmitter on page 15-10; for receiver-specific options, see hdlc receiver on page 15-14. n data clocks: each hdlc channel requires two clock sources: a transmit clock for the transmit data, and a receive clock for the receive data. n hdlc reset: to initiate hdlc reset, set the hreset bit in the hxcon register to 1. hdlc reset clears the hdlc channels and fifos and restores all status registers to their default values. hdlc reset does not affect the user-programmed control bits. n nrz/nrzi data encoding: the microcontroller supports both non-return to zero (nrz) and non-return to zero, invert on zero (nrzi) data formats. specify the encoding format with the nrzi bit of the hxcon register. n transparent mode: transparent mode disables zero-bit insertion and deletion, crc generation and checking, abort generation, and opening/closing flag generation. the hdlc controller transmits data exactly as it is loaded in the transmit fifo. when the fifo is empty, the controller generates idles (mark or flag) and does not set the abort bit. if cts is deasserted in transparent mode, the transmitter goes to the idle state. transparent mode also disables the receive byte counter; therefore, short frame and long frame errors are not reported. byte alignment is possible in all modes except raw dce. additionally, alignment is not possible when the entire time-multiplexed bus is allocated to a single tsa/hdlc channel. to enable transparent mode, set the transm bit in the hxcon register to 1. to use byte alignment when using transparent mode with a time-multiplexed data format, set, then clear, the hreset bit in the hxcon register after configuring the tsa and hdlc channels and establishing operation. the first byte received or transmitted may be corrupted while the hdlc channel is performing the alignment. to mask this effect on the transmit side, configure the transmitter to use mark idles and make the first transmitted byte all 1s (ffh). to maintain byte alignment, all time slot widths used must be a multiple of eight bits and there must be at least one empty time slot. hdlc requires the unused time slot to properly locate the byte boundary. if the transmit fifo underflows, the transmitter loses byte alignment. high-level data link control (hdlc) 15-10 am186?cc/ch/cu microcontrollers users manual n remote loopback mode: to enable remote loopback mode, set the loopr bit in the hxcon register to 1. remote loopback disables the transmitter and echoes the data received at the serial input out to the serial output. the receiver operates normally in this mode. n local loopback mode: to enable local loopback mode, set the loopl bit in the hxcon register to 1. local loopback mode disconnects the serial input and connects the serial output to the receiver input. the serial output can operate in three-state, open drain, or totem pole mode. n crc type: the algorithm for crc generation and checking can be crc-ccit, crc-16, or crc-32. specify the crc type in the crctype field of the hxcon register. n time slot assigner (tsa): each hdlc channel is tightly coupled with a tsa, which can operate in either multiplexed or nonmultiplexed (pass-through) mode. in multiplexed mode, the txclk input becomes the synchronization input and the tsa connects the receive clock to the transmit clock. in multiplexed mode, the tsa controller determines when to enable and disable the hdlc clock. it also allows the user to reduce the number of bits transmitted in a single 8-bit time slot. this reduction allows the transmission of data from 64 kbit/s down to 8 kbit/s in 8 kbit/s decrements. this feature allows the hdlc channel to be used for lap-d and reduced data mode lap-b transmissions such as 56 kbit/s. 15.5.4 hdlc transmitter the transmitter functions include: n opening flag transmission n data transparency (via zero insertion) n generation and transmission of the crc frame-check-sequence characters (if enabled) n transmission of the closing flag. figure 15-3 illustrates the block diagram for the transmitter. note: the hdlc transmitter requires at least one byte of data surrounded by flags: the start flag, one byte of data, and the end flag. a 2-byte crc with no data also constitutes a valid transmission. the hdlc receiver can receive only frames two bytes or longer. figure 15-3 hdlc transmitter block diagram flag/abort generator crc generator (16- or 32-bit) zero insert transmit transparent mode path parallel-to-serial shift register fifo serial from cpu output nrz/nrzi encoder end-of-frame ta g high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-11 the hdlc transmitters have the following features: n transmit fifo: the transmit fifo consists of a 16-byte fifo buffer, end-of-frame logic, and dma-request logic. when using programmed i/o to fill the transmit fifo, a bit must be set after the last byte in a frame is written to the fifo. the smartdma interface uses the terminal count signal from the dma controller. for more information, see chapter 8, dma controller. read the transmit fifo with the hxtd register. n transmit-fifo interface: when the transmit fifo requests data, it either generates an internal dma request or sets the tdata1 bit in the hxistat0 register indicating transmit space is available. this status bit being set can generate a maskable interrupt. n transmit-fifo threshold: the transmit fifo has three options for the level at which it requests data, specified in the tthrsh field of the hxtcon0 register: C when there is space available in the transmit fifo (tthrsh = 00) C when there are 9 bytes of fifo space available (tthrsh = 01) C when there are 16 bytes of fifo space available (tthrsh = 10) reaching the transmit threshold also generates a maskable interrupt (indicated in the tthres bit of the hxistat0 register). n transmit-space available: for programmed i/o, the tdata1 bit in the hxistat0 register indicates when there is space available in the transmit fifo. this indication is independent of the threshold selected. the space available status can also generate a maskable interrupt. n transmit-fifo underflow: when the transmit fifo underflows, it generates a maskable interrupt, enters the abort state, and reports a tuflo error status. n transmit-clock polarity: the transmit clock polarity is specified in the txcinv bit of the hxtcon1 register, independent of the receive clock polarity. this feature is recommended for use only in dce mode. n immediate-transmit start: when immediate transmit start is enabled, the transmitter begins transmitting as soon as data is available in the transmit fifo. when immediate transmit start is disabled, the transmitter does not start transmitting until the fifo is half full or the complete frame is in the fifo, whichever comes first. to enable immediate transmit start, set the imstart bit in the hxtcon0 register to 1. n flag- or mark-idle generation: the hdlc transmitter can transmit either flag- or mark- idles when the transmitter is enabled and is not actively sending a data frame (including the opening and closing flags) or an abort sequence. specify a flag idle by setting the flagidl bit in the hxtcon1 register to 1; specify a mark idle by clearing the flagidl bit to 0. a flag is 7eh (the sequence of one 0, six 1s, and one 0); a mark idle sequence is fifteen 1s; an abort sequence is one 0 followed by from seven to 14 consecutive 1s. to properly support multidrop configurations with collision detection, the hdlc transmitter should be configured to generate mark-idles. when transmitting flag- or mark- idles, the transmitter is in the idle condition. n flag generation with back-to-back frames : the minimum number of flags between frames transmitted is two. at least one closing flag is always generated at the end of a frame, and at least one opening frame is generated at the beginning of a frame (except in transparent mode). back-to-back flags are sent without sharing 0s (i.e., 011111 1001111110, not 011111101111110). high-level data link control (hdlc) 15-12 am186?cc/ch/cu microcontrollers users manual n abort generation: the hdlc transmitter sends an abort sequence (one 0 followed by seven to 14 1s) whenever the forabr bit of the hxtcon0 register is set to 1. the transmitter continues sending an abort sequence as long as this bit is set; however, if the send abort bit is set and cleared on two successive writes to the hdlc command/ control register, at least one abort character is sent. an abort is also sent if cts is lost while the transmitter is in-frame (and cts is enabled) or if a transmit fifo underflow occurs (unless in transparent mode). when in gci (am186cc microcontroller only) or multidrop mode, only one abort is sent and then the transmitter is turned off. n parallel-to-serial shift register: the hdlc transmitter loads the output of the transmit fifo or the flag/abort generator one byte at a time into the parallel-to-serial shift register and then shifts it out. transmission of a flag or abort sequence bypasses the zero-bit- insertion logic. n crc generator: the crc or frame check sequence (fcs) contains the generated crc code for the frame being transmitted. all data transmitted between the opening and closing flags (excluding inserted 0s) is included in the crc calculation. the transmitter appends the calculated crc to the end of the frame just before the closing flag. the transmitter supports the crc-ccitt, crc-16, and crc-32 algorithms, selected in the crctype field of the hxcon register. you can disable crc generation by setting the crcdis bit of the hxtcon0 register to 1. when crc is disabled, the transmitter does not append the crc bytes to the end of the frame. the disable option may be changed at any time before the last byte is to be transmitted. this ability allows programmed i/o to generate some frames with crc and some without crc. n zero-bit lnsertion: the zero-bit-insertion logic, also referred to as data transparency, ensures that the remote receiver does not recognize a flag, mark-idle, or abort embedded in the data. the zero-bit-insertion logic monitors the data stream between the opening and closing flags of a frame and inserts a 0 after detecting five contiguous 1s. zero-bit insertion does not operate in transparent mode or when generating flags, mark-idles, or aborts. n transmit enable: when transmit is disabled, the transmitter waits for the current frame to complete transmission (if there is one) and for status on that frame to be reported, then sets the transmitter stopped bit and begins transmitting either flags or marks depending on the selected idle condition. while transmit is disabled, the transmitter continues to fill up its internal pipe and fifo. if the transmit fifo contains data when transmit is enabled, the transmitter begins transmission within one bit time of when external cts is asserted. if the idle condition is flag-idle, the transmitter finishes the current flag before starting transmission of data. if the idle condition is mark-idle and at least 16 1s have been transmitted, the transmitter may not finish the current mark idle sequence before starting data transmission. to disable transmit, clear the hten bit of the hxtcon0 register. n transmit-fifo enable: normal operation requires both the transmit enable (hten) and the transmit fifo enable (tfifoen) bits of the hxtcon0 register to be set. clearing the tfifoen bit causes the transmit fifo data to be flushed. to avoid possible data loss, disable smartdma control before flushing the fifo. n output states: the serial data output pin on the dce interface (dce_txd_x) supports three-state (reset default), open drain, or totem pole operation under program control. the output must be set to open drain for proper operation in multidrop mode. specify the output state in the odrv field of the hxtcon1 register. n transmitter status: after transmitting a frame, the transmitter generates a maskable interrupt. if an error occurs during transmission, the transmitter stops. read the high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-13 transmitter status in the fabrst, ctslst, tuflo, tgoodf, and tstop bits of the hxistat0 register. n automatic cts : when automatic cts is enabled, the transmitter does not start transmission until cts is asserted. if the transmitter is transmitting (in-frame) and cts is deasserted, a lost cts has occurred. a lost cts halts transmission and generates an abort and a maskable interrupt. if cts is deasserted while the transmitter is in idle, the transmitter does not respond. in multiplexed mode, the transmitter ignores cts . if cts is deasserted in transparent mode while transmitting, the transmitter begins transmitting idles. when auto-enable cts is disabled, the transmitter ignores the cts input. auto-enable cts must be disabled for multidrop mode. to enable automatic cts , set the autocts bit of the hxtcon1 register to 1. n multidrop mode with collision detection: this mode requires the transmit data pin to be physically tied, externally, to the cts input pin. in addition, it requires the mark- idle flag, disabled auto-enable cts , and an open drain output. the hdlc channel delays transmission until it sees a programmable number of consecutive 1s on the cts input pin. specify the number of 1s to delay in the tdelay field of the hxtcon1 register. this feature provides some collision avoidance and a transmit priority based on the number of 1s waited for before transmission. when transmission begins, the transmitter samples the transmit data stream on the cts input and internally compares it to what is transmitted by the hdlc. upon detecting a difference, the transmitter generates a maskable interrupt (lost cts ), stops the data transmission, starts transmitting idle flags, disables transmit, and flushes the transmit fifo. to enable multidrop mode with collision detection, set the mltdrp bit of the hxtcon1 register to 1. n gci d channel contention resolution request: the transmitter asserts a signal when it wants to send data. in the am186cc microcontroller, the gci controller asserts a signal back indicating when access to the d channel is available. when the gciden bit of the hxtcon1 register is set to 1, the transmitter does not begin transmitting until the gci gives this indication. if the access signal is deasserted in the middle of transmission, the transmitter immediately transmits an abort, starts transmitting idles, generates a maskable interrupt, and indicates a lost cts status. at the end of transmission (after the closing flag), the transmitter briefly stops requesting access even if additional frames are to be transmitted. see chapter 17, general circuit interface (gci), for additional information. n transmit bit order: the transmitter supports the option of transmitting data msb first instead of lsb. to specify msb-first transmission, set the tmsbf bit in the hxtcon1 register to 1. this ability is typically used only in transparent mode. n transparent mode: the transmitter supports a transparent mode (set the transm bit of the hxcon register to 1) that transmits the data exactly as it appears in the fifo. transparent mode does no bit stuffing, no framing with flags, and does not support crc. transparent mode is useful for transmitting raw data streams such as audio data (for use with a codec or dsp). to achieve byte alignment, synchronize the transmitter by resetting the hdlc after configuring the tsa and hdlc. raw dce mode does not support byte alignment. additionally, byte alignment is not possible when the entire time- multiplexed bus is allocated to a single tsa/hdlc channel. to enable transparent mode, set the transm bit in the hxcon register to 1. transparent mode is the opposite of data transparency, where zero-bit insertion (bit stuffing) is used to ensure the receiver does not recognize a flag, mark-idle, or abort in the data stream. figure 15-4 and figure 15-5 show a typical transmit with auto-enable cts enabled. cts goes active to start the transmission, which begins with a flag. after the flag, three bits of data are transmitted before cts is recognized as going inactive. this forces txd high. cc high-level data link control (hdlc) 15-14 am186?cc/ch/cu microcontrollers users manual figure 15-6 shows another typical transmit with auto-enable cts enabled. at the end of the closing flag, cts is driven inactive. cts is actually driven inactive at the same time as the last bit of the byte before the flag, but it is not recognized until the next bit; therefore, a lost cts does not occur. figure 15-4 cts controlled start of transmit figure 15-5 cts controlled end of transmit figure 15-6 cts inactive at end of frame 15.5.5 hdlc receiver the receiver takes serial data, determines the frame boundaries, and transfers the data to a 32-byte receive fifo, where it is transferred to memory by the smartdma interface or under programmed i/o control. the smartdma interface automatically puts the frame status into the buffer descriptors. programmed i/o puts the frame status into the fifo at the end of the frame. the receiver functions include: n mark-idle and flag-idle detection n flag/abort recognition n zero-bit deletion n crc checking n address recognition figure 15-7 illustrates the block diagram for the receiver. cts tclk txd cts tclk txd tclk txd cts cts high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-15 note: the hdlc receiver requires frames two bytes or longer. the hdlc transmitter requires at least one byte of data surrounded by flags: the start flag, one byte of data, and the end flag. a 2-byte crc with no data also constitutes a valid transmission. figure 15-7 hdlc receiver block diagram the hdlc receivers have the following features: n flag/abort detection: a flag must be detected before starting to receive a frame. a frame ends and status is reported when the receiver detects a flag or abort sequence. the am186cc and am186ch microcontrollers support receiving back-to-back frames with only one flag between frames. in transparent mode, flag/abort delineation is disabled, and reception begins as soon as the receiver is enabled. reception continues until the receive fifo overflows. n zero-bit deletion : between the opening and closing flags, the receiver removes any 0 that appears after a string of five consecutive 1s (these 0s are added during transmission to prevent a data pattern from resembling an abort, or an opening or closing flag). n receive-byte counter: the receive-byte counter counts the number of bytes received between flags. if the number is less than a 4-bit programmable number, the frame has an error status reported, and part of the frame may be truncated. the receiver rejects very short frames (less than two bytes) and does not put them into the receive fifo. short frames (less than the value set in the minrl field of the hxrcon0 register) and very short frames each generate a separate maskable interrupt. frames that are truncated due to an abort condition do not count as short or very short frames. if the number of bytes received exceeds a 16-bit programmable number, current frame reception stops, an error status is reported, and the receiver begins to look for a flag. transparent mode operation disables the receive-byte counter. n receive-clock polarity: the receive-clock polarity is programmable through the rxcinv bit in the hxtcon0 register, independent of the transmit clock polarity. an inverted clock is recommended for use only in dce mode. n frame status: at the end of reception, the receiver places the receive byte counter value and one byte of frame status in the receive fifo. in programmed i/o mode, the frame status becoming available generates a maskable interrupt, indicated in the reof bit of the hxistat0 register. end-of-frame serial crc checker (16- or 32-bit) zero del. flag/abort detection address detector shift register shift register fifo short frame det. transparent mode path dma & threshold logic drq byte clock byte counter long frame det. input tag high-level data link control (hdlc) 15-16 am186?cc/ch/cu microcontrollers users manual n short-frame counter: the hxsfcnt and hxsfcntp registers indicate the total number of short frames received. the hxsfcnt register clears when read; hxsfcntp does not. this count also includes all very short frames. if the counter rolls over, it generates a maskable interrupt. this count does not include frames with mismatched addresses. n crc checker: when the receiver detects the closing flag, it examines the 16-bit (or 32- bit) crc. if it detects an error, it reports a status bit to that effect. the receiver supports the crc-ccitt, crc-16, and crc-32 algorithms. the receiver always places the crc in the fifo along with the rest of the frame data (that is, all data between flags is placed in the fifo). the crc checker is always enabled, but software can ignore the crc error status (byte 3 of the status read from the hxrd register). specify the crc type in the crctype field of the hxcon register. n serial-to-parallel shift register: output from the zero-bit-deletion unit feeds into a 16- bit shift register, which converts the serial stream into bytes. the receiver then feeds the parallel output of the shift register to the receive fifo one byte at a time. n address detection: the receiver uses address detection to determine whether to receive the current frame. each hdlc channel has four 16-bit matching address registers (the hxa0Chxa3 registers) and four corresponding 16-bit matching address mask registers (the hxa0mskChxa3msk registers). the mask register determines which of the first 16 data bits in the frame the receiver should compare to the corresponding address register and which to ignore. if all unmasked bits of at least one address match, the receiver accepts the frame; otherwise, it discards the frame and starts looking for the next flag. the frame status byte contains information about which address matched. n mismatch-address counter: the hxmacnt and hxmacntp registers keep count of the number of frames that did not have an address match. the hxmacnt register clears when read; hxmacntp does not. count rollover generates a maskable interrupt. the receiver checks all frames two bytes or larger for an address match. the receiver does not check the discarded very short frames. n receive fifo: the receive fifo consists of a 32-byte fifo buffer, end-of-frame logic, and dma-request logic. read the receive fifo at the hxrd register. n receive-fifo interface: the receiver uses either programmed i/o or the dma controller to unload the receive fifo. in programmed i/o mode, the rdata1 bit of the hxistat0 register indicates when data is ready to be read from the receive fifo. data ready also generates a maskable interrupt. the reof bit of the hxistat0 register (and a maskable interrupt) indicate when the frame status from the last frame received is available to be read from the receive fifo and data is no longer ready to be read. the next frame data is not available until that status bit is cleared. the smartdma interface automatically moves the frame status to the buffer descriptors at the end of the frame. n receive-fifo threshold : the receive fifo supports thresholds of 1, 8, 16, or 32 bytes under program control. specify the receive fifo threshold in the rthrsh field of the hxrcon0 register. the smartdma interface does not move data to memory until the receive fifo threshold is reached, indicated by the rthres bit of the hxistat0 register. when the receive fifo reaches the programmed threshold level, the data ready status stays set until the receive fifo is empty. at the end of a frame, the receive fifo outputs the remainder of the frame even if the receive fifo threshold is not met. n receive-data available: for programmed i/o, the rdata1 bit of the hxistat0 register indicates when there is a data byte presently available in the receive fifo. this indication high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-17 is independent of the threshold selected. the receiver can optionally generate a data- ready interrupt as well. n receive end-of-frame: for programmed i/o, the reof bit of the hxistat0 register indicates when any status bytes (that is, an end-of-frame) are present in the fifo. this indication is independent of the threshold selected. the receiver can optionally generate a status ready interrupt as well. n receive-fifo overflow: if the receive fifo overflows, it halts reception of the current frame, disables the receiver, deasserts rtr , and generates a maskable interrupt. the controller puts the overflow status into the receive fifo when space is available. the roflo bit of the hxistat1 register indicates when a receive-fifo overflow occurs. n bit residue: if the number of bits in a frame is not an integer multiple of eight, the receiver rejects the frame and reports the error status in the third status byte read from the hxrd register. the last byte reported of the frame may or may not contain the incomplete last byte of the frame. n receiver enable: when the receiver is disabled, the receiver continues to receive the current frame. when the current frame ends (including the closing flag), or immediately if not in-frame, the receiver deasserts the ready-to-receive (rtr ) signal, and generates a maskable interrupt. after the rtr signal is deasserted, the receiver does not receive any data. when the receiver is re-enabled, it asserts the rtr signal. after reasserting the rtr signal, it does not receive any data until it detects a flag and goes to the in- frame state. when the receiver is disabled in transparent mode, it immediately deasserts the rtr signal and stops reception. when the receiver is enabled in transparent mode, it immediately asserts the rtr signal and starts reception. disable the receiver by clearing the hren bit of the hxrcon0 register to 0. n receive reject: when receive reject is enabled, the receiver immediately stops reception of data and reports an error status if the event occurred while in-frame. the rtr signal is not affected. when receive reject is disabled, the receiver starts looking for a flag. to enable receive reject, set the rreject bit of the hxrcon0 register to 1. n receiver stop: when the receiver is stopped, the receiver immediately stops reception of data and deasserts rtr . the receiver also generates an error status if the event occurred while in-frame. to stop the receiver, set the rstop bit of the hxrcon0 register to 1. n link status: the status of the receiver is reported through the link status. the possible states are: flag idle, mark idle, abort, and in-frame. for each state, the receiver can generate a maskable interrupt when it enters the state. after receiving a flag, a continuous input of 1s goes directly to the mark-idle state without transitioning to the abort state. after exiting reset and a valid state is identified, the receiver always reports the last valid state detected. read the link status in the rtrs, aborts markis, flags, and frames bits of the hxstate register. read the interrupts for these states in the hxistat1 register. n receive bit order: the receiver supports the option of receiving data msb first instead of lsb first. to specify msb first reception, set the rmsbf bit of the hxrcon0 register to 1. this ability is typically used only in transparent mode. n transparent mode: the receiver supports a transparent mode that moves the data into the fifo exactly as it is received with no bit stuffing, flag/abort detection, or crc support. to achieve byte alignment, synchronize the receiver through an hdlc reset after configuring the time slot assigner (tsa) and the hdlc. raw dce mode does not support byte alignment. additionally, alignment is not possible when the entire time- high-level data link control (hdlc) 15-18 am186?cc/ch/cu microcontrollers users manual multiplexed bus is allocated to a single tsa/hdlc channel. to enable transparent mode, set the transm bit of the hxcon register to 1. figure 15-8 shows the assertion and deassertion of rtr with back-to-back flags. a real frame would contain additional data between the two flags. figure 15-8 rtr timing 15.5.6 hdlc and smartdma all smartdma channels support hdlc (the general-purpose dma channels cannot be used with hdlc). for information about using the smartdma interface, see chapter 8, dma controller. this section discusses some of the issues with using an hdlc channel as the transmitter and receiver. 15.5.6.1 hdlc transmitter the only complication with a normal hdlc transmit using smartdma transfer is that, if the packet to be transmitted is composed of more than one buffer and the buffer descriptors are stored from a task that is interruptible, the hdlc transmitter could start up and underflow if the task is interrupted before the last buffer descriptor is updated. to avoid this problem, delay setting the own bit in the first buffer descriptor until all the other descriptors have been completely set up, and set up the other descriptors in reverse order, that is, from last to first. if an error (such as a loss of cts or a fifo underflow) occurs during transmission of a packet, the transmitter stops until software clears the error condition in the hdlc controller. software can either poll for these error conditions or, preferably, set the hardware up to generate an interrupt when they occur. when such an error occurs, the software should take the following steps: 1. clear the smartdma control register txst bit to stop the dma. this stops the dma without clearing the own bit on the current buffer descriptor or going to the next buffer descriptor. 2. clear the hdlc error bit (ctslst or tuflo) in the hxistat0 register. this automatically flushes and restarts the fifo and re-arms the interrupt. 3. to resend the same packet that contains more than one buffer, software must: a. read the ctbd register to determine the current descriptor. b. back up to the start of the packet in the descriptor ring (find the descriptor with the stp bit set), setting the own bit in each buffer before the current buffer back to and including the buffer with the stp bit set. c. store the number of the descriptor, with the stp bit set, into the ctbd register. note that this technique does not work if buffers are reclaimed by the software as soon as their own bits are reset by the hardware. for this technique to work properly, buffers must not be reclaimed until an entire packet has been sent. rclk rxd rtr high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-19 4. finally, set the smartdma txst and poll bits to restart the dma and poll the current descriptor. if step 3 was executed to back the dma to the start of the packet, or if the dma was already at the start of the packet (e.g., if cts was lost during transmission of the first buffer in the packet), then the packet is resent. if step 3 was not executed, and the current dma descriptor does not have stp set, then the dma controller clears the own bit on the descriptor and reads in the next descriptor. the dma controller repeats this clearing of the own bit and stepping to the next descriptor until it encounters a descriptor with the own bit clear, or a descriptor with the stp bit set. in other words, if the current descriptor is not the first descriptor of a packet (stp bit is 0) and step 3 is not executed, the dma controller automatically starts up again at the next packet boundary (next buffer with stp set), and it is up to higher-level end-to-end protocols to notice that the current packet was not transmitted successfully and to resend it. 15.5.6.2 hdlc receiver under normal operation, when an hdlc packet is received, the smartdma interface stores it in one or more buffers, setting the stp bit in the first buffer descriptor, clearing the status bits in any middle buffer descriptors, setting the eop (end-of-packet) and error bits, and storing the total length in the last (or only) buffer descriptor. software must perform two tasks, which in some systems can be performed at the same time: n software must fill the buffer descriptors with pointers to available buffers and information about their size, and set the own bits to make them available to the smartdma interface. if software is late in performing this task, an rbu interrupt is generated. if software is so late that data is lost, an hdlc roflo interrupt is generated. software does not need to enable these interrupts or poll for this status. if software enables these interrupts, it does not need to take any action in response to the interrupts except to provide buffers to the descriptor ring (and reset the interrupt status bit in order to enable subsequent interrupts of the same kind) because the overflow status is reflected in the next packet stored to the ring. if software provides buffers in response to an rbu or hdlc roflo interrupt, the software can also set the dma poll bit. setting this bit causes the dma controller to notice that the own bit of the next buffer is set, sooner than the dma controller may have noticed it on its own. there is never any reason to set the poll bit for the receive buffer unless the dma controller run out of empty buffers. n software must examine the descriptors of buffers that have been received. software searches through the descriptor ring until it finds the first descriptor that either has the own bit set, or has the eop bit set, or until it gets to the last descriptor that it has made available to the hardware. when software finds a descriptor with the own bit reset and the eop bit set, it knows it has found the end of a packet. software then moves the descriptors off the ring, and sends the buffers to a higher-level task. if the error bits are set in the descriptor with the eop, software could simply recycle the buffers to the next free position in the ring, without sending them to the next layer. high-level data link control (hdlc) 15-20 am186?cc/ch/cu microcontrollers users manual 15.5.7 interrupts all interrupts are individually maskable. set the status bits in the hxistat0 and hxistat1 registers. mask interrupts in the hximsk0 and hximsk1 registers. 15.5.7.1 transmit interrupts the microcontroller provides the following transmit interrupts: n transmit threshold reached n data byte available n abort sent n lost cts n transmit fifo underflow n good frame transmitted n transmitter stopped 15.5.7.2 receive interrupts the microcontroller provides the following receive interrupts: n receive threshold reached n receive status available n data byte available n short frame counter rollover n mismatch address counter rollover n receive fifo overflow n flag idle state entered n mark idle state entered n abort state entered n in-frame state entered n rtr deasserted n short frame detected n very short frame detected 15.5.8 hardware-related considerations n the receive threshold (rthrsh) bits in the hdlc channel receive control 0 (hxrcon0) register specify the amount of data needed in the receive fifo before giving an interrupt. the possible values are: 1, 8, 16, or 32 bytes. the receive fifo threshold reached (rthres) bit in the hxistat0 register can generate an interrupt if this programmed threshold has been reached or exceeded in the receive fifo and there were no status bytes present in the fifo at that time. when rthres is set by hardware, the receiver reads the threshold value from the fifo without rechecking the status. if a status byte is put into the fifo after the rthres bit is set, after the first read of the fifo the receiver clears the bit, even if there is still a threshold number of data bytes in the receive fifo. therefore, when the rthres bit is set, the receiver can read the threshold number of data bytes consecutively. high-level data link control (hdlc) am186?cc/ch/cu microcontrollers users manual 15-21 n the receiver sets the one receive data byte available (rdata1) bit in the hdlc channel interrupt status 0 (hxistat) register when the current byte available is data; the rdata1 bit does not reflect the entire fifo contents. if the next byte is status and the following byte is data, the receiver does not set rdata1. 15.5.9 software-related considerations n after setting the hren bit to enable the receiver, the device software must reset the hdlc fifos by setting the hreset bit in the hxcon register. this clears any invalid data in the receive fifo that might be mistaken as the start of the data stream. invalid data is a concern when using transparent mode (transm = 1 in the hxcon register), because in transparent mode the receiver cannot rely on flag sequences to indicate the start of valid data. n when the hdlc channel is disabled, the fifo status reads as full. n in the am186cc microcontroller, hdlc channel d is multiplexed with the uart and with flow control on the high-speed uart. the interface 4 select (itf4) bits in the system configuration (syscon) register must be configured for the hdlc interface. 15.5.10 comparison to other devices in addition to hdlc, the hdlc channels support the sdlc, lap-b, lap-d, ppp, and v.120 communications protocols. the hdlc channels can also be used in transparent mode to support the v.110 protocol. the hdlc protocol is similar to these other bit-oriented protocols: n the advanced data communication control procedures (adccp) developed by the american national standards institute (ansi x3.66) is virtually identical to the hdlc protocol. n the link access procedure balanced (lap-b), adopted by the international telegraph and telephone consultative committee (ccitt) as part of its x.25 packet-switched network standard, is a subset of hdlc. n although not a standard, ibms synchronous data link control (sdlc) is in widespread use. sdlc is a subset of hdlc, with some differences. 15.6 initialization on both external and internal reset, the following occurs: n the multiplexed hdlc signals default to the signals shown in table 15-1 on page 15-4. n all hdlc registers default to 00h except the hxstate, hxtd, hxrd/hxrdp, and hxrfsx registers. n the itf4 bit in the syscon register is cleared, which defaults external interface d to hdlc with flow control. n the exsync bit in the syscon register is cleared, which configures hdlc channel c for raw dce or pcm highway modes. cc cc cc high-level data link control (hdlc) 15-22 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual 16-1 chapter 16 hdlc external serial interface configuration (tsas) note: only the am186cc and am186ch microcontrollers support the tsas. 16.1 overview time slot assigners (tsas) and muxing logic between the hdlc channels and the external communications interfaces of the chip provide flexible data path control on the am186cc and am186ch microcontrollers. this data path control, combined with flexible time slot allocation, allows the microcontrollers external data streams to take on a wide variety of forms. the am186cc microcontroller supports raw dce, pcm highway, and general circuit interface (gci) external data streams. the am186ch hdlc microcontroller supports raw dce and pcm highway external data streams. in the am186cc microcontroller, interface a not only allows for a dedicated dce/pcm hdlc path, but has the capability to multiplex gci/pcm data from each of the remaining nondedicated hdlc channels. depending on the application, each hdlc can communicate to the external world with or without a tsa. each tsa resides between a pcm highway internal bus and an individual hdlc channel. a tsas main function is to allow the transmission and reception of data to and from an individual hdlc by providing the appropriate hdlc clock and clock enable signals during its programmed time slot within an 8-khz frame. in nonmultiplexed mode (there is no time-division multiplexing), an individual external serial bus interface connects directly to an individual hdlc for both transmission and reception. configuring the microcontrollers muxing logic for a specific raw dce data path uses nonmultiplexed mode. in multiplexed mode (there is time-division multiplexing), all hdlc data that enters or leaves the microcontroller passes through a tsa. configuring the microcontrollers muxing logic and tsas for the multiplexed pcm highway uses multiplexed mode. external interface a is unique in that it allows multiple time slots, to and from each hdlc, to multiplex on and off this single interface. configuring the am186cc microcontrollers muxing logic and tsas for the gci data path also uses multiplexed mode. time slot selection allows up to 156 8-bit time slots within a time-division multiplexed (tdm) frame. each tsa channel can support a burst data rate to or from the hdlc of up to 10 mbit/s in dce and pcm highway modes. in all modes of operation, each channel is capable of supporting full-duplex communications. with a maximum data rate of 10 mbit/s and an 8-khz frame, each channel provides programmability to support a maximum of 156 time slots per tdm frame. (although the microcontroller supports up to 4096 bit positions, this requires a lower frame synchronization (frame sync) or a higher, unguaranteed clock rate.) ch cc cc ch cc cc hdlc external serial interface configuration (tsas) 16-2 am186?cc/ch/cu microcontrollers users manual in the am186cc microcontroller, time slot selection also supports isolation of gci b and d channels on separate hdlc channels. each tsa channel can support a burst data rate to or from the hdlc of up to 768 kbit/s in gci mode. the tsa controllers also generate control signals for programmable frame sync pulse polarity and individual channel time slot control output, which is asserted for the duration of the programmed time slot(s). the latter is routed externally for pcm highway applications and can be used in subscriber linecard applications where it is used as an enable for three- state data buffering on the pcm highway. the tsa controllers support adjustable channel sizing with the ability to define time slot start and stop points. this channel adjustment and placement feature is an essential factor for the creation of a gci frame. the adjustable sizing feature also allows the associated hdlc channel to be used for isdn lap-d and reduced data mode x.25 lap-b transmissions. for applications that do not use the entire allocated time slot but do require a defined polarity for the remaining unused bit positions, the tsa controllers provide the option of adding additional polarity bits (up to seven) to fill out the remaining bit positions. cc hdlc external serial interface configuration (tsas) am186?cc/ch/cu microcontrollers users manual 16-3 16.2 block diagrams figure 16-1 and figure 16-2 show simplified block diagrams for the tsa muxing. figure 16-3 shows a block diagram for a single hdlc channel, including connections with the tsa and gci. figure 16-1 block diagram for tsa multiplexing (am186cc communications controller) figure 16-2 block diagram for tsa multiplexing (am186ch hdlc microcontroller) rtr , cts muxing logic tdm1 dce1 tdm1 tsa mux rtr , cts hdlc tdm2 dce2 tdm2 tsa mux rtr , cts hdlc tdm3 dce3 tdm3 tsa mux rtr , cts hdlc tdm4 dce4 tdm4 tsa mux gci/pcm hwy. conversion hdlc dce2 dce3 dce4 external interface d external interface c external interface b external interface a dce1 gci a b c d cc rtr , cts muxing logic tdm1 dce1 tdm1 tsa mux rtr , cts hdlc tdm2 dce2 tdm2 tsa mux hdlc dce2 external interface b external interface a dce1 a b ch hdlc external serial interface configuration (tsas) 16-4 am186?cc/ch/cu microcontrollers users manual figure 16-3 hdlc, tsa, and gci block diagram (same as figure 15-2) transmit clock transmit data pcb registers loopback receiver transmitter pcb bus 32 x 8 fifo 16 x 8 fifo control/status interface control/status registers monitor time slot tic bus pad interface time mux clock mux data mux registers smartdma internal rtr tic bus control internal cts control control i/o out out receive data receive clock receive clk (a, b, c, d) transmit clk (a, b, c, d) receive data (a, b, c, d) transmit data (a, b, c, d) receive clk_a transmit clk_a receive data_a transmit data_a control i/o rxd rxc txc txd in in i/o i/o i/o smartdma bus pcb bus tsa gci hdlc control control/ time slot control channel channel controller controller controller status monitor control data tic bus control i/o cc cc hdlc external serial interface configuration (tsas) am186?cc/ch/cu microcontrollers users manual 16-5 16.3 system design lists the signals that are multiplexed with other microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. figure 16-4 illustrates an example application. figure 16-4 isdn pcm system application example table 16-1 hdlc/tsa/gci multiplexed signals (same as table 15-1) multiplexed signals function default signal ch external interface pios dce pcm gci uart a dce_rxd_a pcm_rxd_a gci_dd_a dce and pcm data input/ gci downstream pin dce_rxd_a dce_txd_a pcm_txd_a gci_du_a dce and pcm data output/ gci upstream pin dce_txd_a dce_rclk_a pcm_clk_a gci_dcl_a dce receive clock/pcm receive and transmit clock/gci receive and transmit clock dce_rclk_a dce_tclk_a pcm_fsc_a gci_fsc_a dce transmit clock/pcm frame sync clock/gci frame sync clock dce_tclk_a dce_cts_a pcm_tsc_a pio17 dce clear to send/pcm external buffer enable pio17 dce_rtr_a pio18 dce ready to receive pio18 isdn pcm transceiver pcm codec am186cc/ch microcontroller pcm_txd_a pcm_rxd_a pcm_fsc_a pcm_clk_a tdmdi tdmd0 fs tdmclk dxa dra fs pclk cc hdlc external serial interface configuration (tsas) 16-6 am186?cc/ch/cu microcontrollers users manual b dce_rxd_b pcm_rxd_b pio36 dce and pcm data input pin pio36 dce_txd_b pcm_txd_b pio37 dce and pcm data output pin pio37 dce_rclk_b pcm_clk_b pio40 dce receive clock/pcm receive and transmit clock pio40 dce_tclk_b pcm_fsc_b pio41 dce transmit clock/pcm frame sync clock pio41 dce_cts_b pcm_tsc_b pio38 dce clear to send/pcm external buffer enable pio38 dce_rtr_b pio39 dce ready to receive pio39 c dce_rxd_c pcm_rxd_c pio42 dce and pcm data input pin pio42 dce_txd_c pcm_txd_c pio43 dce and pcm data output pin pio43 dce_rclk_c pcm_clk_c pcm_clk_c pio22 dce receive clock/pcm receive and transmit clock input/gci-to-pcm conversion clock output pio22 dce_tclk_c pcm_fsc_c pcm_fsc_c pio23 dce transmit clock/pcm frame sync clock input/gci-to-pcm conversion frame sync output pio23 dce_cts_c pcm_tsc_c pio44 dce clear to send/pcm external buffer enable pio44 dce_rtr_c pio45 dce ready to receive pio45 d dce_rxd_d pcm_rxd_d rxd_u pio26 dce and pcm data input/ uart data receive pio26 dce_txd_d pcm_txd_d txd_u pio20 dce and pcm data output/ uart data transmit pio20 dce_rclk_d pcm_clk_d rtr_u pio25 dce receive clock/pcm receive and transmit clock input/uart ready-to-receive pio25 dce_tclk_d pcm_fsc_d cts_u pio24 dce transmit clock/pcm frame sync clock input/uart clear- to-send pio24 dce_cts_d pcm_tsc_d cts_hu pio46 dce clear to send/pcm external buffer enable/high- speed uart clear-to-send pio46 dce_rtr_d rtr_hu pio47 dce ready to receive/high- speed uart ready-to-receive pio47 table 16-1 hdlc/tsa/gci multiplexed signals (same as table 15-1) (continued) multiplexed signals function default signal ch external interface pios dce pcm gci uart cc cc cc hdlc external serial interface configuration (tsas) am186?cc/ch/cu microcontrollers users manual 16-7 16.4 registers table 16-2 lists the three unique registers that program each individual tsa. the x shown in the register name is a, b, c, or d, depending on the channel selected. the offset shown is for channel a; for channel b, add 08h to the offset. both the am186cc and am186ch microcontrollers support channels a and b. the am186cc microcontroller also supports channels c and d. add 10h to the offset for channel c and add 18h for channel d. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. 16.5 operation 16.5.1 usage note: before using the tsa channels, ensure multiplexed pins are configured to reflect the use of the external interface desired and not other functionality (see table 16-1 on page 16-5). configure the time slot assigner (tsa) controllers using the following process: 1. define the bit start position for the transmitted or received data frame for each specific tsa channel in the tsa channel bit start position (tsxstart) register. 2. define the bit stop position for the transmitted or received data frame for each specific tsa channel in the tsa channel bit stop position (tsxstop) register. 3. configure the operating modes for each specific tsa channel in the tsa channel configuration (tsxcon) registerchannel mode, channel frame sync pulse polarity, and channel adjust bit drive leveland enable each tsa channel by setting the en bit to 1. these bits may be set simultaneously but en cannot be set before steps 1C2. the tsas are now enabled for data transfers. for information about configuring hdlc channels to begin transferring the data, see usage on page 15-7. for information about using gci, see usage on page 17-5. table 16-2 tsa register summary offset 1 notes: 1. the x shown in the register name can be a, b, c, or d, depending on the channel selected. the offset shown is for channel a; for channel b, add 08h to the offset; channel c, add 10h; channel d, add 18h. both the am186cc and am186ch microcontrollers support channels a and b. the am186cc microcontroller also supports channels c and d. register mnemonic register name description 2c0h tsxcon tsa channel configuration configures and enables the tsa channel. 2c2h tsxstart tsa channel bit start position defines the time slot start position for transmit and receive data frames. 2c4h tsxstop tsa channel bit stop position defines the bit stop position for transmit and receive data frames. cc cc hdlc external serial interface configuration (tsas) 16-8 am186?cc/ch/cu microcontrollers users manual 4. to establish byte alignment in transparent mode, additional configuration is necessary as follows: a. enable transmit fifo (tfifoen bit), force abort (forabr bit), and transmit enable (hten bit) of the hxtcon0 register for each specific hdlc channel. b. enable receiver (hren bit) of the hxrcon0 register for each specific hdlc channel. c. toggle (set, then clear) hdlc reset (hreset bit) of the hdlc channel control register (hxcon) for each specific hdlc channel. d. clear hxistat0 and hxistat1 registers for each specific hdlc channel. the first byte received or transmitted may be corrupted while the hdlc is performing the alignment. this effect can be masked on the transmit side by configuring the transmitter to use mark idles and making the first byte transmitted all 1s (ffh). 16.5.2 programmable time slots each tsa is unique, and time slots can start and stop on any bit boundary within a time- division multiplexed (tdm) frame, up to a maximum of 4096 bit positions. frame boundary overlapping is allowed and occurs whenever the programmed bit start point exceeds the bit stop point. the microcontroller supports the isolation of 8-bit time slots from 0 to 155 on a standard 8-khz tdm frame (this limitation is due to the 10-mhz limitation of hdlc). the ability to define time slot start and stop points allows for adjustable channel sizing and placement. adjustable channel sizing enables the tdm data channel to or from an individual hdlc to support differing data rates. in the am186cc microcontroller, the channel adjustment and placement feature is an essential factor for the creation of a gci frame. in gci applications, the gci d channel must be size-adjusted to two bits and the gci b channels must be size-adjusted to eight bits (see chapter 17, general circuit interface (gci), for further information regarding b and d channel size and placement). the adjustable sizing feature also allows the hdlc channel to be used for isdn lap-d and reduced data mode x.25 lap-b transmissions such as 56 kbit/s. certain applications do not use the entire allocated time slot, but do require a defined polarity for the remaining unused bit positions. for these applications, the user is given the option of adding additional polarity bits (up to seven) to fill out the remaining bit positions. in short, the user must program a start point, a stop point, the number of bits remaining to complete the allocated time slot, and a polarity for the remaining unused bit positions. note: since a maximum clock rate of 10 mhz is supported, the utilization of the full 4096 bit range is sync rate dependent. for example, the standard 8-khz frame does not support bit ranges above 1250 bit positions or 156 8-bit time slots (this requires a clock rate higher than 10 mhz). applications capable of supporting lower sync rate frequencies can use the full bit range. 16.5.3 muxing logic for the most part, the muxing logic controls the path data takes from an hdlc to an external communication interface (or vice versa). the exception to this can be seen in the last mux stage on interface c in the am186cc microcontroller. here, one of the mux options provides an adjusted gci clock and frame sync source for external interface c. for more information, see gci frame sync and clock conversion on page 16-12. cc cc hdlc external serial interface configuration (tsas) am186?cc/ch/cu microcontrollers users manual 16-9 figure 16-5 on page 16-10 demonstrates the muxing logic for an isdn basic-rate gci interface. the muxes at each stage level have been removed for clarity. in their place is the end data path established after proper mux initialization. this figure illustrates the following: 1. adjustable time slot size: eight bits for each gci b channel and two bits for the gci d channel 2. isolation of single time slots 0, 1, and 3 3. gci b and d channel isolation 4. gci support 5. multiplexed mode for interface a (where multiple hdlc channels are multiplexed onto one line) depending on whether you are transmitting or receiving, figure 16-5 on page 16-10 can be read: stage 1, stage 2, stage 3; or stage 3, stage 2, stage 1. in stage 1, the gci controller extracts the gci monitor (mon), command/indicate (c/i), intercommunication (ic), and terminal interchip communication (tic) channels. at the end of stage 1, the hdlc data is multiplexed with the gci channel data (the b1-, b2- and d- channel isdn data is present as well as the gci mon, c/i, ic, and tic data). in stage 2, all channels are logically muxed onto one internal bus heading to and from interface a. the gci b and d channels are isolated. in stage 3, each hdlc clock is only active during the time slot for the channel it is to transmit or receive. tsa a is configured to enable hdlc clocks for gci channel d data. tsa b is configured to enable clocks for gci b2 channel data. tsa c is configured to enable clocks for gci b1 channel data. hdlc external serial interface configuration (tsas) 16-10 am186?cc/ch/cu microcontrollers users manual figure 16-5 isdn basic-rate gci application (am186cc communications controller) stage 1 stage 2 stage 3 stage 1 stage 2 stage 3 5c 81 7e 8f 3a 4b xx xx xx 8c 9a 8b xx xx xx xx 3a 4b xx xx xx xx xx xx gci with pcm conversion d-channel hdlc channel a b2-channel hdlc channel b b1-channel hdlc channel c d,c/i0, mr,mx mr,mx c/i1, b1 b2 3a 4b b1 b2 b1 b2 mon0 ic1 ic2 mon1 tic , d (2 bits: 10) t s a gci bus pcm bus internal external interface a hdlc controller d frame sync. sync adjuster clk external interface c gci conv. to pcm clk and sync time external interface d pcm highway 1 d (10xxxxxx) hdlc_clk hdlc_clk hdlc_clk hdlc_clk 0 a t s a b t s a c t s a d traffic traffic traffic cc hdlc external serial interface configuration (tsas) am186?cc/ch/cu microcontrollers users manual 16-11 16.5.4 external interfaces as mentioned previously, the am186cc and am 186ch microcontrollers external data streams can take the following forms: raw dce and pcm highway. when connecting directly to an individual hdlc, raw dce format is available. when hdlc data passes through a tsa, the pcm highway interface is available. in addition, the am186cc microcontroller supports the gci external data stream when hdlc data passes through a tsa. 16.5.4.1 raw dce raw dce is a synchronous serial bus generally used in modem and other high-speed serial applications, and runs at up to 10 mbit/s. the am186cc and am186ch microcontroller implementation requires transmit (tclk) and receive (rclk) clock inputs, has receive (rxd) and transmit data (txd), and the clear-to-send (cts ) and ready-to-receive (rtr ) flow control signals. 16.5.4.2 pcm highway pcm highway is a generic serial bus used to support a wide range of data rates (including e1/t1) and runs at up to 10 mbit/s. the am186cc and am186ch microcontroller implementation is composed of data transmit (txd), data receive (rxd), data clock (clk), frame sync clock (fsc), and time slot control (tsc ) signals. each of the individual pcm highway interfaces are pin-multiplexed with one or more of the following serial bus interfaces: raw dce and high-speed uart. in the am186cc microcontroller, the individual pcm highway interfaces are also pin- multiplexed with gci. a converted gci frame sync and clock interface for the pcm codecs is also multiplexed with one of the four pcm highway interfaces. for a listing of all the pin multiplexing, see table 16-1 on page 16-5. pcm channel configuration (e.g., channel size, channel length, channel placement, etc.) is provided through proper tsa initialization. 16.5.4.2.1 pcm highway applications the pcm highway implementation features the following: n every tsa can support a separate pcm physical interface simultaneously. n each pcm interface is pin-multiplexed with other serial bus interfaces. n all of the hdlc channels can be routed to pcm highway interface a. n each hdlc channel supports pcm channel time slot selection, fully configurable through the integrated tsas. n gci clock and frame synchronization conversion and routing directly from the gci to the pcm highway interface are supported for external codec applications. data is routed externally (with respect to the am186cc microcontroller) directly from the codec to the gci transceiver device for this type of application. n support for a time slot control signal that asserts for the duration of the programmed time slots. cc cc cc hdlc external serial interface configuration (tsas) 16-12 am186?cc/ch/cu microcontrollers users manual n targets the following external codecs (see table 16-3 on page 16-14): C amd am79c02/03 C amd am79c031 C motorola mc14555x C national tp305x family C national tp307x family C at&t t75xx family C ti/intel 291x family n targets the following external isdn transceivers (isdn requires three channels): C amd am79c30a/32a s/t C lucent t7237 u note: the am186cc microcontroller does not provide the pcm codec master clocks for gci applications. 16.5.4.2.2 gci frame sync and clock conversion to support a wide variety of external pcm codecs while in gci mode, the microcontroller divides down the gci clock frequency (which is twice the gci data rate) to match the pcm data rate. in addition to a divided-down clock, a programmable one-clock-prior-to-data frame sync (the programmability determines where the frame sync appears relative to a b channel time slot) provides the needed flexibility to support the targeted pcm codecs (listed previously). these two converted signals (converted gci frame sync and converted gci clock) are an output on the am186cc microcontrollers external communication interface c. all codec data movement is completely external to the microcontroller and is directly routed between the pcm codec and the gci bus. all external pcm codecs directly connected to the gci bus must meet all of the following conditions: 1. be configured to output data on the rising edge of the converted clock and input data on the falling edge of the converted clock (for gci bus compatibility). 2. be able to accept a one-clock-prior-to-data frame sync. 3. be able to accept an active high frame sync. 4. be capable of accepting a data clock frequency of 768 khz. note: the am186cc microcontroller only provides the pcm codec data/bit clock. the am186cc microcontroller does not provide the pcm codec master clock(s). figure 16-6 and figure 16-7 illustrate both frame sync programmability and gci conversion, respectively. cc cc cc cc hdlc external serial interface configuration (tsas) am186?cc/ch/cu microcontrollers users manual 16-13 figure 16-6 programmable frame sync figure 16-7 converted gci clock and frame sync gci b1 channel gci b2 channel 123456 70 12 3 frame sync programmed for channel b1 frame sync programmed for channel b2 0 7 fsc clk gci b1 channel gci b2 channel 123456 70 12 3 0 7 fsc clk cc bit 0 bit 1 dcl clk gci clock and frame sync pcm clock and frame sync gci data fsc fsc signifies the clock edge data is input signifies the clock edge frame sync is detected dont care for codec bit 0 bit 1 dont care for codec du solid line illustrates frame syncs minimum setup and hold times (with respect to dcl) dd cc hdlc external serial interface configuration (tsas) 16-14 am186?cc/ch/cu microcontrollers users manual 16.5.4.3 gci the am186cc microcontroller supports gci, which is an industry-standard serial bus for interconnecting telecommunications integrated circuits. for more information, see chapter 17, general circuit interface (gci). 16.5.5 software-related considerations n when using the tsas in transparent pcm highway mode, the first byte of data transferred must always contain a 1 as the first bit. if the first bit is a 0, the idle state (mark idle) previous to the actual data stream is corrupted, which could falsely indicate the start of actual data. this only applies when using transparent mode. 16.5.6 comparison to other devices the am186cc and am186ch microcontrollers are similar to the amd am79c30 in clock slave mode. 16.6 initialization on both external and internal reset, the following occurs: n all the tsa registers default to c0h, which disables the tsa channels (they must be configured by software before being enabled). n the multiplexed signals default as shown in table 16-1 on page 16-5. table 16-3 timing parameters per device (supported pcm codecs in gci mode) parameter 1 notes: 1. all loading is 150 pf. device time (in ns) 79c30 as master am186cc am79c02/ 03/031 mc14555 x tp305x tp307x clock period min: 487 max: 815 min: 974 max: 1630 min: 122 max: 7812 clock high pulse width min: 260 min: 260 min: 48 max: 3890 min: 50 min: 160 min: 80 clock low pulse width min: 260 min: 260 min: 48 max: 3890 min: 50 min: 160 min: 80 frame sync setup time min: 50 min: 50 min: 25 max: clk prd-50 min: 50 min: 50 min: 30 frame sync hold time min: 50 min: 260 (min pw) 2 2. one clock prior to frame sync is a full clock period, guaranteed to hold for a minimum pulse width low. min: 50 min: 50 min: 100 min: 30 data output delay max: 100 data movement occurs out- side the am186cc min: 3/30ns max: 80/150 min: 20 typ: 60 max: 140 min: 0 max: 140 max: 80 data output hold time min: 70 min: 5/30 max: 80/150 max: 80 data input setup time pw + 20 min: 25 min: 0 min: 50 min: 30 data input hold time 50 min: 5 min: 50 min: 50 min: 15 cc cc am186?cc/ch/cu microcontrollers users manual 17-1 chapter 17 general circuit interface (gci) note: only the am186cc microcontroller supports gci. 17.1 overview the general circuit interface (gci) is an interface specification developed jointly by alcatel, italtel, gpt and siemens. this specification (sometimes called iom-2) defines an industry- standard serial bus for interconnecting telecommunications integrated circuits. the standard covers linecard, nt1, and terminal architectures for integrated services digital network (isdn) applications. the am186cc microcontroller supports the terminal version of gci, which serves four main functions: n connection of voice/data modules to an osi layer 1, gci-scit (special circuit interface t) device (transceiver) n programming and control of devices that do not have a microprocessor interface (e.g., a coder-decoder (codec) or a u-interface transceiver) n interchip communications between devices on the bus (e.g., a codec to a speech encryption device) n connection of multiple data link controllers to the d channel, including access arbitration handled through the terminal interchip communication (tic) bus depending on the application, each hdlc can communicate to the external world with or without a tsa. each of the four hdlc channels can be programmed to select between raw dce and dedicated pcm highway external interfaces. the am 186cc microcontrollers hdlc channel a interfaces to the gci controller block, and allows multiplexed pcm highway and gci interfaces to the other three hdlc channels. see chapter 15, high-level data link control (hdlc) and chapter 16, hdlc external serial interface configuration (tsas) for more information. full documentation on gci/iom-2 is available in the amd iom-2 interface reference guide , order #12576. 17.2 block diagram figure 17-1 shows the block diagram for a single hdlc channel, including connections with the tsa and gci. cc general circuit interface (gci) 17-2 am186?cc/ch/cu microcontrollers users manual figure 17-1 hdlc, tsa, and gci block diagram (same as figure 15-2) transmit clock transmit data pcb registers loopback receiver transmitter pcb bus 32 x 8 fifo 16 x 8 fifo control/status interface control/status registers monitor time slot tic bus pad interface time mux clock mux data mux registers smartdma internal rtr tic bus control internal cts control control i/o out out receive data receive clock receive clk (a, b, c, d) transmit clk (a, b, c, d) receive data (a, b, c, d) transmit data (a, b, c, d) receive clk_a transmit clk_a receive data_a transmit data_a control i/o rxd rxc txc txd in in i/o i/o i/o smartdma bus pcb bus tsa gci hdlc control control/ time slot control channel channel controller controller controller status monitor control data tic bus control i/o cc cc general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-3 17.3 system design table 17-1 lists the hdlc/tsa/gci signals that are multiplexed with other am186cc microcontroller functions. pinstraps are sampled only at external reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. table 17-2 on page 17-3 shows an example application. figure 17-2 isdn ta gci-to-pcm conversion system application example table 17-1 hdlc/tsa/gci multiplexed signals (same as table 15-1) multiplexed signals function default signal ch external interface pios dce pcm gci uart a dce_rxd_a pcm_rxd_a gci_dd_a dce and pcm data input/ gci downstream pin dce_rxd_a dce_txd_a pcm_txd_a gci_du_a dce and pcm data output/ gci upstream pin dce_txd_a dce_rclk_a pcm_clk_a gci_dcl_a dce receive clock/pcm receive and transmit clock/gci receive and transmit clock dce_rclk_a dce_tclk_a pcm_fsc_a gci_fsc_a dce transmit clock/pcm frame sync clock/gci frame sync clock dce_tclk_a dce_cts_a pcm_tsc_a pio17 dce clear to send/pcm external buffer enable pio17 dce_rtr_a pio18 dce ready to receive pio18 isdn gci transceiver pcm codec gci_du_a gci_dd_a gci_fsc_a gci_dcl_a sbin sbout sfs sclk dxa dra fs pclk pcm_fsc_c pcm_clk_c am186cc controller cc general circuit interface (gci) 17-4 am186?cc/ch/cu microcontrollers users manual b dce_rxd_b pcm_rxd_b pio36 dce and pcm data input pin pio36 dce_txd_b pcm_txd_b pio37 dce and pcm data output pin pio37 dce_rclk_b pcm_clk_b pio40 dce receive clock/pcm receive and transmit clock pio40 dce_tclk_b pcm_fsc_b pio41 dce transmit clock/pcm frame sync clock pio41 dce_cts_b pcm_tsc_b pio38 dce clear to send/pcm external buffer enable pio38 dce_rtr_b pio39 dce ready to receive pio39 c dce_rxd_c pcm_rxd_c pio42 dce and pcm data input pin pio42 dce_txd_c pcm_txd_c pio43 dce and pcm data output pin pio43 dce_rclk_c pcm_clk_c pcm_clk_c pio22 dce receive clock/pcm receive and transmit clock input/gci-to-pcm conversion clock output pio22 dce_tclk_c pcm_fsc_c pcm_fsc_c pio23 dce transmit clock/pcm frame sync clock input/gci-to-pcm conversion frame sync output pio23 dce_cts_c pcm_tsc_c pio44 dce clear to send/pcm external buffer enable pio44 dce_rtr_c pio45 dce ready to receive pio45 d dce_rxd_d pcm_rxd_d rxd_u pio26 dce and pcm data input/ uart data receive pio26 dce_txd_d pcm_txd_d txd_u pio20 dce and pcm data output/ uart data transmit pio20 dce_rclk_d pcm_clk_d rtr_u pio25 dce receive clock/pcm receive and transmit clock input/uart ready-to-receive pio25 dce_tclk_d pcm_fsc_d cts_u pio24 dce transmit clock/pcm frame sync clock input/uart clear- to-send pio24 dce_cts_d pcm_tsc_d cts_hu pio46 dce clear to send/pcm external buffer enable/high- speed uart clear-to-send pio46 dce_rtr_d rtr_hu pio47 dce ready to receive/high- speed uart ready-to-receive pio47 table 17-1 hdlc/tsa/gci multiplexed signals (same as table 15-1) (continued) multiplexed signals function default signal ch external interface pios dce pcm gci uart cc cc cc general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-5 17.4 registers the registers listed in table 17-2 program the gci. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. 17.5 operation 17.5.1 usage note: before using gci, ensure multiplexed pins are configured to reflect the use of gci and not other functionality (see table 17-1 on page 17-3). 1. to enable the gci interface, software must set the mode field of the tsacon register to 10b. this is necessary whether or not tsa channel a is being used. 2. if transmitting using the gci, see transmitting data on page 17-6; if receiving, see receiving data on page 17-7. table 17-2 gci register summary offset register mnemonic register name description 2a0h gpcon gci peripheral control configures gci. 2a2h gistat gci interrupt status contains status. all bits can generate an interrupt if not masked off in gimsk. 2a4h gimsk gci interrupt mask mask register for gistat. when a mask bit is 0 (the reset value), the corresponding interrupt is masked off. 2a6h gtic gci tic bus address enables tic bus operation. 2a8h gictd gci intercommunication transmit data contains user-defined transmission data for gci ic channel 1 or 2. 2aah gicrd gci intercommunication receive data contains received data for either gci ic channel 1 or 2. 2ach gicrdp gci intercommunication receive data peek copy of gicrd register that does not change status when read. 2aeh gcitd0 gci command/indicate transmit data 0 contains user-defined transmission data for gci c/i0 channel. 2b0h gcird0 gci command/indicate receive data 0 contains received data for gci c/i0 channel. 2b2h gcird0p gci command/indicate receive data 0 peek copy of gcird0 register that does not change status when read. 2b4h gcitd1 gci command/indicate transmit data 1 contains user-defined transmission data for gci c/i1 channel. 2b6h gcird1 gci command/indicate receive data 1 contains received data for gci c/i1 channel. 2b8h gcird1p gci command/indicate receive data 1 peek copy of gcird1 register that does not change status when read. 2bah gmtd gci monitor transmit data contains user-defined transmission data for gci mon0 or mon1 channels. 2bch gmrd gci monitor receive data contains received data for gci mon0 or mon1 channels. 2beh gmrdp gci monitor receive data peek copy of gmrd register that does not change status when read. general circuit interface (gci) 17-6 am186?cc/ch/cu microcontrollers users manual 17.5.1.1 transmitting data 1. configure the hdlc channels and time slot assigners to transmit the data. for details, see chapter 15, high-level data link control (hdlc), and chapter 16, hdlc external serial interface configuration (tsas). 2. configure and activate the gci channels: a. if using the tic bus access procedure, set the ticen and ticad bits in the gtic register. for information about the tic bus access procedure, see tic bus support on page 17-16. b. if transmitting monitor channel data, set the applicable configuration options in the gpcon register (the mchen, mchsel, and brdis bits). c. if transmitting ic channel data, set the applicable configuration options in the gpcon register (the icsel and brdis bits). d. for ci/1 channel data, set the applicable configuration option in the gpcon register (the brdis bit). e. if the bus is in a deactivated state, activate the bus by setting the gciact bit in the gpcon register. for details, see gci bus deactivation/activation on page 17-9. 3. set the interrupts to be taken with the gimsk register. bits in this register enable interrupts based on interrupts set in the gistat register. corresponding bits must be set in both registers for the interrupt to be taken. if an interrupt is disabled in gimsk, the status can still be read. note that for each gcitd0 register write, if using the tic bus access procedure, the bar bit must be taken into consideration. 4. wait for the dclst bit in the gistat register to be set, indicating the data clock has been started by the master clock device. 5. if the bus was in a deactivated state, turn off the gci activation request by clearing the gciact bit in the gpcon register. 6. for monitor channel transmission, each transmit buffer available interrupt should write new data into the transmit register until all data has been transmitted. 7. for monitor channel transmission, set the meomrq bit in the gpcon register on the last byte transmitted. this bit forces the monitor channel transmitter to send an eom when all data is written. the outgoing mx bits and incoming mr bits held inactive for two or more frames indicates that the monitor channel is idle in the outgoing direction. at the start of transmission, program the gpcon register to select one of the two monitor channels. then load data into the gci monitor transmit data (gmtd) register, which causes the gci controller to present the first data byte to the bus and to perform an inactive-to- active transition of the outgoing mx bits. placing data on the bus also generates the monitor channel transmit buffer available interrupt, indicating that the next data byte may be written to the buffer. outgoing mx bits remain active, and the data is repeated until an inactive-to- active transition of the incoming mr bit is received. in subsequent transmissions, all the following bytes to be transmitted are presented to the bus coincident with an active-to-inactive transition of outgoing mx bits. the gci specification defines a general case in which the transmitter waits for an inactive-to-active transition of incoming mr bits, and a maximum speed case in which the transmitter achieves a higher transmission rate by anticipating the falling edge of incoming mr bits. after transmitting the last byte of data, indicated by the gmtd register being empty and the general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-7 meomrq bit being set, the gci controller deactivates the outgoing mx bits in response to incoming mr bits going inactive, and leaves them inactive. 17.5.1.2 receiving data 1. configure the hdlc channels and time slot assigners to receive the data. for details, see chapter 15, high-level data link control (hdlc), and chapter 16, hdlc external serial interface configuration (tsas). 2. configure the gci channels: a. if using the tic bus access procedure, set the ticen bits in the gtic register. for information about the tic bus access procedure, see tic bus support on page 17-16. b. if receiving monitor channel data, set the applicable configuration options in the gpcon register (the mchen, mchsel, and brdis bits). c. if receiving ic channel data, set the applicable configuration options in the gpcon register (the icsel and brdis bits). d. for ci/1 channel data, set the applicable configuration option in the gpcon register (the brdis bit). e. if the bus is in a deactivated state, activate the bus by setting the gciact bit in the gpcon register. for details, see gci bus deactivation/activation on page 17-9. 3. set the interrupts to be taken with the gimsk register. bits in this register enable interrupts based on interrupts set in the gistat register. if software disables an interrupt in gimsk, it can still read the interrupt status in the gistat register. 4. wait for the dclst bit in the gistat register to be set, indicating the data clock has been started by the master clock device. 5. if the bus was in a deactivated state, turn off the gci activation request by clearing the gciact bit in the gpcon register. 6. for monitor channel transmission, on the first data available interrupt, software must set the mcarv configuration bit to continue transmission. this bit holds off the remote transmitter until software has determined the first byte is valid (the first byte is usually a known address byte). if software fails to determine that the first byte is valid, then software should abort reception (i.e., this message is for some other downstream device). 7. for monitor channel transmission, the meomrd interrupt is set to indicate that an end- of-message (eom) has been received by the monitor channel. at the time the receiver sees the first byte, indicated by the inactive-to-active transition of incoming mx bits, outgoing mr bits are by definition inactive. the gci controller activates outgoing mr bits in response to the activation of incoming mx bits, loads the data byte on the bus into the monitor receive data register, and generates a monitor channel receive data available interrupt. outgoing mr bits remain active until the next byte is received or an eom is detected (incoming mx bits held inactive for two or more frames). in subsequent receives, the gci controller receives data into the buffer on each falling edge of incoming mx bits, and generates a monitor channel receive data available interrupt. note that the data was actually valid at the time the incoming mx bits became inactive, one frame before becoming active (the am186cc microcontroller performs a data integrity check to confirm stable data for two frames). outgoing mr bits are deactivated at the time data is read and reactivated one frame later. the receipt of an eom, which is incoming mx bits remaining inactive for two or more frames, terminates the reception of data. general circuit interface (gci) 17-8 am186?cc/ch/cu microcontrollers users manual an abort is a signal from the receiver to the remote transmitter indicating that data has been missed. the receiver sends an abort (indicated with the mtard bit in the gistat register) by holding mr bits inactive for two or more frames in response to mx bits going active. receiving an abort, indicated with the mrad bit of the gistat register, generates a transmitter interrupt. the remote transmitter is held off until the monitor receive data register is read, because mr bits are held active until the receive byte is read. the transmitter does not start the next transmission cycle until mr bits go inactive. 17.5.2 gci structure: channels and frames figure 17-3 illustrates the gci terminal mode frame structure. the am186cc microcontroller also provides a second interface used with the gci interface (discussed in gci-to-pcm converted pin interface on page 17-14). this second interface allows an external pcm codec to multiplex directly onto a gci terminal frame b channel. for more information, see the amd iom-2 interface reference guide , order #12576. figure 17-3 gci terminal mode frame structure 17.5.3 gci applications the am186cc microcontroller gci implementation: n targets the following external isdn transceivers in gci mode: C amd am79c30/am79c32 s C siemens peb2091 u C siemens peb2081 s/t C siemens peb2086 s C motorola mc145574 s/t C motorola mc145572 u C national tp3420 s/t n targets the following external codec: C amd am79c04 n with gci-to-pcm conversion, targets the following pcm external codecs (see table 16-3 on page 16-14): C amd am79c02/03 C amd am79c031 C motorola mc14555 b1 b2 mon0 dc/i0 mx mr ic1 ic2 mon1 c/i1 mx mr tic 8-bits 8-bits 8-bits 2-bits 2-bits 2-bits 8-bits 8-bits 8-bits 4-bits 8-bits 6-bits 8-bits 8-bits 8-bits gci subframe 0 gci subframe 1 gci subframe 2 fsc dd/ du general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-9 C national tp305x family C national tp307x family C at&t t75xx family C ti/intel 291x family n supports gci terminal mode n supports gci slave mode (i.e., a timing slave where the gci_fsc_a and gci_dcl_a signals are inputs) n supports interdevice communication via monitor and command/indicate channels n supports the tic bus, providing the capability of connecting more than one device to the d and c/i channels in the first subframe (via c/i0 and d-channel arbitration) n supports d-channel collision detection via the echo bits from the s-interface n is multiplexed with one fixed am186cc external raw dce interface n does not support: C gci linecard mode C gci master mode C tic bus a/b bit: an optional supplementary bit used for d-channel control: 1 indicates the d channel is available, 0 indicates the d channel is blocked C the following terminal mode signals (used for connecting non-gci components): C bcl: 1x-bit rate clock C sds1 and sds2: data strobes which identify the location of the b channels 17.5.4 gci bus 17.5.4.1 gci bus deactivation/activation the gci bus includes an activation/deactivation capability. either upstream components or downstream components on the bus can initiate activation and deactivation. figure 17-4 illustrates the activation/deactivation process. when deactivated, the upstream device holds all clock outputs low. the downstream device holds all the clock outputs low, and forces open drain data outputs to a high-impedance state (seen as a high on the system bus due to the external pullup resistor). the activation/deactivation procedure is a combination of software handshakes through the c/i channel, and hardware indications through the clock and data lines. the amd iom-2 interface reference guide , order #12576, describes both the hardware and the software protocols in detail. general circuit interface (gci) 17-10 am186?cc/ch/cu microcontrollers users manual figure 17-4 bus activation/deactivation 17.5.4.1.1 deactivation the upstream device typically initiates deactivation. when the am186cc microcontroller receives the deactivation request over the c/i channel, it must respond by sending the deactivation indication over the c/i channel. the upstream device then sends the deactivation confirmation command over the c/i channel. the am186cc microcontroller detects that the clock has stopped (defined as no clock pulse received for 650 ns) and forces itself to the deactivated state. in the deactivated state, the microcontroller forces both the du and dd signals to a high- impedance state, and monitors the dcl input (by use of the dclst bit in the gistat register) for any rising edge that would indicate an activation request from the upstream device. 17.5.4.1.2 activation either the upstream or the downstream device can initiate activation. for the am186cc microcontroller to activate the interface, software must set the activation bit (gciact) of the gpcon register. this forces the microcontroller to pull its data output pin (du) low, causing the upstream device to start the gci clocks. when the clocks are running, as indicated by the dclst status bit being set, the microcontroller must respond to the interrupt by loading the proper c/i command response into the c/i0 transmit register, then clearing the gciact bit. this releases the data output pin (du) from being held low and allows the microcontroller to complete the activation procedure by sending the proper commands over the c/i channel. the dcl clock remains active until the upstream device stops the clock. when activation originates from the upstream device, the dclst bit is set when the clocks become active (dcl going high). the microcontroller begins normal gci transmission/ clock (dcl) received from upstream; timing request interrupt generated deactivation activation downstream activation upstream clocks stopped by upstream device software clears activation bit software sets activation bit; du output forced low du output forced to z dd output forced to z time out (clocks off) (du = 0) (clocks off) (du = 0) (clocks on) idle (clocks off) (du = z) (dd = z) active (clocks on) (du = data) general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-11 reception as soon as dcl appears; no intervention from the controller is required. however, the microcontroller must respond to the interrupt and perform the normal c/i channel software handshakes before activation completes. 17.5.4.2 gci bus reversal in terminal mode, a device may be required to transmit both upstream and downstream, based on which gci channel is being transmitted at any one time. as a result, the actual data pins of the gci interface need to be both inputs and outputs, changing direction based on which channel is being transmitted at the time. 17.5.4.2.1 downstream versus upstream the following terms are used in gci: downstream direction: data is output on gci_dd_a by an upstream device and this data is a gci_du_a input to the downstream device. upstream direction: data is output on gci_du_a by a downstream device and this data is a gci_dd_a input to the upstream device. downstream device: generates gci_du_a and terminates gci_dd_a. upstream device: generates gci_dd_a and terminates gci_du_a. because pin reversal is supported, a device on the gci bus can be considered a downstream device, an upstream device, or both. figure 17-5 demonstrates the am186cc microcontroller as an gci subframe 0 downstream device (the transceiver, an upstream device, outputs data on gci_dd_a and the am186cc microcontroller, the downstream device, inputs data from gci_dd_a). figure 17-5 also demonstrates the am186cc microcontroller as a gci subframe 1 upstream device (the am186cc microcontroller, an upstream device, outputs data on gci_dd_a and a downstream device, such as an gci codec, inputs data from gci_dd_a). devices which do not support pin reversal are fixed to transmit and receive in one direction only. for example, a line transceiver is always an upstream device communicating solely with downstream devices (it transmits information on gci_dd_a to downstream devices, and receives information on gci_du_a from devices sending information upstream to this upstream transceiver). therefore, in this case, anything on the gci bus is always considered downstream from the upstream transceiver. note: in most documentation, where a reference point is not given, but upstream or downstream are mentioned, the default reference point is almost always the transceiver: that is, downstream (from the transceiver), upstream (to the transceiver), the upstream (transceiver) device, and so on. general circuit interface (gci) 17-12 am186?cc/ch/cu microcontrollers users manual figure 17-5 downstream versus upstream 17.5.4.2.2 bus reversal enabled versus disabled when bus reversal is enabled (see figure 17-6), the am186cc microcontroller is the clock slave (gci_fsc_a and gci_dcl_a are inputs) and control master (can communicate with other downstream devices through the mon1 and c/i1 channels). when bus reversal is disabled (see figure 17-7), the am186cc microcontroller is the clock slave (gci_fsc_a and gci_dcl_a are inputs) and control slave ( cannot communicate with other downstream devices). d and c/i0 channel arbitration are provided by the tic bus. (the tic bus has been split up into its individual bits for illustration.) figure 17-6 gci with bus reversal enabled gci_du_a gci_dd_a gci_fsc_a gci_dcl_a clock source gci_du_a gci_dd_a gci upstream device (control mas- ter and clock slave) am186cc transceiver am186cc codec example 1: am 186cc microcontroller downstream, transceiver upstream example 2: gci codec downstream, am 186cc microcontroller upstream controller controller gci downstream device (control slave and clock master) gci upstream device (control mas- ter and clock master) gci downstream device (control slave and clock slave) gci_fsc_a gci_dcl_a dd du downstream #1 downstream #2 dd dd du du dd du ic1,ic2,mon1,c/i1 b1,b2,d,mon0,c/i0,e(in),s/g(in), bac(out), tba2Ctba0(out) transceiver am186cc notes: e, s/g, bac, and tba2Ctba0 are bits on the tic bus. general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-13 figure 17-7 gci with bus reversal disabled 17.5.5 gci interface signals 17.5.5.1 four-pin interface the gci terminal mode interface consists of a four-pin subset of the seven-pin gci industry standard serial bus. the gci interface for the am186cc microcontroller uses the frame synchronization clock (gci_fsc_a), data clock (gci_dcl_a), data downstream (gci_dd_a), and data upstream (gci_du_a) signals. the definition of the gci external signals is dependent on the current bus state (activated/deactivated) and the mode of operation (bus reversal enabled/disabled), as described in table 17-3. table 17-3 gci signals signal signal function mode: reversal state: activated mode: reversal state: deactivated mode: no reversal state: activated mode: no reversal state: deactivated gci_fsc_a frame sync clock input input input input gci_dcl_a data clock input input input input gci_dd_a data down- stream input/ open drain output high impedance input high impedance gci_du_a data up- stream open drain output/input open drain output open drain output open drain output transceiver dd du downstream #1 downstream #2 dd dd du du dd du b1,b2,d,mon0,c/i0,ic1,ic2, mon1,c/i1,e(in),s/g(in), bac(out), tba2-0(out) am186cc notes: e, s/g, bac, and tba2Ctba0 are bits on the tic bus. general circuit interface (gci) 17-14 am186?cc/ch/cu microcontrollers users manual 17.5.5.2 gci-to-pcm converted pin interface the converted gci to pcm interface consists of two pins. this interface (external interface c on the am186cc microcontroller) uses the signals listed in table 17-4. for more information about frame sync and clock conversion, see chapter 16, hdlc external serial interface configuration (tsas). 17.5.6 operating frequencies gci_dcl_a is used to clock data on and off of the bus, and it operates at twice the data rate. the clock rate is 1.536 mhz (the data rate is 768 khz). gci_dcl_a is always generated by the upstream component. when the bus is deactivated, gci_dcl_a is held in a low state by the upstream device. gci_fsc_a is an 8-khz clock that indicates the start of a frame. gci_fsc_a is always generated by the upstream device, which is the layer 1 device in terminal applications. 17.5.7 gci channels the gci channels consist of three voice/data channels (b1, b2, and d), two monitor channels (mon0 and mon1), two command/indication channels (c/i0 and c/i1), two interchip communication channels (ic1 and ic2), and the tic bus. 17.5.7.1 gci hdlc channel steering all hdlc channel data steering is provided through proper tsa (time slot assigner) and mux initialization. while there is nothing to prevent an hdlc channel from accessing any set of contiguous bits within the gci frame, only accesses to the b, d, and ic channels are guaranteed. for more information about tsa configuration, see chapter 16, hdlc external serial interface configuration (tsas). 17.5.7.2 monitor channel operation the monitor channel is full duplex and operates on a pseudo-asynchronous basis, that is, while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the mx (monitor transmit) and mr (monitor receive) bits. for example, data is placed onto the monitor channel and the mx bit is activated. this data is transmitted repeatedly (once per 8-khz frame) until the transfer is acknowledged through the mr bit. thus, the data rate is not 8 kbyte per second. am186cc microcontroller monitor channel support is provided on a one-at-a-time basis (the mchsel bit in the gpcon register designates which monitor channel is selected). for a detailed description of the monitor channel handshake procedure, see the amd iom-2 interface reference guide , order #12576. 17.5.7.3 monitor channel collision detection for multidrop configurations, a collision resolution mechanism is implemented in the monitor channel transmitter that looks for the idle phase of the transmitted mx/mr bits and makes a per bit check on the transmitted monitor data. table 17-4 converted gci signals external signal function pcm_clk_a converted gci to pcm data clock pcm_fsc_a converted gci to pcm frame synchronization clock general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-15 to access the monitor channel through upstream monitor channel collision detection on the first byte and downstream device recognition on the first byte (these procedures are used in monitor channel multidrop configurations), use the following procedures. 17.5.7.3.1 upstream monitor channel data transmission the address of the monitor message contained in the first monitor byte transmitted determines the monitor channel access priority. the following hardware/software procedure is followed: 1. software configures the monitor channel for data transmission. 2. hardware waits for the idle phase before transmitting the first byte of monitor data. 3. during the first byte transmitted, a per bit check occurs on each transmitted monitor bit. if any bit mismatches, the transmitter immediately withdraws from the monitor channel by setting all remaining monitor bits to 1 (thus allowing another device with higher priority to gain control of the monitor channel), sets the monitor channel collision detection interrupt, and reverts back to waiting for the idle condition. note: the collision detection interrupt is set on any monitor data transmit bit mismatch (i.e., from the first byte transmitted to the last byte transmitted). therefore, if software wishes to differentiate how it services other byte collisions from first-byte collisions, it must maintain this knowledge itself. 17.5.7.3.2 downstream monitor channel data reception device recognition allows a downstream device to determine whether or not it is the intended target for an initiated monitor channel message sent by an upstream device (the address to be recognized is contained in the first byte of the monitor message). the following hardware/software procedure is followed: 1. hardware waits for the idle phase. 2. after detecting the idle phase, hardware waits for a valid first byte to be sent by an upstream device. 3. after receiving the first byte, hardware indicates to software, through a data-available interrupt, that the first byte has arrived. 4. software determines whether or not the microcontroller was the intended target. 5. if a valid address is recognized (from the first byte), software indicates to the receiver to continue with data reception by setting a valid address-compare bit. otherwise, software indicates to the receiver that it should not continue receiving data (through a software-abort bit). 17.5.7.4 c/i channel operation the c/i channel communicates real-time status information and maintenance commands. unlike the monitor channel, the am186cc microcontroller supports both c/i channels contained in gci subframe 0 and gci subframe 1 concurrently. software reads the received data from one of the c/i receive data (gcird0 or gcird1) registers. software writes c/i transmit data to one of the c/i transmit data (gcitd0 or gcitd1) registers. the gci controller monitors these two channels, and generates an interrupt any time the receive data changes and is stable for two frames (gcis standard data integrity check). data on the c/i channel is continuously transmitted in each frame until new data is to be sent. in this way, the c/i channel can be thought of as a set of static status lines that only change when the status changes. for a list of c/i codes (for gci subframe 0 only), and further c/i channel operation, refer to the amd iom-2 interface reference guide , order #12576. general circuit interface (gci) 17-16 am186?cc/ch/cu microcontrollers users manual 17.5.7.5 tic bus support the meaning of each bit within the tic bus is dependent on whether the am186cc microcontroller is transmitting or receiving on the tic bus. table 17-5 lists and describes the tic bus bits. in the downstream direction (from the transceiver), the tic bus on gci subframe 2 is used for d and c/i0 channel access control in s/t interface terminals. the tic bus downstream has the format shown in figure 17-8. figure 17-8 tic bus downstream format the availability of the s/t interface d-channel is indicated in bit 5 (stop/go bit) of the downstream tic bus. the am186cc microcontroller gci tic bus controller checks the stop/go bit to determine if it has access to the d-channel. if it does, it can start transmission of an hdlc frame. if the tic bus controller does not have access, it must halt the transmission. bits 7 and 6 are the d-channel echo bits from the s-interface (reflecting back the two d-channel bits of the current frame). the am186cc microcontroller gci tic bus controller compares the echo bits with the sent d-channel bits to determine if a collision has occurred. a d-channel collision is reported to an hdlc through an internal signal, originating from the gci tic bus controller, whose function is similar to an external cts deassertion (a mechanism that stops hdlc transmission). the am186cc microcontroller does not use the a/b bit. in the upstream direction (to the transceiver), the tic bus on gci channel 2 is used for the tic bus access procedure, enabling the connection of several layer 2 d-channel protocol controllers to the gci interface. the tic bus upstream has the format shown in figure 17-9. figure 17-9 tic bus upstream format table 17-5 tic bus bits bit name bit function bac (bus accessed) indicates to the other devices that the tic bus is being accessed. when 0, the bus is being accessed; when 1, it is free. this bit is driven to zero by the device that gets an address match on tba2Ctba0. tba2-0 (tic bus address) address bit used for arbitration of tic bus control. assumes open-drain bus such that the device with the lowest address has the highest priority. the lowest priority address, which is also the default, is 111. e-bits (echo bits) d-channel echo bits from the s-interface. s/g bit (stop/go) indicates availability of the s-interface d-channel. when 0, the d-channel is clear for transmission. when 1, d-channel transmission should be halted. bit number76543210 bit nameees/ga/b1111 bit number76543210 bit name 1 1 bac tba2 tba1 tba0 1 1 general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-17 an am186cc microcontroller access request can either be generated by software (microprocessor access to c/i channel 0) or by the hdlc controller itself (transmission of an hdlc framesignified internally by a signal, originating from the gci tic bus controller, whose function is similar to an external rts assertion). in the case of an access request, the gci tic bus controller checks the bac bit for the status bus free (bac = 1). if the bus is free, the gci tic bus controller starts transmitting its individual tic bus address (the source address indicated in figure 17-9 by the tba2Ctba0 bits). if an erroneous address is detected, the procedure is terminated immediately. if the complete tic bus address can be transmitted without error, the d-channel and c/i channel 0 are immediately occupied; during the subsequent frames the bus is identified as occupied (bac = 0) until the access request is withdrawn. after a successful bus access, the hdlc controller is set into a lower priority class, that is, a new bus access cannot be performed until the status bus free (bac = 1) is indicated in two successive frames. if none of the d-channel protocol controllers connected to the gci interface request access to the d and c/i channels, the tic bus address 7 is present. the device with this address therefore has access, by default, to the d and c/i channels. the following procedures gain access to the d-channel and c/i0 channel when tic bus support is enabled. 17.5.7.5.1 d-channel arbitration and collision detection (hardware control) hardware flow control for the gci bus accessed (bac) bit is added through rts /cts handshaking, and follows a procedure very similar to the c/i0 arbitration scheme discussed in c/i0 arbitration (software control) on page 17-18. 1. the hdlc controller makes a d-channel send request to the gci tic bus controller by asserting an internal rts signal (this signal remains asserted until the entire hdlc frame has been transmitted). 2. the gci tic bus controller checks if the bac bit is set to 1. if not, access is not currently allowedtransmission is postponed. only when bac = 1 does the gci tic bus controller continue with this access procedure. otherwise, it remains in this state. 3. when bac = 1, the gci tic bus controller, in the same frame, transmits the tic bus address (tba2Ctba0) on the open drain output. on the tic bus, binary 0s overwrite binary 1s. therefore, low tic bus addresses have higher priority. during tic bus reception, the s/g bit is monitored. note: s/g bit generation in the gci tic bus is sent downstream from an upstream transceiver. 4. after transmitting a tic bus address bit, the gci tic bus controller reads back the value to check whether its own address bit has been overwritten by a controller with higher priority. this procedure continues until all three address bits are sent and confirmed thus granting access to the gci tic bus. in the event a bit is overwritten by an external controller with higher priority, the gci tic bus controller withdraws immediately from the bus by setting all remaining tic bus address bits to 1. (this assures that the lowest address has priority. if the remaining bits are not immediately set to 1, addresses such as 101 and 011 would have equal priority.) if a bit is overwritten and an address mismatch occurs, the tic bus controller returns to step 2. 5. if access is granted (i.e., no address mismatch occurred) and the s/g bit is 0 (i.e., the s-interface is free for transmission), the gci tic bus controller asserts an internal cts signaling to the hdlc controller that it is now allowed to clock out data on its programmed time slot starting in the following gci frame. the bac bit, during this hdlc transmission, is set to 0 by the gci tic bus controller to block all remaining controllers. general circuit interface (gci) 17-18 am186?cc/ch/cu microcontrollers users manual in the case where the s/g bit is 1, only the d-channel data is prevented from being switched through the gci bus (i.e., the c/i0 channel could request access to this already established tic bus and transmit its information). the tic bus request remains unaffected (for example, if the microcontroller has earned the right to the gci tic bus it does not give up this bus and keeps bac and the tic address active while waiting for go). as soon as the s-interface d-channel is clear, signified by the s/g bit cleared (go), the controller commences with d-channel data transmission. note: when gci tic access is granted, bac = 0, regardless of s/g. at this point, both c/i0 and the hdlc controller have access to the gci tic bus (i.e., if c/i0 data needs to be transmitted it does not have to arbitrate for the gci tic bustic bus access has already been established). to relinquish the gci tic bus after a c/i0 or d-channel transmission, both the c/i0 request (a software request) and the hdlc controller request (a hardware request) must be deasserted. the hdlc controller cannot transmit back-to-back frames. therefore, if c/i0 keeps the tic bus open (the tic bus established by the hdlc controller), another hdlc transmission does not occur until after the c/i0 gives up the tic bus and bac = 1 in two successive frames (i.e., the tic bus cannot be accessed again for at least one gci frameregardless of whether the hdlc controller request or the c/i0 request established the tic bus). 6. after the completed transmission of an hdlc frame, signified by the hdlc controller deasserting the tic bus controllers rts , the hdlc controller is withdrawn from the tic bus (bac is set back to 1 in the following frame if a software tic bus request has not been made for c/i0 communication), and the hdlc controller is prevented from accessing the tic bus again for one gci frame (i.e., the controller was moved into a lower priority as mentioned earlier). this also applies even if a new hdlc frame is to be transmitted in immediate succession. this gives all connected devices an equal chance to access the tic bus. 7. if a collision occurs at any time during the transmission of a d-channel hdlc frame, the am186cc microcontroller immediately ceases transmission (collision is signified to the hdlc controller by deasserting cts while in frame), returns to the d-channel monitoring state (i.e., waits for another request to send and start over), and sends 1s over the d-channel. 17.5.7.5.2 c/i0 arbitration (software control) software controls the gci bus accessed (bac) bit through the bus access request (bar) bit of the gcitdx register following a procedure very similar to the d-channel arbitration scheme described above. this bit provides access to the c/i0 channel when tic bus support is enabled. software should set the bar bit whenever the microcontroller has c/i0 data available to transmit. 1. when bar = 1, the tic bus controller arbitrates access to the c/i0 channel. 2. the gci tic bus controller checks if the bac bit is set to 1. if not, access is not currently allowedtransmission is postponed. only when bac = 1 does the gci tic bus controller continue with this access procedure. otherwise, it remains in this state. 3. when bac = 1, the gci tic bus controller, in the same frame, transmits the tic bus address (tba2Ctba0) on the open drain output. on the tic bus, binary 0s overwrite binary 1s. thus, low tic bus addresses have higher priority. 4. after transmitting a tic bus address bit, the gci tic bus controller reads back the value to check whether its own address bit has been overwritten by a controller with higher priority. this procedure continues until all three address bits are sent and confirmed thus granting access to the gci tic bus. in the event a bit is overwritten by an external controller with higher priority, the gci tic bus controller withdraws immediately from the general circuit interface (gci) am186?cc/ch/cu microcontrollers users manual 17-19 bus by setting all remaining tic bus address bits to 1. (this assures that the lowest address has priority. if the remaining bits are not immediately set to 1, addresses such as 101 and 011 would have equal priority.) if a bit is overwritten and an address mismatch occurs, the tic bus controller returns to step 2. 5. if access was granted, the c/i0 channel is in possession of the gci tic bus, and c/i0 communication can begin in the following gci frame. note: when gci tic access is granted, bac = 0regardless of s/g. at this point, both c/i0 and the hdlc controller have access to the gci tic bus (i.e., if the hdlc controller needs to transmit d-channel data, it does not have to arbitrate for the gci tic bustic bus access has already been established). the hdlc controller does not have to arbitrate for the gci tic bus, but it must wait for an asserted s/g from the transceiver before it receives its internal cts and can transmit, as stated in the previous section. to relinquish the gci tic bus after a c/i0 or d-channel transmission, both the c/i0 request (a software request) and the hdlc controller request (a hardware request) must be deasserted. when the software request bit has been cleared (ending c/i0 transmission), the c/i0 channel is not allowed back onto the same established tic bus should it remain open for a hdlc transmission. when the tic bus is given up by the hdlc controller, neither the d-channel nor the c/i0 channel is allowed access to the tic bus again for at least one gci frame. 6. after the completion of c/i0 data, software should remove its request by clearing its request bit. when done, the c/i0 channel control is withdrawn from the tic bus (bac is set back to 1 in the following frame as long as the hdlc controller has no d-channel communication in progress) and the c/i0 channel is prevented from accessing the tic bus again for one gci frame (i.e., the channel is moved into a lower priority as mentioned earlier in this chapter). this gives all connected devices an equal chance to access the tic bus. 17.5.7.6 ic channel operation the two ic channels have access to a single interrupt-driven microprocessor transmit/receive buffer. a register bit determines which channel gets access to this buffer. because the data output is open-drain, the unused ic channel and all high bits of the chosen ic channel are placed in a high-impedance state (unless driven by an hdlc channel through a time slot assigner). 17.5.8 interrupts the gci controller can generate the following maskable interrupts (sharing one direct processor interrupt line) using the gistat and gimsk registers. n ic buffer available or buffer empty: indicates that a byte of data has been received on the ic channel, and that a new ic byte can be loaded for transmission. n gci timing request: response to gci_dcl_a starting (going high) from the deactivated state. n change in c/i1 channel status: indicates that the contents on the receive side of c/i channel 1 have changed since the c/i receive data register was last read. n change in c/i0 channel status: indicates that the contents on the receive side of c/i channel 0 have changed since the c/i receive data register was last read. n monitor channel receive abort detected: indicates an implied transmitter abort due to out-of-sequence transmit handshake bits or handshake bit transmission errors. n monitor channel collision detected: indicates that a collision has occurred on the monitor channel during the transmission of a monitor byte. general circuit interface (gci) 17-20 am186?cc/ch/cu microcontrollers users manual n monitor channel transmit abort request received: indicates that an abort request has been received on the monitor channel. this indicates that the receiver on the other end of the monitor channel has failed to receive the transmitted data correctly and is requesting that the current transmission be discontinued and the data transmission be repeated through software. n monitor channel end-of-message received: indicates that an eom has been received on the monitor channel. this indicates that the message currently being received has concluded. n monitor channel transmit buffer available: indicates that a new byte of data can be loaded into the monitor transmit data register. n monitor channel receive data available: indicates that a byte of data has been received on the monitor channel and is available in the monitor receive data register. 17.5.9 software-related considerations to enable the gci interface, software must set the mode bit field to 10b in the tsa channel a configuration (tsacon) register. this is necessary regardless of whether tsa channel a is being used. 17.5.10 comparison to other devices the am 186cc microcontrollers gci interface is similar to the amd am79c30 in clock slave mode. 17.6 initialization on external and internal reset, the following occurs: n the tsas default to non-gci mode. n the gci signals default to alternate functionality as shown in table 17-1 on page 17-3. n the exsync bit of the syscon register is cleared, making the hdlc channel c interface available for raw dce or pcm highway operation. n the mode field of the tsxcon register is cleared, specifying raw dce operation. n the gciden bit of the hxtcon1 register is cleared, disabling gci d-channel control of the hdlc channel. n the mchen bit of the gpcon register is cleared, disabling both monitor channels. n the mchsel bit of the gpcon register is cleared, selecting monitor channel 1. n the icsel bit of the gpcon register is cleared, selecting ic channel 1. n the brdis bit of the gpcon register is cleared, enabling bus reversal. n the mxba bit of the gistat register is set, indicating that a new byte of data can be loaded into the gmtd register. n all gci interrupts enables are cleared to 0 in the gimsk register, masking the interrupts. n the ticen and echoen bits are cleared to 0 in the gtic register, disabling tic bus access and d-channel echo compares, respectively. am186?cc/ch/cu microcontrollers users manual 18-1 chapter 18 universal serial bus (usb) note: only the am186cc and am186cu microcontrollers support usb. 18.1 overview the universal serial bus (usb) is an industry-standard bus architecture for computer peripheral attachment. the usb provides a single interface for easy, plug-and-play, hot- plug attachment of peripherals such as a keyboard, mouse, speakers, printers, scanners, and communication devices. the usb allows simultaneous use of many different peripherals with a combined transfer rate of up to 12 mbit/s. both the am186cc and am186cu microcontrollers include a highly flexible integrated usb peripheral controller that designers can use to implement a variety of microcontroller-based usb peripheral devices for telephony, audio, or other high-end applications. these microcontrollers can be used in self-powered usb peripherals that use the full-speed signaling rate of 12 mbit/s. they do not support the usb low-speed rate (1.5 mbit/s). an integrated usb transceiver is provided to minimize system device count and cost, but an external transceiver can be used instead, if required. the usb peripheral controllers features meet or exceed all of the usb device class resource requirements defined by the usb specification, version 1.0 . this chapter refers to this version of the usb specification throughout. consult the usb specification for details about overall usb system design. (at the time of this writing, the current usb specification and related information can be obtained on the web at www.usb.org .) the usb controller does not support usb host or hub functions. however, the am186cc and am186cu microcontrollers can be used to implement usb peripheral functions in a device that also contains separate usb hub circuitry. the integrated usb peripheral controller provides a very efficient and easy-to-use interface, so that device software (or software) does not incur the overhead of managing low-level usb protocol requirements. each of the controllers data endpoints is highly programmable and flexible, allowing the device to adapt to any usb host request that is made during the device configuration process. because of the flexibility of the usb peripheral controllers endpoints, a design can allow its descriptors to be updated on-the-fly by the hosts device driver, if necessary. the usb peripheral controller hardware implements a number of usb standard commands directly; the rest can be implemented in device software. in addition, the usb peripheral controller provides a high degree of flexibility to help designers accommodate vendor- or device-class-specific commands, as well as any new features that might be added in future usb specifications. the usb peripheral controller includes specialized hardware to support isochronous data transfers. using the microcontrollers dma features, isochronous transfers from an off-chip peripheral can be automatically synchronized to the usb data rate with little or no cpu overhead. cu cc universal serial bus (usb) 18-2 am186?cc/ch/cu microcontrollers users manual the am186cc microcontroller also supports isochronous transfers from one of the integrated hdlc channels. the usb peripheral controller also includes robust error detection and management features so the device software can manage transfers in any number of ways as required by the application. the usb suspend/resume, reset, and remote wake-up features are also supported. 18.2 block diagram figure 18-1 shows the block diagram for the usb peripheral controller. figure 18-1 usb interface block diagram 18.3 system design the following sections describe pin multiplexing and feature trade-offs to consider when designing peripherals that use the usb peripheral controller. 18.3.1 signal trade-offs table 18-1 lists the usb interface signals (including signals internal to the microcontroller) that are multiplexed with other microcontroller functions. pinstraps are sampled only at reset and do not affect the pins other functions, so they are not shown in this table. other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin. cc general- purpose dma usbd+ usbdC external transceiver interface control registers cpu, memory interface, and other peripheral devices usb controller usb transceiver am186cc/cu microcontroller fifo buffers usbx1 usbx2 hdlc a pcm gci usbsci/ usbsof cc smartdma channel universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-3 . 18.3.1.1 usb transceiver interface by default, the usb peripheral controller utilizes an integrated usb transceiver to directly drive and receive data on the usbd+ and usbdC differential physical interface signals. this transceiver allows a usb peripheral device to be designed with the am186cc or am186cu microcontroller without requiring the additional board space needed by a discrete transceiver device. the usb device terminator requirement is not integrated, so the designer should add a single 1.5 k- w pullup resistor on the usbd+ signal to indicate this is a full-speed device. the usb specification requires a driver impedance between 29 w and 44 w on the usbd+ and usbdC signals. the cmos drivers used have a much lower impedance, so matching resistors must be placed in series on the usbd+ and usbdC signals as shown in figure 18-2 on page 18-4 and figure 18-3 on page 18-5. 18.3.1.2 programmable connect and disconnect because the microcontroller is meant to be in a self-powered application, there are a few issues to resolve to meet usb specifications. for a full-speed device, the usb specification requires a 1.5 k- w device terminator to a 3.0-v to 3.6-v voltage source on usbd+, derived from or controlled by the power supplied by the usb cable (v usb ), that does not supply current when v usb is unpowered or removed. in a self-powered usb application, the usb host/hub also cannot supply current to the usb device when the device is unpowered. to help meet these criteria, the microcontroller is programmable to disable and three-state the internal transceiver differential outputs. the other requirement is to disable the external table 18-1 usb multiplexed signals signal function multiplexed signal(s) default signal internal usb transceiver i/o pins usbd+ internal usb transceiver differential input/output udpls usbd+ usbdC internal usb transceiver differential input/output udmns usbdC external usb transceiver i/o pins udmns status input from external transceiver usbdC usbdC udpls status input from external transceiver usbd+ usbd+ utxdmns output to the external transceiver differential driver rsvrd_102 rsvrd_102 utxdpls output to the external transceiver differential driver rsvrd_101 rsvrd_101 uxvoe external transceiver transmit output enable rsvrd_103 rsvrd_103 uxvrcv receive input from external transceiver rsvrd_104 rsvrd_104 usb clock inputs usbsci usb sample clock input uclk usbsof pio21 pio21 usbsof usb start-of-frame synchronization output uclk usbsci pio21 pio21 usbx1 usb peripheral controller crystal input usbx1 usbx2 usb peripheral controller crystal output usbx2 universal serial bus (usb) 18-4 am186?cc/ch/cu microcontrollers users manual 1.5 k- w pull up on usbd+ when v usb is removed. the following system design issues should be resolved to provide a robust self-powered usb device application: on connect: n monitor v usb to identify a powered usb host/hub. n enable the 1.5 k- w pullup on usbd+ to signal a connect condition to the host/hub. on disconnect: n monitor v usb to identify power being removed from the usb host/hub. n three-state usbd+/usbdC outputs. n remove power from 1.5 k- w pull up. on both connect and disconnect: n isolate v usb from the usb device when the device is unpowered. figure 18-2 illustrates a circuit diagram of an example application using the internal transceiver. figure 18-3 illustrates a circuit diagram of an example application using the external transceiver. figure 18-2 usb with internal transceiver am186cc/cu microcontroller dg s d s g 1.5 k- w pio_usb_detect pio_usb_vcc usbdC [udmns] usbd+ [udpls] v usb usbdC usbd+ gnd 1 2 3 4 usb type b r1 r2 note: the usb specification requires a driver impedance between 29 w and 44 w on the usbd+ and usbdC signals. for information about driver characteristics and selecting a series resistor value, see the data sheets for the am186cc and am186cu microcontrollers. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-5 figure 18-3 usb with external transceiver if necessary, to enable interface signals for an external transceiver, disable the integrated usb transceiver by asserting the usbxcvr pinstrap at reset (power-on or assertion of res ). table 18-1 on page 18-3 lists all usb signals, plus information about multiplexed functions. note: before using either the internal usb transceiver or the external usb transceiver interface, software must set the pup_xcver bit in the usb device miscellaneous functions (usbmfr) register to power up the usb transceiver and enable the transceiver interface. 18.3.1.3 usb clock source the usb peripheral controller hardware requires a 48-mhz clock input for proper operation. the usb peripheral controller can be driven directly from the primary system clock if the primary system clock is operating at 48 mhz. otherwise, use a dedicated usb clock source so that the primary microcontroller system clock and the usb clock are independent of each other. when the dedicated usb clock source is used, the only requirement is that the pio_usb_detect pio_usb_vcc dg s d s g usb type b v usb usbdC usbd+ gnd 1 2 3 4 utxdmns[rsvrd_102] utxdpls[rsvrd_101] uxvoe [rsvrd_103] uxvrcv[rsvrd_104] udmns[usbdC] udpls[usbd+] 1.5 k- w r1 r2 note: the usb specification requires a driver impedance between 29 w and 44 w on the usbd+ and usbdC signals. for information about driver characteristics and selecting a series resistor value, see the documentation for the external transceiver. am186cc/cu microcontroller universal serial bus (usb) 18-6 am186?cc/ch/cu microcontrollers users manual primary system clock must be a minimum of 24 mhz when using the usb peripheral controller . to select the dedicated usb clock source, assert either the usbsel2 or usbsel1 pinstrap during reset (power-on or assertion of res ). these pinstraps select either 4x or 2x pll operation, allowing the use of a 12-mhz or 24-mhz crystal, respectively, as the usb clock input on pins usbx1 and usbx2. table 18-2 lists the permutations of the usb pll mode pinstraps. 18.3.1.4 isochronous synchronization signals the usbsci signal input and usbsof signal output provide for isochronous transfer synchronization, which is described on page 18-23. these signals are multiplexed on the same pin with the uart external clock input signal (uclk). enabling the usbsof signal output (by setting the esof_en bit in the isochronous synchronization control (isctl) register) overrides the usbsci signal input if that signal is also selected (through the sam_clk_sel field in the isctl register.) do not enable the usbsof signal output at the same time as the uart external clock input (uclk). the uclk signal is enabled by the xtrn bit in the high-speed serial port control 1 (hspcon1) or serial port control 1 (spcon1) registers. the usbsci and uclk signal inputs can be enabled at the same time, but it is unlikely that the same signal source can be used as an input for both of these functions. 18.3.2 dma trade-offs the microcontroller contains two different kinds of dma channels, general-purpose dma and smartdma channels. the usb data endpoints can use either kind. choosing which type of dma channel to use, if any, involves the following system trade-offs: n the integrated hdlc controllers in the am186cc microcontroller can use only the smartdma channel. consequently, if all four hdlc controllers are to be used with dma (for high-bandwidth hdlc connections), then the usb can use only general-purpose dma or no dma. n other integrated peripherals such as the uarts and the external dma request lines can use only the general-purpose dma channels. n for usb bulk endpoints, smartdma channels have advantages over general-purpose dma channels that can result in higher performance and lower software overhead, especially when each transaction is relatively small. when most transactions are relatively large, general-purpose dmas may have a small performance advantage over smartdma channels. n for usb isochronous endpoints with true streaming data, general-purpose dmas are slightly easier to use than smartdma channels. table 18-2 usb pll mode pinstraps {usbsel1 } {usbsel2 } usb pll mode 1 1 use cpu clock, usb pll disabled (default) 0 1 4x, usb pll enabled 1 0 2x, usb pll enabled 00reserved cc universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-7 n each usb data endpoint can only be connected to a single specific smartdma channel, but can be connected to any general-purpose dma channel. because smartdma channels are directional (either transmit or receive), a general-purpose dma channel must be used if more than 2 in data endpoints or more than 2 out data endpoints are desired. for more about dma and other i/o options, see handling usb data on page 18-18. 18.4 registers the registers listed in table 18-3 program the usb peripheral controller. there are four general configuration registers, six miscellaneous control and status registers, ten registers for the dedicated control and interrupt endpoints, and eight registers each for the four data endpoints. appendix a summarizes the bits in all the registers. for a complete description of all the peripheral registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. table 18-3 usb register summary offset register mnemonic register name description usb general configuration registers 1e0h uistat1 usb interrupt status 1 common status register for interrupt-capable status bits of each usb endpoint. 1e2h uimask1 usb interrupt mask 1 enables or disables interrupts generated by uistat1 bits. 1e4h uistat2 usb interrupt status 2 shows status of usb and controller features. 1e6h uimask2 usb interrupt mask 2 enables or disables interrupts generated by uistat2 status bits. usb miscellaneous registers 1e8h usbmfr usb device miscellaneous functions provides internal usb transceiver power and disable control; usb suspend status; usb soft reset control; usb self-powered device attribute; and remote wake-up control/status. 1eah rtfmcnt real time frame monitor count used to estimate progress of the current host frame. 1ech tstmp time stamp contains the current frame number. 1eeh tstmpm time stamp match match register for time stamp bit in uistat2. 1f0h isctl isochronous synchronization control used to control external frame synchronization (usbsof signal enable), auto-rate bytes per sample, usb sample source clock; and fpmcnt bit latch count rate. 1f2h fpmcnt frame position monitor count used during isochronous in transfers to compare the source data rate (usbsci signal) to the usb hosts data rate. the hosts sof rate or data rate can then be adjusted accordingly. in the am186cc microcontroller, the hdlc a/pcm/gci source data rate can also be compared to the usb hosts data rate. cc ch universal serial bus (usb) 18-8 am186?cc/ch/cu microcontrollers users manual usb control endpoint registers 200h cntctl control endpoint control/status contains control and status bits for the control endpoint (endpoint 0). 202h cntsiz control endpoint receive packet size shows the size of the packet present in the control endpoints fifo. 206h cntdat control endpoint data port used to read from or write to the control endpoints fifo. the fifo address pointer is advanced on each access. 208h cntrpk control endpoint receive data port peek used to read the current value in the control endpoints fifo without advancing the fifo pointer. 20ah cntdef1 control endpoint definition 1 shows the control endpoints definition: endpoint number, configuration, interface, alternate setting, direction, and type. these parameters are fixed for the control endpoint. 20ch cntdef2 control endpoint definition 2 shows the control endpoints fifo size and maximum packet size. these parameters are fixed for the control endpoint. usb interrupt endpoint registers 210h iepctl interrupt endpoint control/status contains control and status bits for the interrupt endpoint. 216h iepdat interrupt endpoint data port used to write to the interrupt endpoints fifo. the fifo address pointer is advanced on each access. 21ah iepdef1 interrupt endpoint definition 1 used to set the interrupt endpoints definition: endpoint number, configuration, interface, alternate setting. the interrupt endpoints direction (in) and type (interrupt) are fixed. 21ch iepdef2 interrupt endpoint definition 2 used to set the interrupt endpoints fifo size (fixed for the interrupt endpoint) and maximum packet size. usb data endpoint a registers 220h aepctl a endpoint control/status contains control, status, and error bits for the endpoint. 222h aepsiz a endpoint received packet size shows the size of the packet present in the endpoints fifo. 224h aepbufs a endpoint buffer status shows the number of bytes present in the endpoints fifo. 226h aepdat a endpoint data port used to read from or write to the endpoints fifo. the fifo address pointer is advanced on each access. 228h arcvpk a endpoint receive data port peek used to read the current value in the endpoints fifo without advancing the fifo pointer. 22ah aepdef1 a endpoint definition 1 used to set the endpoints definition: endpoint number, configuration, interface, alternate setting, direction, and type. table 18-3 usb register summary (continued) offset register mnemonic register name description universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-9 22ch aepdef2 a endpoint definition 2 used to set the endpoints fifo size and maximum packet size. 22eh aepdef3 a endpoint definition 3 used to set auto-rate enable, status interrupt mask, transfer mode, and stop mask. usb data endpoint b registers 230h bepctl b endpoint control/status behaves the same as the endpoint a registers, but for endpoint b. 232h bepsiz b endpoint received packet size 234h bepbufs b endpoint buffer status 236h bepdat b endpoint data port 238h brcvpk b endpoint receive data port peek 23ah bepdef1 b endpoint definition 1 23ch bepdef2 b endpoint definition 2 23eh bepdef3 b endpoint definition 3 usb data endpoint c registers 240h cepctl c endpoint control/status behaves the same as the endpoint a registers, but for endpoint c, except that endpoint c and d have two additional fifo size options: 32 and 64 bytes. 242h cepsiz c endpoint received packet size 244h cepbufs c endpoint buffer status 246h cepdat c endpoint data port 248h crcvpk c endpoint receive data port peek 24ah cepdef1 c endpoint definition 1 24ch cepdef2 c endpoint definition 2 24eh cepdef3 c endpoint definition 3 usb data endpoint d registers 250h depctl d endpoint control/status behaves the same as the endpoint a registers, but for endpoint d, except that endpoint c and d have two additional fifo size options: 32 and 64 bytes. 252h depsiz d endpoint received packet size 254h depbufs d endpoint buffer status 256h depdat d endpoint data port 258h drcvpk d endpoint receive data port peek 25ah depdef1 d endpoint definition 1 25ch depdef2 d endpoint definition 2 25eh depdef3 d endpoint definition 3 table 18-3 usb register summary (continued) offset register mnemonic register name description universal serial bus (usb) 18-10 am186?cc/ch/cu microcontrollers users manual 18.5 operation the am186cc and am186cu microcontrollers act as usb peripheral devices. the usb is a half-duplex, master/slave, polled bus. in other words, the microcontroller only transmits on the usb in response to a request from the usb host, usually a personal computer. there can be only one transmitter on the usb at a time. when the usb host addresses a peripheral, it also addresses a particular endpoint on that device. each endpoint is configured with a logical number that the usb host uses to address that endpoint. no two endpoints can be configured with the same logical number. the endpoint responds to the hosts requests, sending or receiving device data. in usb nomenclature, data flowing from the host travels in the out direction, and data flowing to the host travels in the in direction. because the am186cc or am186cu microcontroller resides in a usb peripheral, its out endpoints receive data, and its in endpoints transmit data. each endpoint is supported by a first-in-first-out buffer (fifo). the fifo is a temporary storage location for the data that is passed between the microcontrollers cpu or memory bus and the integrated usb peripheral controller. the microcontroller supports six endpoints: n one dedicated control endpoint (endpoint 0) n one dedicated interrupt endpoint n four fully programmable data endpoints (named aCd) the following sections describe the usb endpoints and explain how to use them. 18.5.1 usage this section briefly lists the tasks that software must perform to program the usb peripheral controller for various applications. the following programming tasks do not cover all possibilities. they are intended to provide a basic understanding of usb register usage. the user should program the registers appropriately for each specific application. many of the subjects mentioned in the following lists are discussed more thoroughly elsewhere in this chapter. 18.5.1.1 general usb peripheral controller programming issues n always power up the transceiver (internal or external) by setting the pup_xcvr bit in the usb device miscellaneous functions (usbmfr) register. n always configure an endpoints definition registers before enabling the endpoint. changing the endpoint register values while the endpoint is enabled could result in unpredictable behavior. n when using usb status bits as interrupt sources, be sure to program the interrupt channel 2 control (ch2con) register to enable the channel and select its internal source (usb). n refer to the am186?cc/ch/cu microcontrollers register set manual , order #21916 for register default values and details about using each register field. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-11 18.5.1.2 programming the control endpoint the host uses the usb peripheral controllers dedicated control endpoint for detection and control of the device. the endpoint contains an 8-byte fifo for storage of commands, command data (for host command writes), and responses (for host command reads). the maximum packet size of the control endpoint is always eight bytes, the physical size of the fifo. the control endpoints number is fixed at 0. all usb devices must have a control endpoint with endpoint number 0. the usb host uses this endpoint to initialize and control the device. endpoint 0 gives the host access to the devices configuration information (device descriptors) and overall status. all of the usb standard and vendor- or device-class-specific commands are directed to this endpoint. see command handling on page 18-26. the following registers configure the control endpoint: n control endpoint definition 1 (cntdef1): all fields in this register are read only. they can be read to determine endpoint attributes. n control endpoint definition 2 (cntdef2): all fields in this register are read only. they can be read to determine endpoint attributes. n control endpoint control/status (cntctl): C the endpoint enable bit (ep_en) enables or disables the endpoint. device software can enable the endpoint in the stalled state by clearing the ep_not_stalled bit while the ep_en bit is being set. the hardware, however, sets the ep_not_stalled bit upon reception of a setup packet from the host. C device software can be interrupted by two sources: the act_req bit or the new_command bit. to enable these bits as interrupt sources, set the cnt_ep_act and cnt_ep_new bits in the usb interrupt mask 1 (uimask1) register. on reset, hardware owns the fifo (indicated by the cleared act_req bit). after hardware fills the fifo, it sets the act_req bit to transfer ownership of the fifo to software. the first time software owns the fifo, it clears the new_command bit and proceeds with writing data to or reading data from the fifo. software can use the control endpoint receive packet size (cntsiz) register to determine the number of valid data bytes present in the endpoint fifo. after software has completed its tasks, it hands the fifo back to the hardware by clearing the act_req bit. at the end of data (the last time software puts data in the fifo), software also clears the command_busy bit. hardware then sets the act_req bit once for the last packet, and then again for the end of command. for more information, see the am186?cc/ ch/cu microcontrollers register set manual , order #21916. 18.5.1.3 programming the interrupt endpoint because usb is polled, this is not an interrupt in the traditional sense. when the device wishes to interrupt the host, it returns data when the interrupt endpoint is polled. the usb peripheral controllers dedicated interrupt endpoint contains a 16-byte fifo, which software loads with the data to return on the next poll from the host. the maximum packet size can be set to eight or 16 bytes. for more information, see interrupt endpoint programming on page 18-29. universal serial bus (usb) 18-12 am186?cc/ch/cu microcontrollers users manual the host polls the interrupt endpoint once every 1 to 255 ms. device software requests a poll rate when it sets up the endpoints descriptor data structure, which the host obtains by issuing a get_descriptor command during device configuration. note that the interrupt endpoint can only be used in non-dma mode. the following registers are used to configure the interrupt endpoint in response to commands received from the usb host: n interrupt endpoint definition 1 (iepdef1): C based on the set_configuration command, the device software should write the ep_cfg field in the iepdef1 register. C based on the set_interface command, the device software should write the ep_int and ep_aset fields in the iepdef1 register. C based on the endpoint descriptor associated with the alternate setting, the device software should write the ep_num field in the iepdef1 register. n interrupt endpoint definition 2 (iepdef2): endpoint maximum packet value can be programmed to a value of 8 or 16. n interrupt endpoint control/status (iepctl): C the endpoint enable bit (ep_en) enables or disables the endpoint. C initial control of the data fifo is assigned to software. device software can therefore write to the endpoint fifo (iepdat). after writing to the fifo, the software should clear the act_req bit, thereby giving control back to the usb endpoint hardware and allowing it to transmit the written data. C hardware sets the act_req bit after the endpoint has successfully sent a data packet to the host and the packet has been acknowledged. to enable the act_req bit as an interrupt source, set the int_ep_act bit in the uimask1 register. C there is a feature that allows the device software to update stale data if it has not been transmitted. this is done by clearing the not_flush bit, which causes the hardware to revert control to the device software by setting the act_req bit. note that the act_req bit is set only if there is no active data transfer from this endpoint to the host. device software can verify if the act_req bit is set and if it is, can update stale data by writing to the fifo (iepdat). 18.5.1.4 programming data endpoints the usb peripheral controller provides four data endpoints.two have 16-byte fifos, and the other two have 64-byte fifos. each data endpoint is individually programmable as to direction (in or out relative to the host), transfer type (bulk, isochronous, or interrupt), and maximum packet size. the maximum packet size set for these endpoints can be greater than the fifos physical size if using a general-purpose dma or smartdma channel. (note that the endpoints have differences in how they interface to the smartdma channels.) legal maximum packet sizes are any power of 2 between 8 and 64 for data endpoints configured for bulk transfers, and any integer up to 1023 for data endpoints configured for isochronous transfers. the four endpoints are named a, b, c, and d. where the following description applies to any of them, an x is used in the register name in place of the endpoint name. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-13 the following registers configure a data endpoint in response to commands received from the usb host. for details on any of these registers, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. n endpoint definition 1 (xepdef1): C based on the set_configuration command, the device software should write the ep_cfg field in the xepdef1 register. C based on the set_interface command, the device software should write the ep_int and ep_aset fields in the xepdef1 register. C the endpoint number should be configured through the ep_num field in the xepdef1 register. C endpoint direction and endpoint type should be configured through the ep_dir and ep_type fields, respectively. n endpoint definition 2 (xepdef2): fifo size and endpoint maximum packet value fields can be programmed. the values depend on the endpoint type selection. (endpoint a and b fifos can be 8 or 16 bytes. endpoint c and d fifos can be 8, 16, 32, or 64 bytes.) n endpoint definition 3 (xepdef3): C based on application requirements, the appropriate interrupt mask and stop mask fields are programmable. C the mode field can configure the endpoint. this determines how the endpoint interfaces with system memory or another peripheral's data port. C to enable the auto rate feature, use the auto_rate_en field. note that this feature only applies to an endpoint that is configured as an isochronous in endpoint and interfaces with a dma mode. this feature requires additional programming in the isochronous synchronization control (isctl) register. for more information, see isochronous transfer features on page 18-24. n endpoint received packet size (xepsiz): this is a status register that provides information on the size of the received packet (in bytes) when the endpoint is configured for the out direction. n endpoint buffer status (xepbufs): this is a status register that provides information on the number of bytes, if any, is in the endpoint fifo. n endpoint data port (xepdat): device software or the dma controller uses this register to read/write to the endpoint fifo. a valid access to this register increments the address pointer. n endpoint receive data port peek (xrcvpk): debug or emulator software uses this register to read the endpoint data fifo without advancing the address pointer. it is only applicable for the out direction. universal serial bus (usb) 18-14 am186?cc/ch/cu microcontrollers users manual n endpoint control/status (xepctl): this register controls various aspects of the data endpoint. because the data endpoint is flexible in terms of the endpoint type, direction, and mode, besides other programmable features, use of this register is discussed in the following specific application scenarios. 18.5.1.4.1 endpoint a configured as bulk out, non-dma mode 1. program the endpoint a registers: C set ep_type = 10b (bulk) and ep_dir = 1 (out) in the aepdef1 register. C set mode = 000b (non-dma) in the aepdef3 register. C if interrupts are to be used, set the appropriate bits in the uimask1 or uimask2 register. if endpoint status bits are to generate interrupts, also set the appropriate mask bits in the aepdef3 register. C perform any additional programming of the definition registers that is required for the specific application. 2. enable the data endpoint by setting the ep_en bit in the aepctl register. 3. assign initial control of the data fifo to the usb endpoint hardware by clearing the act_req bit in the iepctl register. data sent by the host is written to the data fifo. at the end of a successful transfer, hardware sets the act_req bit to transfer control to software. to enable this bit as an interrupt source, set the a_ep_act bit in the uimask1 register. 4. when the act_req bit is set, read the endpoint fifo (aepdat). note that the number of bytes written by the host can be obtained from the aepsiz register. 5. after reading the appropriate number of bytes from the fifo, clear the act_req bit to give control back to the usb endpoint hardware and allow it to reuse the fifo for subsequent data. 18.5.1.4.2 endpoint a configured as bulk in, non-dma mode 1. program the endpoint a registers: C set ep_type = 10b (bulk) and ep_dir = 0 (in) in the aepdef1 register. C set mode = 000b (non-dma) in the aepdef3 register. C if interrupts are to be used, set the appropriate bits in the uimask1 or uimask2 register. if endpoint status bits are to generate interrupts, also set the appropriate mask bits in the aepdef3 register. C perform any additional programming of the definition registers that is required for the specific application. 2. enable the data endpoint by setting the ep_en bit in the aepctl register. 3. for an in endpoint, initial control of the data fifo is assigned to the device. device software can therefore write to the endpoint fifo (aepdat) when it is ready. 4. after it is finished writing to aepdat, software should clear the act_req bit in the iepctl register to give control back to the usb endpoint hardware and allow it to transmit the written data. hardware sets the act_req bit after the endpoint has successfully sent a data packet to the host and the packet has been acknowledged. to enable the act_req bit as an interrupt source, set the a_ep_act bit in the uimask1 register. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-15 5. device software can clear the not_flush bit in the aepctl register if it needs to update stale data in the fifo before the data is transmitted. this causes the usb hardware to return control to software by setting the act_req bit. however, the act_req bit is set only if there is no active data transfer from this endpoint to the host. device software can verify if the act_req bit is set and if it is, can update stale data by writing to the fifo (aepdat). 18.5.1.4.3 endpoint c configured as bulk out, general-purpose dma mode 1. program the endpoint c registers: C set ep_type = 10b (bulk) and ep_dir = 1 (out) in the cepdef1 register. C set mode = 010b or 011b (general-purpose dma) in the cepdef3 register. these modes behave the same when used for an out endpoint. C set the appropriate interrupt mask bits in the uimask1 or uimask2 register. for general-purpose dma operation, enable the appropriate interrupt mask bits in the cepdef3 register to allow the device software to be notified of the fifo status. for example, the full_pkt, short_pkt, other_error, or buffer_error status bits could stop the hardware, requiring device software to take appropriate action and then clear the act_req bit to let the hardware continue. C perform any additional programming of the definition registers that is required for the specific application. 2. in the general-purpose dma control 0 (gdxcon0) register for an available general- purpose dma channel, set dsel = 11100b (usb endpoint c, source-synchronized). make any other dma channel configuration settings that are required, then set st = 1 in the gdxcon0 register to enable the dma channel. enable the dma channel before enabling the dma request source to avoid data loss or initial error conditions. it is important to note that in dma mode, the act_req bit no longer serves as a semaphore lock for the data fifo. the data fifo now behaves as a circular fifo with simultaneous read/write capability. the act_req bit acts as a stop/go bit for the hardware. for details, see the xepctl register description in the am186?cc/ch/cu microcontrollers register set manual , order #21916. if software sets the endpoints act_req bit, the dma transfer stops until software clears the bit again. 18.5.1.4.4 endpoint c configured as bulk in, general-purpose dma mode with terminal count not ignored 1. program the endpoint c registers: C set ep_type = 10b (bulk) and ep_dir = 0 (in) in the cepdef1 register. C set mode = 011b (general-purpose dma, terminal count not ignored) in the cepdef3 register. in this mode, when the terminal count for the general-purpose dma channel reaches zero, the byte of data written is marked as the last byte in the usb endpoint fifo. if the transfer size is an integer multiple of the maximum packet size, device software can write a zero byte to the endpoint fifo by clearing the not_zero bit in the cepctl register and following that with a dummy write to the cepdat register. the not_zero bit is set automatically when the data port is written. C set the appropriate interrupt mask bits in uimask1 or uimask2. for general-purpose dma operation, enable the appropriate interrupt mask bits in the cepdef3 register to allow the device software to be notified of the fifo status. for example, the full_pkt, short_pkt, other_error, or buffer_error status bits could universal serial bus (usb) 18-16 am186?cc/ch/cu microcontrollers users manual stop the hardware, requiring device software to take appropriate action and then clear the act_req bit to let the hardware continue. C perform any additional programming of the definition registers that is required for the specific application. 2. in the general-purpose dma control 0 (gdxcon0) register for an available general- purpose dma channel, set dsel = 11101b (usb endpoint c, destination synchronized). make any other dma channel configuration settings that are required, then set st = 1 in the gdxcon0 register to enable the dma channel. enable the dma channel before enabling the dma request source to avoid data loss or initial error conditions. it is important to note that in dma mode, the act_req bit no longer serves as a semaphore lock for the data fifo. the data fifo now behaves as a circular fifo with simultaneous read/write capability. the act_req bit acts as a stop/go bit for the hardware. for details, see the xepctl register description in the am186?cc/ch/cu microcontrollers register set manual , order #21916. if software sets the endpoints act_req bit, the dma transfer stops until software clears the bit again. 18.5.2 data transmission and data types for the am186cc and am186cu microcontrollers, all communication across the usb takes place in full-speed mode. usb bus transactions involve transmissions in up to three types of packets: token, data, and handshake. the token packet contains information about the type and direction of the transaction as well as the device address and which endpoint to use. the data packet, if any, contains actual commands or data. there can be one data packet, none, or more than one in a transaction. the format of a data packet varies according to what type of endpoint is being used. the handshake packet contains information regarding whether or not the transaction was completed successfully. when beginning a transfer, the host issues a start-of-frame (sof) packet. when the usb peripheral controller decodes this packet, it indicates the start-of-frame in the usb interrupt status 2 (uistat2) register. also decoded in the start-of-frame packet is a time stamp, which the usb peripheral controller places in the time stamp (tstmp) register. 18.5.2.1 usb suspend, resume, and remote wakeup a usb suspend is indicated if traffic across the usb cable ceases for 3 ms or more. this causes the usb peripheral controller to go into suspend mode, which hardware indicates by setting both the susp bit in the usb device miscellaneous functions (usbmfr) register and the usb_sus bit in the usb interrupt status 2 (uistat2) register. the usb_sus can be enabled as an interrupt source by setting the corresponding bit in the uimask2 register. when a usb suspend is detected, software should take any necessary action and wait for a usb resume, which hardware indicates by clearing the susp bit in the usbmfr register and by setting the usb_res bit in the uistat2 register. usb_res can also be enabled as an interrupt source by setting the corresponding bit in the uimask2 register. the remote wakeup feature is provided for peripheral devices that might need to wake up the usb remotely. the devices remote wakeup feature must be enabled by the host, which does so by issuing an appropriate set_feature command to the device. this automatically sets the rwake_en bit in the usbmfr register. if the rwake_en bit is set and the controller is in usb suspend mode, device software can initiate a usb resume by setting the rwake bit in the usbmfr register. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-17 18.5.2.2 usb reset hardware sets the usb_rst bit in the uistat2 register when a usb reset signal is detected on the usb bus. the usb_rst bit can be enabled as an interrupt source by setting the corresponding bit in the uimask2 register. 18.5.2.3 usb protocol handling, in direction for endpoints that are configured for the in direction (transmit), data to be sent to the usb host is placed in the endpoint fifo by the device software or the dma controller. when the usb host issues an in token packet to the endpoint, the controller hardware converts the data stored in the endpoints fifo into a serial data stream, computes the crc, performs the bit stuffing operation, and generates the nrzi converted data stream. at the same time, it assembles the data packet in the correct format, including the sync, pid, data, crc, and eop fields as required by the usb specification. finally, the usb peripheral controller drives the data stream out to the usb host through the integrated transceiver drivers on the usbd+ and usbdC signal lines (or to an external transceiver if one is used). the device software is responsible for filling the endpoints fifo before starting the transaction, and for keeping the fifo full during the transaction, if necessary. if a packet error occurs, the device software is responsible for responding appropriately. for bulk transfers, this entails refilling the endpoint fifo with the data that was sent in the last frame. for isochronous transfers, the software must proceed to fill the fifo with data for the next packet. for more information, see error recovery on bulk and interrupt endpoints on page 18-22 and error recovery on isochronous endpoints on page 18-23. the controller hardware automatically generates the appropriate usb handshake packets for the various transfer types. the device software can cause the endpoint to enter its stalled condition when appropriate. 18.5.2.4 usb protocol handling, out direction for endpoints that are configured in the out direction (receive), the usb peripheral controller receives the serial data stream from the usb host. the usb peripheral controller hardware identifies the incoming sync field, performs the nrzi-to-nrz conversion, performs the bit-stripping operation, decodes the pid, and tests the devices addr and endp fields. for packets that are addressed to the device and an enabled endpoint number, the usb peripheral controller performs the serial-to-parallel conversion and places the data into the endpoints fifo. during this process, the endpoint hardware checks the packets crc, data toggle sense, and all handshake packets. in addition, the controller hardware monitors the number of data bytes sent by the host. if the number of bytes sent exceeds the endpoints maximum packet size, the usb peripheral controller automatically flags an error and sends a negative acknowledge packet to the host if the endpoint type is bulk, control, or interrupt. the primary responsibility of the device software or dma controller is to move data written into the endpoints fifo to system memory or some other microcontroller peripheral. the device software must also monitor the usb peripheral controller to service packet errors that are detected during reception. the appropriate usb handshake packets are generated automatically by the controller hardware for the various transfer types and error conditions. the device software can also cause the endpoint to enter its stalled condition when appropriate. universal serial bus (usb) 18-18 am186?cc/ch/cu microcontrollers users manual for the usb control endpoint, the system software is responsible for decoding and servicing several of the usb standard commands and all device class or vendor specific commands. hardware is provided that allows the system software to detect incoming commands, and respond appropriately. the hardware also allows the software to detect all command abort scenarios. 18.5.3 handling usb data the usb peripheral controller handles all of the low-level usb protocol requirements in hardware. data movement between device memory or other microcontroller peripherals and the usb peripheral controllers endpoints is managed by device software executing on the microcontroller cpu. the device software can use status polling or interrupts to handle fifo data for any endpoint (control, interrupt, and aCd). in addition, the data endpoints (aCd) support either general- purpose dma or smartdma channel transfers. device software sets up the method of operation for the endpoints by programming control and definition registers. there are register bits to enable or disable interrupts that can be generated as data transfers proceed, or the software can poll status bits to determine the status of each endpoint. registers for each data endpoint determine the dma channels used (if any), the endpoints direction (in or out, relative to the host), and its type (isochronous, bulk, or interrupt). these registers are also used to set up other information used in the usb configuration process. for control, interrupt, and bulk data transfers, usb guarantees correct data delivery with automatic retry. microcontroller hardware performs this task transparently to the software except for data endpoints that have been configured to use dma. when dma is being used, the device software is involved in error detection and recovery. for isochronous data transfers, the usb specification calls for only a good-faith attempt at delivery. isochronous transfers call for real-time delivery of each packet, so damaged packets cannot be retransmitted. special status and interrupt bits are provided for the control endpoint to indicate whether the packet currently in that endpoints fifo is a command that must be handled by device software. 18.5.4 polled i/o in polled i/o mode, no dma channel is specified, and interrupts are disabled. the device software must actively poll the usb status register to determine when it owns the endpoints fifo, and then it must write or read the endpoints data port register to fill or empty the fifo. an endpoint operates in this mode only when the maximum packet size has been programmed to be less than or equal to the size of the fifo. in this mode, the fifo cannot operate in a circular fashion as it does for dma transfers (see page 18-19). for a receive endpoint (out direction relative to the host), the usb peripheral controller sets the endpoints act_req bit in the status register whenever the fifo is full of valid data, or when an end-of-packet event has occurred. if this bit is set, the software can empty the fifo the next time it polls this endpoint. the amount of valid data in the fifo is indicated by the endpoints received packet size and buffer status registers. when software has finished reading the fifo, it must clear the act_req bit to release fifo ownership to the usb peripheral controller. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-19 for a transmit endpoint (in direction), the act_req bit is set if the fifo is ready to be filled with data. if this bit is set, software can fill the fifo when it has data for that endpoint to transmit, then it must clear the act_req bit to release the fifo. if an error occurs on a packet received by a bulk, control, or interrupt endpoint, the act_req bit is not set. instead, the fifo is flushed, and the host retransmits the packet. if an error occurs when the endpoint being addressed is isochronous, no retransmission can occur; the data that was sent or received must be used as is. 18.5.5 interrupt-driven i/o a single interrupt channel can be configured to alert software that the usb peripheral controller requires attention. interrupt mask fields allow the device software to enable the events it is interested in, and the status registers show which events have occurred. the interrupt mode of operation is very similar to the polled mode. it is an extension of the polled mode in which the act_req bit is enabled to cause an interrupt. the device softwares interrupt handler then polls the status bits to see which endpoint needs service. errors that occur in this mode are handled the same as in polled mode. 18.5.6 using usb with dma compared with polled or interrupt i/o, using dma with usb gives the following benefits: n improved throughput: this is an important consideration, not only from the microcontroller's perspective, but also from the usb host's perspective. if the microcontroller is ready to receive or transmit data whenever the host wishes, it reduces usb bus overhead due to retries. n larger packets: when the usb peripheral controller is used with dma, there is no restriction on packet size, other than that mandated by the usb specification (1023 bytes/packet for isochronous, 64 bytes/packet for bulk). when dma is not used, packets are restricted to the size of the endpoints' fifo. n automatic rate control: the microcontroller's automatic rate control feature is only available when using dma. this feature allows the amount of data sent in an isochronous in packet to be controlled by the number of pcm highway frames or other external events that occur in each usb frame. however, using dma with usb is more complicated than using polled or interrupt i/o. in polled or interrupt mode, the usb hardware performs all error handling itself. the host is notified only when a packet has been received or transmitted without errors. with dma, software is responsible for recovering from errors. this includes backing up dma pointers, taking into account the amount of data that has not yet been transferred to or from the endpoint's fifo, and so on. in addition, using dma requires extra programming effort even before exception handling is considered. 18.5.6.1 dma availability dma mode is only available for endpoints aCd. in dma mode, endpoints are programmed to use the microcontrollers general-purpose dma or smartdma channels. when used with a usb data endpoint, the general-purpose dma channels allow the device software to set up a single usb packet or an entire i/o request packet (irp) to transfer data automatically between memory and the endpoints fifo. during the transfer, software interaction is required only to handle fifo and usb packet errors. smartdma channel pairs 2 and 3 can be used with specific endpoints if they are configured in the correct direction, as shown in table 18-4. smartdma channels allow device software to set up single or multiple usb packets, or single or multiple irps, to be moved universal serial bus (usb) 18-20 am186?cc/ch/cu microcontrollers users manual automatically between the endpoints fifo and memory (or i/o), possibly using even less overhead than general-purpose dma. software interaction is still required to handle fifo and usb packet errors. selection of what type (if any) of dma to use for a particular type of usb data pipe should take into account several issues: n smartdma channels may be better for some tasks. for example, smartdma channels can transition from one fifo to the next without incurring any interrupt overhead or latency. n general-purpose dma is simpler to program and understand for many tasks. n each smartdma channel is only capable of operation in a single direction. because each endpoint is associated with a particular smartdma channel, a given system can have a maximum of two endpoints for any direction (in or out). when selecting dma channels to use, be sure to consider other microcontroller functions (such as hdlc or uarts) that might be using dma. see dma trade-offs on page 18-6. 18.5.6.2 dma/fifo interaction unlike the polled i/o or interrupt methods, in dma mode the maximum packet size can be programmed to a value greater than the physical size of the fifo. because of this, the protocol for filling or emptying a fifo is different than when using polled i/o or interrupts. the fifo in the endpoint operates in a circular fashion while in dma mode. for a receive (out) endpoint, the usb peripheral controller issues a dma request whenever the fifo is not empty. it continues to assert the dma request until the fifo is empty. the usb peripheral controller detects that a receive transaction has completed; either successfully or unsuccessfully. if a smartdma channel is configured to store packet status to the fifo descriptor, it handles packet errors automatically and places the error status in the last three bytes sent. if general-purpose dma is used, or if a smartdma channel is configured to not store packet status in the fifo descriptor, bits in the endpoints status register can cause an interrupt when an error occurs. for a transmit (in) endpoint, a dma request is asserted whenever the fifo is not full. the request assertion continues until the fifo is full. data bytes can be marked either as the last byte of the transfer or as a null byte. if the endpoint is configured to use a general- purpose dma channel, it can indicate the last byte upon reaching the terminal count. if the table 18-4 usb endpoints used with dma usb endpoint dma channel usb data endpoint (aCd) configured in either direction any general-purpose dma channel, 0C3 usb data endpoint a if configured as a usb out (receive) endpoint 1 notes: 1. smartdma channels 2 and 3 transmit and receive cannot be assigned to different peripherals. for example, if smartdma channel 2 receive is assigned to usb data endpoint a, then smartdma channel 2 transmit can be used for usb data endpoint b, but cannot be used with the hdlc controller on the am186cc microcontroller. smartdma pair 2 receive channel usb data endpoint b if configured as a usb in (transmit) endpoint. smartdma pair 2 transmit channel usb data endpoint c if configured as a usb out endpoint 1 smartdma pair 3 receive channel usb data endpoint d if configured as a usb in endpoint 1 smartdma pair 3 transmit channel universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-21 endpoint is configured to use a smart dma channel, information in the fifo descriptor indicates if a byte is the last byte or a null byte. 18.5.6.3 setting up dma for usb the usb peripheral controller gives the programmer a large degree of freedom in using dma with usb endpoints. in general, most methods of using dma with usb fall into one of three categories: n undelimited transfers are generally used for isochronous data that has no natural boundaries, such as audio data. for these types of transfers, either the smartdma channel or the general-purpose dma serve equally well to transfer data into a circular fifo. in addition, smartdma control can transfer data to or from another peripheral, such as the hdlc controller on the am186cc microcontroller. for undelimited in (to the host) transfers, the amount of data transferred in each packet is the endpoint's maximum packet size unless auto rate control is enabled on the endpoint. if auto rate control is enabled, the packet size can equal the number of samples received during the previous frame multiplied by a programmable byte/sample factor, if this value is less than the programmed maximum packet size. n buffer-per-packet transfers can be used for either bulk transactions or nonstreaming isochronous transfers. the amount of data transferred for each packet is determined by the fifo size. buffer per packet transfers are required if smartdma is used with packet status stored in the fifo descriptor (mode = 101b in the xepdef3 register). n buffer-per-i/o request packet (irp) transfers are similar to buffer-per-packet transfers, except that a dma fifo contains multiple packets. in general, buffer-per-irp is simpler to program for the normal case, but error handling is more complicated because dma must be restarted in the middle of the fifo. buffer per irp transfers are highly recommended for in endpoints using a smartdma channel. 18.5.6.4 short packets short packets typically delineate the end of a usb i/o request packet (irp). for example, if the maximum packet size is 64 bytes, and a fifo that is 260 bytes is to be transferred, four full-length packets are transferred followed by a packet that contains only four bytes. this delineation is very useful because it provides an out-of-band indication of where one information fifo ends and the next one starts. in fact, it is so useful that usb specifically allows for zero-length packets, to ensure that this delineation can be performed even when the fifo size is a multiple of the maximum packet size. the smartdma channel is fully capable of sending and receiving zero-length packets. (on receive, it simply stores the byte count provided by the usb peripheral controller, which is zero, and on transmit, a special signal from the smartdma controller indicates that the packet has no data.) with general-purpose dma, receiving a zero-length packet is exactly the same as receiving any other short packetthe usb should be set to stop on receipt of a short packet, and the software examines the received length. sending a zero-length packet is performed differently because no data is transferred through the dma controller. to send a short packet of one byte or greater, simply program the dma controller to send the desired count, after programming the usb peripheral controllers dma mode to 011. in this mode, when the dma controller sends the last byte, the packet is sent, even if the usb fifo is not full. to send a zero-byte packet in general-purpose dma mode, you must clear the not_zero bit in the xepctl register, and then write one byte (of any value) to the endpoints fifo. universal serial bus (usb) 18-22 am186?cc/ch/cu microcontrollers users manual 18.5.6.5 error recovery on bulk and interrupt endpoints when an endpoint is configured as a bulk or interrupt endpoint, data delivered over the endpoint is guaranteed to be correct, but is not guaranteed to be delivered within any certain time interval. when dma is used, device software must intervene when exceptions occur to guarantee correct data. the following error recovery situations must be considered: n smartdma channel receive does not require any low-level software intervention if the usb dma mode is set to 110 (store status in smartdma channel fifo). instead, the higher level software that pulls packets out of the smartdma channel fifo descriptor ring must examine each fifos status to determine if it was received correctly or not, and discard fifos with errors. n if smartdma channel receive is used when the usb dma mode is set to 100 (dont store status), then all status processing must be performed by low level software. this mode is typically used for bulk data if it is desired to receive an entire usb irp as a single fifo. because the usb hardware is not storing any status in the smartdma channel descriptors, it is up to software to program the usb endpoint to interrupt whenever an error or a short packet is received. the interrupt handler should then disable the smartdma channel, update the smartdma channel descriptor (because some good data may have been stored before the bad datathe descriptor is updated to point to where the bad data was received so that it can be overwritten) and the smartdma channel descriptor pointer, re-enable the smartdma channel, and then restart the usb endpoint by clearing the act_req and interrupt bits. this is a significant amount of overhead, but the interrupt routine is only executed when an error or an end of packet occurs, and the higher level software never needs to worry about retrieving bad data from the fifo, because the interrupt routine can make sure that all stored data is good before status is stored. n like smartdma channel receive, general-purpose dma receive can either be performed per packet or per irp, depending on whether the usb is programmed to stop on all packets or just on short packets. if an error occurs, it is up to the software to back the dma pointer up to the start of the current packet (using information about where it is and how much data is still left in the fifo), and clear the error and the act_req bit. n smartdma channel transmit requires the usb to be set to stop on errors. if an error occurs during transmit, the interrupt handler must disable the smartdma channel, program its fifo pointer to point back to the failing location, restart the dma, and then flush the fifo and restart the endpoint by clearing the act_req, not_flush, and error bits. if the smartdma channel is being used in buffer-per-packet mode, then only the smartdma channels fifo descriptor pointer needs to be updated, but if the smartdma channel is being used in a buffer-per-irp mode, then the smartdma channels memory pointer must be read, and the actual fifo descriptor in memory must be reprogrammed (starting address and length) so that the dma can be restarted in the middle of the fifo. when reprogramming the starting address, the number of bytes that were transferred from memory to the fifo before the error occurred must be taken into account. n general-purpose dma transmit requires that the dma mode be set to 011, to stop and interrupt on dma terminal count. as with the smartdma channel, just because a dma fifo has been sent to the host doesnt mean that it has been successfully delivered. interrupts should be enabled for fifo errors and other errors, and if an error occurs, the current packet must be resent. if multiple packets are in the fifo (buffer per irp), then the start of the current packet in the fifo must be calculated by taking into account the current dma pointer and the number of bytes that are currently stored in the endpoint's fifo. the endpoint's fifo should be flushed before dma is restarted. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-23 18.5.6.6 error recovery on isochronous endpoints isochronous data, by definition, is very time-sensitive. neither pcm highway nor usb have any mechanism or concept of retransmission of isochronous data. nevertheless, there are error-recovery issues with isochronous data. for the intended audio applications, these primarily revolve around making sure that fifo pointers do not overlap or drift too far apart. for example, assume the am 186cc microcontrollers hdlc controller is storing audio data in a circular fifo, and the usb peripheral controller is pulling audio data out of the fifo. because usb operation happens in (nominally) 8 sample bursts, and pcm highway operation happens one sample at a time, if the fifo pointers ever overlapped, old data could be transmitted intermixed with the new data, and the audio would be garbled. likewise, if the pointers get too far apart, excessive delay is introduced in the audio. during normal operation, the pointers should stay a relatively constant distance apart. however, it is possible to miss a frames worth of data on the usb, because isochronous transfers are not guaranteed. when this occurs, the best that software can do is to adjust the dma pointers to keep the error localized as a single glitch in the audio, rather than let it accumulate and cause excessive delay, or cause garbled audio (by the pointers repeatedly crossing each other). it is probably also a good idea for a missed out transaction for usb (pcm highway pipes) to inject silence into the fifo for the duration of the missed transaction, to minimize the annoyance of the audio glitch. adjusting the pointers is very straightforward on a general-purpose dma circular fifo (e.g., stop the dma, add a constant to the pointer, and restart the dma), but is more complicated on the smartdma channel. if a smartdma channel is being used for isochronous data, the simplest thing to do is to set it up so that there are two descriptors in the ring. each descriptor points to a portion of the circular fifo. when a pointer needs to be adjusted, the dma is stopped, the current location (low order 16 bits) of the memory pointer is read from the dma hardware, a new value is calculated by adding or subtracting the adjustment from the memory pointer, and the fifo descriptors are updated so that the next one executed covers the portion of the fifo from the new memory pointer to the end of the fifo, and the other descriptor covers the portion of the fifo from the start of the fifo to the new pointer. then the dma is restarted. note that, because such an adjustment could make one fifo very small (e.g. one byte), it is important to use the feature that allows dma own bits to be reset. otherwise, dma effectively stops and requires software intervention each time through the fifos, and there is a latency requirement to service both the descriptors within a very short time period. 18.5.7 isochronous transfer synchronization the isochronous transfer type is required by audio, telephony, or other applications that need real-time streaming delivery to avoid distortion. the usb configuration process ensures that the data pipe from the host to an isochronous endpoint has enough bandwidth to transfer the endpoint's maximum packet size in every frame, but the design must also synchronize the data so it is delivered at the correct rate. cc universal serial bus (usb) 18-24 am186?cc/ch/cu microcontrollers users manual isochronous synchronization involves converting the data stream from its sample rate (for example, the 44.1-khz rate of an audio cd player) into packets delivered at the fixed usb start-of-frame (sof) rate of 1 khz (1000 frames per second). the usb specification defines three types of isochronous synchronization: n asynchronous : the data sample clock and the usb frame rate are independent of each other. it is up to the hosts device driver and device software to convert the data rate as needed. for example, a receiving endpoints software (host or device) can provide feedback so the transmitting endpoints software can adjust the amount of isochronous data sent in each frame. n synchronous : the data sample rate is synchronized with the usb sof rate so the same amount of isochronous data can be transmitted in every frame. there are two ways to achieve this: C lock the data source sample clock to the usb sof rate. for example, a design can route the microcontrollers usbsof output through a pll to drive the sample clock of an external codec. for more about the usbsof signal, see isochronous synchronization signals on page 18-6. C request usb master client capability (through the usb driver basic host interface) and then adjust the usb sof rate to keep it synchronized with the sample clock. only one device can be the master client at a time, so devices that use this method must be able to operate asynchronously if master client capability is denied. n adaptive : the data sample clock can be freely adjusted to receive or transmit data at any rate within a given range. the microcontrollers auto rate feature (described in the following section) allows isochronous in endpoints to implement adaptive synchronization with a variety of input sources. the type of synchronization to use for an isochronous endpoint depends on the design requirements and capabilities of the peripheral device. all of these synchronization types make use of usb peripheral controller features described in the following section. 18.5.8 isochronous transfer features the usb peripheral controller provides full support for the isochronous transfer type while minimizing system resource overhead. a usb peripheral device using the am186cc or am186cu microcontroller can easily support the isochronous data transfer in the in direction as an asynchronous, synchronous, or adaptive synchronous data source. these features combined with the other integrated communications devices and dma controller allow many different communications and audio devices to be built with this device. the following microcontroller features are provided to support isochronous transfers: n missing-sof detection : the usb peripheral controller implements an adaptive missing-sof detection mechanism. a missing sof packet is detected when the current usb frame length is six usb bit times greater than the last frame in which a sof packet was successfully received. hardware indicates a missing sof by setting the uistat2 registers ms_sof bit, which software can enable as an interrupt source by setting the corresponding bit in the uimask2 register. n sof generation : whenever an sof is detected, hardware sets the uistat2 registers sof_gen bit, which software can enable as an interrupt source by setting the corresponding bit in the uimask2 register. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-25 the sof is also reflected on the controllers usbsof output signal, which is used in the first method (lock the sample clock) of synchronous isochronous synchronization, as described in isochronous transfer synchronization on page 18-23. if a missing sof is detected, the usb peripheral controller automatically generates an internal sof, which is reflected by the sof_gen bit and the usbsof signal. this allows synchronous isochronous endpoints to remain locked to the usb clock even when the sof packet is corrupted on the bus. n usb frame position monitoring : this allows the device software to detect any difference between the sample rate of a data source and the usb frame rate. this is required for an isochronous in endpoint that uses the second method (request usb master client capability) for synchronous isochronous synchronization, as described in isochronous transfer synchronization on page 18-23. in the am186cc microcontroller, the sam_clk_sel field in the isctl register can select a sample rate clock source: either the usbsci signal (on the uclk pin) or the frame synchronization signal used for hdlc channel a, pcm highway, and gci. during each usb frame, the fpmcnt register latches the usb frame position bit counter after a specific number of source clocks are counted on the sample input. the value latched in the fpmcnt register is the number of usb bit times counted during the source clock interval specified in the bcnt_lrate field of the isctl register (1C64 source clocks, programmable in powers of two). device software can compare these two values to determine whether the usb frame rate and the source sample clock are moving relative to each other. if the device is granted master client capability, it is able to use the usb device basic host interface (defined in the usb specification) to gradually increase or decrease the usb sof rate to correct any drift with respect to the data sources sample rate. whenever fpmcnt is updated, hardware sets the uistat2 registers pos_up bit, which software can enable as an interrupt source by setting the corresponding bit in the uimask2 register. n auto rate: this allows the designer to implement adaptive synchronization on an isochronous in endpoint using general-purpose dma or smartdma to handle an arbitrary data source rate. the auto rate feature uses the data sources sample rate clock (frame rate) as an input to automatically control the number of data bytes sent to the usb host during each transaction. in the am186cc microcontroller, the sam_clk_sel field in the isctl register can select a sample rate clock source: either the usbsci signal (on the uclk pin) or the frame synchronization clock (fsc) signal used for hdlc channel a, pcm highway, and gci. the bytes_sam field in isctl sets the number of bytes to move per source clock sample (1, 2, or 4 bytes). also make sure that the max packet size programmed for the endpoint is greater than or equal to the largest number of data bytes that the endpoint might need to move during a usb transaction. after the sample clock source and bytes per sample are selected, set the auto_rate_en bit in the xepdef3 register (where x = a, b, c, or d) to enable auto rate for the endpoint. cc cc universal serial bus (usb) 18-26 am186?cc/ch/cu microcontrollers users manual the specified number of bytes is transferred on each sample clock as long as data is present in the endpoints fifo, or is sequentially written to the fifo as needed during the transaction. n start of frame and frame number monitoring : the usb peripheral controller monitors the usb sof packet and latches the frame number value into the time stamp (tstmp) register upon successfully receiving the sof packet from the usb host. software can arm the time stamp match (tstmpm) register by writing a specific usb frame number to it. then, when the usb peripheral controller receives an sof packet with a number greater or equal to the written value, hardware sets the uistat2 registers tstmp_m bit, which software can enable as an interrupt by setting the corresponding bit in uimask2. the interrupt does not occur again until tstmp_m is cleared in uistat2 and tstmpm is written again. this mechanism allows software to start a certain data pattern during a specific usb frame, if required. this feature can be used for asynchronous usb data sources using implicit data pattern generation. 18.5.9 command handling the primary function of the devices control endpoint is to accept and respond to commands issued to it by the usb host. all of the usb standard, device class, and vendor specific commands are issued to the control endpoint known as the device endpoint 0. the usb peripheral controller hardware handles some of these commands without requiring that the device software decode and specifically handle the command. other commands are received from the usb host and passed on to the device software for processing. these commands and how they are handled are outlined in the following sections. 18.5.9.1 commands handled by device software table 18-5 on page 18-27 describes the commands that must be handled by the device software. when any command is received by the usb peripheral controller, hardware sets the new_command bit in the cntctl register. if the device software must take some action, the act_req bit is also set in the affected endpoints xepctl register. the new_command bit and all of the act_req bits have mirror bits in the uistat1 register. (a mirror bit is set whenever the corresponding status bit is set.) each mirror bit can be enabled as an interrupt source by setting the corresponding bit in the uimask1 register. the software is then required to decode the command data and either: n accept subsequent data associated with the command (for out commands). when it is finished handling an out command, software must clear the command_busy bit in the cntctl register to indicate that it is ready to process more commands. n return the appropriate data requested in the command (for in commands). the usb peripheral controller hardware automatically clears the command_busy bit in the cntctl register when it finishes transmitting the requested data. all of the low-level usb protocol processing is handled entirely in hardware (that is, all handshake packets are accepted from or returned to the usb host automatically). universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-27 . 18.5.9.2 commands handled by the usb peripheral controller hardware table 18-6 on page 18-28 describes the commands that do not require device software handling. when these commands are detected by the usb peripheral controller, they are handled entirely in hardware. the device software does have the ability to detect the reception of any usb setup packet sent to it by the usb host, but it cannot monitor the specific setup packet type when the command is handled solely by the controller hardware. table 18-5 usb commands handled by device software command parameters and data passed data direction results get_descriptor device, configuration, or string descriptor in the device software, upon detecting this command, should return all of the data associated with the particular descriptor that was requested. because this controller allows the endpoint parameters to be programmed at any time, an un- limited number of descriptors can be supported. set_configuration device configuration out the device software, upon detecting this command, should configure all of the endpoints with the applicable usb parameters based on the descriptor information that was passed to the host during the get_descriptor command. set_interface interface alternate setting out the device software, upon detecting this command, should configure the endpoints associated with the specified interface, for the requested alternate setting, based on the descriptor information that was passed to the host during the get_descriptor command. set_descriptor device, configuration, string, interface, or endpoint descriptor out the device software, upon detecting this command, should accept a new descriptor from the usb host. sync_frame synchronization frame in the device software, upon detecting this command, should return the frame number in which an isochronous, in endpoint begins its data pattern. device class or vendor specific various in and out the device software should service the commands that it has been programmed to handle. if the device software does not recognize a particular command it should clear the ep_not_stalled bit in the cntctl register to direct the controller hardware to return the stalled handshake in the data stage. (the new_command bit must be cleared at the same time, or clearing the ep_not_stalled bit has no effect.) universal serial bus (usb) 18-28 am186?cc/ch/cu microcontrollers users manual 18.5.10 command protocol as a slave device, the am186cc or am186cu microcontroller must always be prepared to let the usb master send a new setup packet. in other words, software could be processing a command, and the host could send a new command without warning. the software should stop working on the old command and deal with the new one immediately. in practice, it is impossible to arbitrarily stop a program at any point like this. for example, the software could have been writing out a response to the previous command, and stopping it at a precise moment is very difficult. the new_command interlock bit allows the hardware to ignore the software during time periods when the software is still in the middle of processing a previous command. during processing of a command, the act_req bit is politely bounced back and forth between hardware and software. for setup and control write packets (data from the host), hardware sets the act_req bit to indicate that the host has filled the fifo. software then clears the act_req bit to indicate that it has drained the fifo. for control read packets, table 18-6 usb commands handled by usb peripheral controller hardware command parameters and data passed data direction results set_address devices usb address out device stores the address assigned to it by the usb host. set_feature device remote wake-up, or endpoint stall out the devices remote wake up feature is enabled (or) a particular endpoint is forced to be stalled. if the specified endpoint is not configured, the device returns the stalled handshake to the host during the status stage. clear_feature device remote wake-up, or endpoint stall out the devices remote wake-up feature is disabled (or) a particular endpoint is forced to be un-stalled. if the specified endpoint is not configured, the device returns the stalled handshake to the host during the status stage. get_status device self powered, device remote wake-up, or endpoint stall status in the devices programmable self powered bit is returned to the usb host as a value of 1 or 0, indicating that the device is self-powered or bus-powered. the remote wake up bit is returned with a value that depends on whether the remote wake up feature was last set or cleared. a particular endpoints stall status is returned to the usb host. if the specified endpoint is not configured, the device returns the stalled handshake to the host during the status stage. get_configuration devices current configuration in the current device configuration number is returned to the usb host. get_interface interfaces current selected alternate setting in the currently selected alternate setting for the interface number that is specified in this command is returned to the usb host. if the specified interface is not present, the device returns the stalled handshake to the host during the status stage. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-29 software clears the act_req bit when it has filled the fifo with information to go to the host, and hardware sets the act_req bit after the information has safely made it to the host. the host can send a new command at any time, so the new_command bit provides a somewhat less polite method for the hardware to inform the software of who owns the fifo. when a setup packet is detected (before it is written to the fifo), the hardware clears the act_req bit, and sets the new_command bit, to show that the hardware stole ownership from the software. because the software could be busy trying to update the fifo and/or the act_req, ep_not_stalled, or command_busy bits, the host locks out accesses to the fifo and these bits whenever new_command is set. attempts by software to read or write the fifo, or to alter these bits, fail silently. when a command is received that software must handle, it is stored in the fifo and then the act_req bit is set to indicate that the fifo contains valid data. 18.5.10.1 data transfer using the control endpoint the control endpoint can transfer data, but there are several potential problems. at the end of control read data transfers, it is impossible for the software to know whether the host accepted the most recent data sent, or whether it sent the status stage before accepting the data. for usb commands, it is not an error for the host to terminate a command early. for example, it can ask to read descriptors, and enter the status phase before it has finished reading all the descriptors. this is problematic for data transfers, and the only real way around it is for the host to transmit information in the setup packet that describes where in the data stream it wishes to start reading. at the end of control write data transfers, it is impossible for the software to know whether the device successfully completed the status phase, or whether a new setup packet aborted the status phase. as with the control read problem, this problem can be alleviated by the host sending information in the command packet about where in the data stream this write should start. 18.5.10.2 control endpoint interrupts the act_req bit and the new_command bit are reflected in the uistat1 register as the cnt_ep_act and cnt_ep_new bits. software can mask off these interrupts in the uimask1 register. most applications use only the cnt_ep_act interrupt, but some applications may find it advantageous to use the cnt_ep_new interrupt. this interrupt is useful if the system spawns a new task to deal with data transactions. in this case, the software could use a cnt_ep_new interrupt to spawn the task dealing with the aborted command. 18.5.11 interrupt endpoint programming the microcontroller's usb interface contains one interrupt endpoint. the purpose of an interrupt endpoint is to allow small amounts of data to be transferred from the device to the host. according to section 4.7.3 of the usb specification, a small, spontaneous data transfer from a device is referred to as interrupt data. such data can be presented for transfer by a device at any time, and is delivered by the usb at a rate no slower than as is specified by the device. interrupt data typically consists of event notification, characters, or coordinates that are organized as one or more bytes. an example of interrupt data is the coordinates from a pointing device. although an explicit timing rate is not required, interactive data may have response time bounds that the usb must support. universal serial bus (usb) 18-30 am186?cc/ch/cu microcontrollers users manual 18.5.11.1 usb command processing and the interrupt endpoint when a set_configuration or set_interface command is received, software must reprogram the interrupt endpoint definition registers (if necessary) to reflect the new configuration and alternate interface setting. also, the descriptor relating to the interrupt endpoint (which is returned to a host get_descriptor request) must contain the correct maximum packet size (8 or 16 bytes) and interval value (1-ms to 255-ms interrupt rate). 18.5.11.2 data transfer with the interrupt endpoint the interrupt endpoint can be used in two different ways. if the amount of data to be transferred on each interrupt is less than or equal to the maximum packet size, each packet sent to the host constitutes an entire transaction. if the amount of data to be transferred on each interrupt exceeds the maximum packet size, an interrupt can consist of multiple packets. in this case, each packet except the last one must be maxpacketsize bytes. transferring a number of bytes between 0 and maxpacketsize C 1 (inclusive) denotes the end of the transaction. if a large number of bytes are to be transferred on each interrupt, it is strongly suggested that the maximum packet size be set to 16, because this makes more efficient use of the usb bandwidth than a setting of 8. 18.5.11.3 interrupt endpoint interrupts the act_req bit is reflected in the uistat1 register as the int_ep_act bit. software can mask off this interrupt in the uimask1 register. 18.5.12 endpoint definitions the usb specification provides for endpoints to be grouped into interfaces. multiple interfaces that do not share endpoints can be grouped into configurations, and a device can have multiple configurations, only one of which can be in use at any one time. in the am186cc and am186cu microcontrollers, software assigns each of the endpoints (other than the control endpoint, which has a number of 0 and appears in every interface) an endpoint number, interface number, configuration number, alternate setting number, max packet size, and direction. the usb specification, version 1.0 defines the endpoint configuration process: host software should only set configuration and interface values that match a device descriptor returned by the device in response to a get_descriptor command. however, the usb hardware accepts as valid any configuration or feature setting in the range of 0d to 3d, regardless of the available descriptors. to help ensure reliable operation in any usb environment, device software can define a minimal descriptor (i.e., endpoint 0 with no bandwidth allocation) for any configuration and interface settings that it does not define otherwise. 18.5.12.1 control endpoint definition the control endpoint features are not programmable as are the other endpoints. this endpoint is common to, and is required by, all usb device class specifications. table 18-7 lists the control endpoint parameters. the control endpoint (endpoint 0) is always considered to be a member of all device configurations, a member of all interfaces present in a device configuration, and a member of all alternate settings of any given interface. universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-31 18.5.12.2 interrupt endpoint definition the am186cc and am186cu microcontrollers each provide one dedicated interrupt endpoint. typically, all of the usb device class specifications require that a usb device contain at least one interrupt endpoint. the usb host uses this endpoint, in conjunction with the devices control endpoint, to process class-specific transactions and to generally service specific device requests when required. the interrupt endpoint features are highly programmable. device software can modify these features at any time in response to the various commands issued to the devices control endpoint. the usb host can make these requests during the device enumeration process or at any other time during the device operation. table 18-8 lists the interrupt endpoint features. table 18-7 control endpoint definition parameter value usb parameters number 0 configuration all interface all alternate setting all type control maximum packet size eight bytes system parameters data handling polled i/o or interrupt driven fifo depth eight bytes table 18-8 interrupt endpoint definition parameter value usb parameters number 1C15 configuration 0C3 interface 0C3 direction in (to host only) alternate setting 0C7 type interrupt max packet size 8 or 16 bytes system parameters data handling polled i/o or interrupt driven fifo depth 16 bytes universal serial bus (usb) 18-32 am186?cc/ch/cu microcontrollers users manual 18.5.12.3 data endpoint definition the am186cc and am186cu microcontrollers each provide four general-purpose data endpoints. these endpoints transfer large amounts of data between the usb host and device using either the usb bulk, isochronous, or interrupt transfer protocols. note that if the data endpoint is programmed for interrupt transfer, the dma mode is not applicable. typically, all of the usb device class specifications require that a usb device contain any number and type of data endpoints to transfer the various data types required by the device class. the data endpoint features are highly programmable. device software can modify these features at any time in response to the various commands issued to the devices control endpoint. table 18-9 lists the data endpoint features. table 18-9 data endpoints aCd definition parameter values usb parameters number 1C15 configuration 0C3 interface 0C3 alternate setting 0C7 direction (endpoints a and c) in or out out direction (endpoints b and d) in type interrupt, bulk, or isochronous bulk isochronous bulk isochronous max. packet size (endpoints a and b) 1C16 bytes (8 or 16 for bulk) 8, 16, 32, or 64 bytes 1C1023 bytes 1 notes: 1. a 24-mhz processor clock is not fast enough for software to keep up with 1023-byte isochronous in or out packets using only an 8, 16, or 32-byte fifo. if a 24-mhz processor clock is used and a max packet size of 1023 bytes is required for isochronous data, use endpoint c or d and set the fifo size to 64 bytes. 8, 16, 32, or 64 bytes 1C1023 bytes 1 max. packet size (endpoints c and d) 1C64 bytes (8 16, 32, or 64 for bulk) 8, 16, 32, or 64 bytes 1C1023 bytes 8, 16, 32, or 64 bytes 1C1023 bytes system parameters data handling polled i/o or interrupt driven general-purpose dma smartdma channel fifo depth (endpoints a and b) 8 or 16 bytes fifo depth (endpoints c and d) 8, 16, 32, or 64 bytes universal serial bus (usb) am186?cc/ch/cu microcontrollers users manual 18-33 18.5.13 software-related considerations n a data endpoint must be configured with the xepdefx register before enabling it with the ep_en bit in the xepctl register. n when the mode bit field in the xepdef3 register is set to 101b (smartdma channel, status stored in the buffer descriptor), a bulk out transfer that results in a retransmission of data by the host due to handshake packet errors produces the following buffer descriptor field values: stp = 1, enp = 1, and crc = 1. the mcnt value in the buffer descriptor is invalid because setting the crc bit causes the err bit to be set as well. also, when the mode bit field is set to 101b, a bulk or isochronous out transfer with a message size that is an integer multiple of the maximum packet size results in the following buffer descriptor field values: stp = 1, enp = 1, and mcnt = 0. 18.6 initialization on both an external and internal reset, the following occurs: n all usb interrupts are cleared and masked. n the usb peripheral controller reports that it is self-powered (s_power bit of the usbmfr register is set). n the interrupt endpoint number is set to 1. n the interrupt endpoint fifo defaults to 16 bytes deep. n the interrupt endpoint maximum packet size is set to 16d. n the a, b, c, and d endpoints default to out direction, bulk type, with a maximum packet size of 8 bytes. n the a and b endpoint fifos default to 16 bytes deep. n the c and d endpoint fifos default to 64 bytes deep. n the isochronous missed packet and full data packet interrupts are unmasked. universal serial bus (usb) 18-34 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual a-1 appendix a register summary table a-1 on page a-2 provides a summary of all the am 186cc/ch/cu microcontrollers peripheral control block (pcb) registers, listed in offset order. the table includes the following information for each register: n abbreviated name n register description page number n relative offset from the pcb base (set in reloc) n default location in i/o space (equal to the default pcb base of fc00h plus the registers relative offset) n default value at reset n bit and field names and layout an x in the default value column denotes a digit for which the default value is not defined. a ? indicates that the digits value depends on external inputs. if a digit contains both undefined and external input bits, a ? is used. if more than one default value is given for a register, it contains one or more bits with undefined defaults. in this case either value might be present. if a group of registers is not supported on all the am186cc/ch/cu microcontrollers, the group heading indicates the controllers that support that group of registers. an exclamation point ( ! ) following a specific bit or register name indicates that additional controller-specific information can be found in the individual register or bit description. r e g i s t e r s u m m a r y a-2 am186 ?cc/ch/cu microcontrollers users manual table a-1 am186cc/ch/cu microcontrollers register summary name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hdlc channel a registers hacon 00h fc00h 0000h res hreset res nrzi transm loopr loopl crctype hatcon0 02h fc02h 0000h res tthrsh res tfifoen forabr hten imstart crcdis lbread lbnow hatcon1 04h fc04h 0000h res flagidl mltdrp autocts tmsbf txcinv gciden odrv tdelay harcon0 06h fc06h 0000h res rthrsh rcpst rmsbf rxcinv rreject rstop hren minrl harcon1 08h fc08h 0000h maxrl hastate 0ah fc0ah 0010h 0030h res ctss rtrs aborts markis flags frames haistat0 0ch fc0ch 0000h res reof rthres rdata1 tthres tdata1 res fabrst ctslst tuflo tgoodf tstop haimsk0 0eh fc0eh 0000h res reof rthres rdata1 tthres tdata1 res fabrst ctslst tuflo tgoodf tstop haistat1 10h fc10h 0000h res mamc sfmc short vshort rtrdes roflo aborte markie flage framee haimsk1 12h fc12h 0000h res mamc sfmc short vshort rtrdes roflo aborte markie flage framee hatd 14h fc14h 00xxh res tdata hard 16h fc16h 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 rdata harfs1 (16h) (fc16h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fbcnt[7C0] harfs2 (16h) (fc16h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fbcnt[15C8] harfs3 (16h) (fc16h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fram foflo crce mtch fabort flong fshort hardp 18h fc18h 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 rdata hasfcnt 1ah fc1ah 0000h hsfcnt hasfcntp 1ch fc1ch 0000h hsfcntp hamacnt 1eh fc1eh 0000h hmacnt hamacntp 20h fc20h 0000h hmacntp haa0 22h fc22h 0000h ha haa0msk 24h fc24h 0000h hamsk haa1 26h fc26h 0000h ha haa1msk 28h fc28h 0000h hamsk haa2 2ah fc2ah 0000h ha haa2msk 2ch fc2ch 0000h hamsk haa3 2eh fc2eh 0000h ha haa3msk 30h fc30h 0000h hamsk name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc ch register summary am186 ?cc/ch/cu microcontrollers users manual a-3 hdlc channel b registers hbcon 40h fc40h 0000h res hreset res nrzi transm loopr loopl crctype hbtcon0 42h fc42h 0000h res tthrsh res tfifoen forabr hten imstart crcdis lbread lbnow hbtcon1 44h fc44h 0000h res flagidl mltdrp autocts tmsbf txcinv gciden odrv tdelay hbrcon0 46h fc46h 0000h res rthrsh rcpst rmsbf rxcinv rreject rstop hren minrl hbrcon1 48h fc48h 0000h maxrl hbstate 4ah fc4ah 0010h 0030h res ctss rtrs aborts markis flags frames hbistat0 4ch fc4ch 0000h res reof rthres rdata1 tthres tdata1 res fabrst ctslst tuflo tgoodf tstop hbimsk0 4eh fc4eh 0000h res reof rthres rdata1 tthres tdata1 res fabrst ctslst tuflo tgoodf tstop hbistat1 50h fc50h 0000h res mamc sfmc short vshort rtrdes roflo aborte markie flage framee hbimsk1 52h fc52h 0000h res mamc sfmc short vshort rtrdes roflo aborte markie flage framee hbtd 54h fc54h 00xxh res tdata hbrd 56h fc56h 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 rdata hbrfs1 (56h) (fc56h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fbcnt[7C0] hbrfs2 (56h) (fc56h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fbcnt[15C8] hbrfs3 (56h) (fc56h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fram foflo crce mtch fabort flong fshort hbrdp 58h fc58h 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 rdata hbsfcnt 5ah fc5ah 0000h hsfcnt hbsfcntp 5ch fc5ch 0000h hsfcntp hbmacnt 5eh fc5eh 0000h hmacnt hbmacntp 60h fc60h 0000h hmacntp hba0 62h fc62h 0000h ha hba0msk 64h fc64h 0000h hamsk hba1 66h fc66h 0000h ha hba1msk 68h fc68h 0000h hamsk hba2 6ah fc6ah 0000h ha hba2msk 6ch fc6ch 0000h hamsk hba3 6eh fc6eh 0000h ha hba3msk 70h fc70h 0000h hamsk table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc ch register summary a-4 am186 ?cc/ch/cu microcontrollers users manual hdlc channel c registers hccon 80h fc80h 0000h res hreset res nrzi transm loopr loopl crctype hctcon0 82h fc82h 0000h res tthrsh res tfifoen forabr hten imstart crcdis lbread lbnow hctcon1 84h fc84h 0000h res flagidl mltdrp autocts tmsbf txcinv gciden odrv tdelay hcrcon0 86h fc86h 0000h res rthrsh rcpst rmsbf rxcinv rreject rstop hren minrl hcrcon1 88h fc88h 0000h maxrl hcstate 8ah fc8ah 0010h 0030h res ctss rtrs aborts markis flags frames hcistat0 8ch fc8ch 0000h res reof rthres rdata1 tthres tdata1 res fabrst ctslst tuflo tgoodf tstop hcimsk0 8eh fc8eh 0000h res reof rthres rdata1 tthres tdata1 res fabrst ctslst tuflo tgoodf tstop hcistat1 90h fc90h 0000h res mamc sfmc short vshort rtrdes roflo aborte markie flage framee hcimsk1 92h fc92h 0000h res mamc sfmc short vshort rtrdes roflo aborte markie flage framee hctd 94h fc94h 00xxh res tdata hcrd 96h fc96h 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 rdata hcrfs1 (96h) (fc96h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fbcnt[7C0] hcrfs2 (96h) (fc96h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fbcnt[15C8] hcrfs3 (96h) (fc96h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fram foflo crce mtch fabort flong fshort hcrdp 98h fc98h 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 rdata hcsfcnt 9ah fc9ah 0000h hsfcnt hcsfcntp 9ch fc9ch 0000h hsfcntp hcmacnt 9eh fc9eh 0000h hmacnt hcmacntp a0h fca0h 0000h hmacntp hca0 a2h fca2h 0000h ha hca0msk a4h fca4h 0000h hamsk hca1 a6h fca6h 0000h ha hca1msk a8h fca8h 0000h hamsk hca2 aah fcaah 0000h ha hca2msk ach fcach 0000h hamsk hca3 aeh fcaeh 0000h ha hca3msk b0h fcb0h 0000h hamsk table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc register summary am186 ?cc/ch/cu microcontrollers users manual a-5 hdlc channel d registers hdcon c0h fcc0h 0000h res hreset res nrzi transm loopr loopl crctype hdtcon0 c2h fcc2h 0000h res tthrsh res tfifoen forabr hten imstart crcdis lbread lbnow hdtcon1 c4h fcc4h 0000h res flagidl mltdrp autocts tmsbf txcinv gciden odrv tdelay hdrcon0 c6h fcc6h 0000h res rthrsh rcpst rmsbf rxcinv rreject rstop hren minrl hdrcon1 c8h fcc8h 0000h maxrl hdstate cah fccah 0010h 0030h res ctss rtrs aborts markis flags frames hdistat0 cch fccch 0000h res reof rthres rdata1 tthres tdata1 res fabrst ctslst tuflo tgoodf tstop hdimsk0 ceh fcceh 0000h res reof rthres rdata1 tthres tdata1 res fabrst ctslst tuflo tgoodf tstop hdistat1 d0h fcd0h 0000h res mamc sfmc short vshort rtrdes roflo aborte markie flage framee hdimsk1 d2h fcd2h 0000h res mamc sfmc short vshort rtrdes roflo aborte markie flage framee hdtd d4h fcd4h 00xxh res tdata hdrd d6h fcd6h 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 rdata hdrfs1 (d6h) (fcd6h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fbcnt[7C0] hdrfs2 (d6h) (fcd6h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fbcnt[15C8] hdrfs3 (d6h) (fcd6h) 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 fram foflo crce mtch fabort flong fshort hdrdp d8h fcd8h 00xxh stat1a stat0a statnum rthres rdata1 tthres tdata1 rdata hdsfcnt dah fcdah 0000h hsfcnt hdsfcntp dch fcdch 0000h hsfcntp hdmacnt deh fcdeh 0000h hmacnt hdmacntp e0h fce0h 0000h hmacntp hda0 e2h fce2h 0000h ha hda0msk e4h fce4h 0000h hamsk hda1 e6h fce6h 0000h ha hda1msk e8h fce8h 0000h hamsk hda2 eah fceah 0000h ha hda2msk ech fcech 0000h hamsk hda3 eeh fceeh 0000h ha hda3msk f0h fcf0h 0000h hamsk table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc register summary a-6 am186 ?cc/ch/cu microcontrollers users manual general-purpose dma channel 0 registers gd0con0 100h fd00h 0000h st ast tc int res p res ts res dsel ! gd0con1 102h fd02h 0000h sm/io saw sinc dm/io daw dinc gd0srcl 104h fd04h 0000h dsa[15C0] gd0srch 106h fd06h 0000h res dsa[19C16] gd0dstl 108h fd08h 0000h dda[15C0] gd0dsth 10ah fd0ah 0000h res dda[19C16] gd0tc 10ch fd0ch 0000h tc general-purpose dma channel 1 registers gd1con0 110h fd10h 0000h st ast tc int res p res ts res dsel ! gd1con1 112h fd12h 0000h sm/io saw sinc dm/io daw dinc gd1srcl 114h fd14h 0000h dsa[15C0] gd1srch 116h fd16h 0000h res dsa[19C16] gd1dstl 118h fd18h 0000h dda[15C0] gd1dsth 11ah fd1ah 0000h res dda[19C16] gd1tc 11ch fd1ch 0000h tc general-purpose dma channel 2 registers gd2con0 120h fd20h 0000h st ast tc int res p res ts res dsel ! gd2con1 122h fd22h 0000h sm/io saw sinc dm/io daw dinc gd2srcl 124h fd24h 0000h dsa[15C0] gd2srch 126h fd26h 0000h res dsa[19C16] gd2dstl 128h fd28h 0000h dda[15C0] gd2dsth 12ah fd2ah 0000h res dda[19C16] gd2tc 12ch fd2ch 0000h tc general-purpose dma channel 3 registers gd3con0 130h fd30h 0000h st ast tc int res p res ts res dsel ! gd3con1 132h fd32h 0000h sm/io saw sinc dm/io daw dinc gd3srcl 134h fd34h 0000h dsa[15C0] gd3srch 136h fd36h 0000h res dsa[19C16] gd3dstl 138h fd38h 0000h dda[15C0] gd3dsth 13ah fd3ah 0000h res dda[19C16] table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. register summary am186 ?cc/ch/cu microcontrollers users manual a-7 gd3tc 13ch fd3ch 0000h tc smartdma channel pair 0 registers sd0con 140h fd40h 0000h res tepi tbui ttci repi rbui rtci txso rxso p poll res txst rxst sd0trcal 142h fd42h 0000h tra[15C4] res trc sd0trah 144h fd44h 0000h res tra[19C16] sd0rrcal 146h fd46h 0000h rra[15C4] res rrc sd0rrah 148h fd48h 0000h res rra[19C16] sd0stat 14ah fd4ah 0000h res tep tbu ttc rep rbu rtc res sd0cbd 14ch fd4ch 0000h res crbd res ctbd sd0ctad 14eh fd4eh 0000h ctad sd0crad 150h fd50h 0000h crad smartdma channel pair 1 registers sd1con 158h fd58h 0000h res tepi tbui ttci repi rbui rtci txso rxso p poll res txst rxst sd1trcal 15ah fd5ah 0000h tra[15C4] res trc sd1trah 15ch fd5ch 0000h res tra[19C16] sd1rrcal 15eh fd5eh 0000h rra[15C4] res rrc sd1rrah 160h fd60h 0000h res rra[19C16] sd1stat 162h fd62h 0000h res tep tbu ttc rep rbu rtc res sd1cbd 164h fd64h 0000h res crbd res ctbd sd1ctad 166h fd66h 0000h ctad sd1crad 168h fd68h 0000h crad smartdma channel pair 2 registers sd2con 170h fd70h 0000h res tepi tbui ttci repi rbui rtci txso rxso p poll dsel ! txst rxst sd2trcal 172h fd72h 0000h tra[15C4] res trc sd2trah 174h fd74h 0000h res tra[19C16] sd2rrcal 176h fd76h 0000h rra[15C4] res rrc sd2rrah 178h fd78h 0000h res rra[19C16] sd2stat 17ah fd7ah 0000h res tep tbu ttc rep rbu rtc res sd2cbd 17ch fd7ch 0000h res crbd res ctbd sd2ctad 17eh fd7eh 0000h ctad table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc ch cc ch cc cu register summary a-8 am186 ?cc/ch/cu microcontrollers users manual sd2crad 180h fd80h 0000h crad smartdma channel pair 3 registers sd3con 188h fd88h 0000h res tepi tbui ttci repi rbui rtci txso rxso p poll dsel ! txst rxst sd3trcal 18ah fd8ah 0000h tra[15C4] res trc sd3trah 18ch fd8ch 0000h res tra[19C16] sd3rrcal 18eh fd8eh 0000h rra[15C4] res rrc sd3rrah 190h fd90h 0000h res rra[19C16] sd3stat 192h fd92h 0000h res tep tbu ttc rep rbu rtc res sd3cbd 194h fd94h 0000h res crbd res ctbd sd3ctad 196h fd96h 0000h ctad sd3crad 198h fd98h 0000h crad universal serial bus (usb) general configuration registers uistat1 1e0h fde0h 0000h res d_ep_ statint d_ep_ act c_ep_ statint c_ep_ act b_ep_ statint b_ep_ act a_ep_ statint a_ep_ act other_ int int_ep_ act cnt_ep_ new cnt_ep_ act uimask1 1e2h fde2h 0008h res d_ep_ statint d_ep_ act c_ep_ statint c_ep_ act b_ep_ statint b_ep_ act a_ep_ statint a_ep_ act oi_unm int_ep_ act cnt_ep_ new cnt_ep_ act uistat2 1e4h fde4h 0000h usb _ rst usb _ sus usb _ res res tstmp _ mpos _ up sof _ gen ms _ sof uimask2 1e6h fde6h 0000h usb _ rst usb _ sus usb _ res res tstmp _ mpos _ up sof _ gen ms _ sof usbmfr 1e8h fde8h 0008h res pup _ xcver susp s _ res s _ power dis _ xcver rwake rwake _ en rtfmcnt 1eah fdeah 0000h res rtfcnt tstmp 1ech fdech 0000h res tstmp tstmpm 1eeh fdeeh 0000h res tstmpm isctl 1f0h fdf0h 0000h esof _ en res bytes _ sam res bcnt _ lrate sam _ clk _ sel ! fpmcnt 1f2h fdf2h 0000h res fpm_cnt usb control endpoint registers cntctl 200h fe00h 0000h ep_en ep _ not _ stalled not _ flush act _ req new _ command command _ busy res cntsiz 202h fe02h 0000h res rcv_pkt_size cntdat 206h fe06h 00xxh res d cntrpk 208h fe08h 00xxh res d cntdef1 20ah fe0ah 0000h ep_num ep_cfg res ep_int res ep_aset ep _ dir ep_type cntdef2 20ch fe0ch 0008h res fifo_size ep_mx_pct table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc cu cc cu cc cu register summary am186 ?cc/ch/cu microcontrollers users manual a-9 usb interrupt endpoint registers iepctl 210h fe10h 0000h ep_en ep_not_ stalled not_ flush act_ req res iepdat 216h fe16h 00xxh res d iepdef1 21ah fe1ah 1003h ep_num ep_cfg res ep_int res ep_aset ep_dir ep_type iepdef2 21ch fe1ch 0410h res fifo _ size ep _ mx _ pct usb data a endpoint registers aepctl 220h fe20h 0000h ep _ en ep _ not _ stalled not _ flush act _ req stat _ int res not _ zero not _ last _ byte res iso _ start iso _ stop iso _ ms full _ pkt short _ pkt buf _ err other _ err aepsiz 222h fe22h 0000h res rps aepbufs 224h fe24h 0000h res buf_stat aepdat 226h fe26h 00xxh res d arcvpk 228h fe28h 00xxh res d aepdef1 22ah fe2ah 2006h ep_num ep_cfg res ep_int res ep_aset ep_dir ep_type aepdef2 22ch fe2ch 0408h res fifo_ size ep_mx_pct aepdef3 22eh fe2eh 0018h res auto_ rate_en iso_ms_ imsk full_pkt_ imsk shrt _ pkt _ imsk buf_err_ imsk oth_err_ imsk mode iso_ms_ smsk full_pkt_ smsk shrt _ pkt _ smsk buf_err_ smsk oth_err_ smsk usb data b endpoint registers bepctl 230h fe30h 0000h ep _ en ep _ not _ stalled not _ flush act _ req stat _ int res not _ zero not _ last _ byte res iso _ start iso _ stop iso _ ms full _ pkt short _ pkt buf _ err other _ err bepsiz 232h fe32h 0000h res rps bepbufs 234h fe34h 0000h res buf_stat bepdat 236h fe36h 00xxh res d brcvpk 238h fe38h 00xxh res d bepdef1 23ah fe3ah 3006h ep_num ep_cfg res ep_int res ep_aset ep_dir ep_type bepdef2 23ch fe3ch 0408h res fifo_ size ep_mx_pct bepdef3 23eh fe3eh 0018h res auto_ rate_en iso_ms_ imsk full_pkt_ imsk shrt _ pkt _ imsk buf_err_ imsk oth_err_ imsk mode iso_ms_ smsk full_pkt_ smsk shrt _ pkt _ smsk buf_err_ smsk oth_err_ smsk table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc cu cc cu cc cu register summary a-10 am186 ?cc/ch/cu microcontrollers users manual usb data c endpoint registers cepctl 240h fe40h 0000h ep _ en ep _ not _ stalled not _ flush act _ req stat _ int res not _ zero not _ last _ byte res iso _ start iso _ stop iso _ ms full _ pkt short _ pkt buf _ err other _ err cepsiz 242h fe42h 0000h res rps cepbufs 244h fe44h 0000h res buf_stat cepdat 246h fe46h 00xxh res d crcvpk 248h fe48h 00xxh res d cepdef1 24ah fe4ah 4006h ep_num ep_cfg res ep_int res ep_aset ep_dir ep_type cepdef2 24ch fe4ch 0c08h res fifo_size ep_mx_pct cepdef3 24eh fe4eh 0018h res auto_ rate_en iso_ms_ imsk full_pkt_ imsk shrt _ pkt _ imsk buf_err_ imsk oth_err_ imsk mode iso_ms_ smsk full_pkt_ smsk shrt _ pkt _ smsk buf_err_ smsk oth_err_ smsk usb data d endpoint registers depctl 250h fe50h 0000h ep _ en ep _ not _ stalled not _ flush act _ req stat _ int res not _ zero not _ last _ byte res iso _ start iso _ stop iso _ ms full _ pkt short _ pkt buf _ err other _ err depsiz 252h fe52h 0000h res rps depbufs 254h fe54h 0000h res buf_stat depdat 256h fe56h 00xxh res d drcvpk 258h fe58h 00xxh res d depdef1 25ah fe5ah 5006h ep_num ep_cfg res ep_int res ep_aset ep_dir ep_type depdef2 25ch fe5ch 0c08h res fifo_size ep_mx_pct depdef3 25eh fe5eh 0018h res auto_ rate_en iso_ms_ imsk full_pkt_ imsk shrt _ pkt _ imsk buf_err_ imsk oth_err_ imsk mode iso_ms_ smsk full_pkt_ smsk shrt _ pkt _ smsk buf_err_ smsk oth_err_ smsk table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc cu cc cu register summary am186 ?cc/ch/cu microcontrollers users manual a-11 high-speed asynchronous serial port (high-speed uart) registers hspcon0 260h fe60h 0000h res rsie brk ab fc txie rxie tmode rmode evn pen aben d7 stp2 hspcon1 262h fe62h 0000h tfen rfen tflush rflush abaud res men mab2 mab1 mab0 brkval exdwr exdrd xtrn ! hspstat 264h fe64h 0000h rthrsh tthrsh res oerim res match brk ab rdr thre fer oer per temt idled idle hspimsk 266h fe66h 02f8h rthrsh tthrsh res oerim res match brk ab rdr thre fer oer per temt idled idle hsptxd 268h fe68h 0000h res ab tdata hsprxd 26ah fe6ah 0000h rdr thre fer oer per match brk ab rdata hsprxdp 26ch fe6ch 0000h rdr thre fer oer per match brk ab rdata hspbdv 26eh fe6eh 0000h bauddiv hspm0 270h fe70h 0000h mchr1 mchr0 hspm1 272h fe72h 0000h mchr3 mchr2 hspm2 274h fe74h 0000h mchr5 mchr4 hspab0 276h fe76h 0000h abdiv0 abthrsh0 hspab1 278h fe78h 0000h abdiv1 abthrsh1 hspab2 27ah fe7ah 0000h abdiv2 abthrsh2 hspab3 27ch fe7ch 0000h abdiv3 abthrsh3 asynchronous serial port (uart) registers spcon0 280h fe80h 0000h res rsie brk ab fc txie rxie tmode rmode evn pen aben d7 stp2 spcon1 282h fe82h 0000h res brkval exdwr exdrd xtrn ! spstat 284h fe84h 0000h res brk ab rdr thre fer oer per temt idled idle spimsk 286h fe86h 02f8h res brk ab rdr thre fer oer per temt idled idle sptxd 288h fe88h 0000h res ab tdata sprxd 28ah fe8ah 0000h rdr thre fer oer per res brk ab rdata sprxdp 28ch fe8ch 0000h rdr thre fer oer per res brk ab rdata spbdv 28eh fe8eh 0000h bauddiv table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. register summary a-12 am186 ?cc/ch/cu microcontrollers users manual general circuit interface (gci) registers gpcon 2a0h fea0h 0000h res pcmfsc mcarv marq mchen mchsel meomrq icsel gciact brdis gistat 2a2h fea2h 0002h 0102h res ic dclst chgci1 chgci0 mrad mcd mtard meomrd mxba mrda gimsk 2a4h fea4h 0000h res ic dclst chgci1 chgci0 mrad mcd mtard meomrd mxba mrda gtic 2a6h fea6h 0007h res ticen echoen res ticad gictd 2a8h fea8h 00ffh res ic12t gicrd 2aah feaah 0000h res ic12r gicrdp 2ach feach 0000h res ic12p gcitd0 2aeh feaeh 000fh res bar res ci0t gcird0 2b0h feb0h 000fh res ci0r gcird0p 2b2h feb2h 000fh res ci0p gcitd1 2b4h feb4h 003fh res ci1t gcird1 2b6h feb6h 003fh res ci1r gcird1p 2b8h feb8h 003fh res ci1p gmtd 2bah febah 00ffh res mon01t gmrd 2bch febch 0000h res mon01r gmrdp 2beh febeh 0000h res mon01p time slot assigner (tsa) channel a registers tsacon 2c0h fec0h 0000h en res mode ! res fscp drvlvl res esadj tsastart 2c2h fec2h 0000h res bpstart tsastop 2c4h fec4h 0000h res bpstop time slot assigner (tsa) channel b registers tsbcon 2c8h fec8h 0000h en res mode ! res fscp drvlvl res esadj tsbstart 2cah fecah 0000h res bpstart tsbstop 2cch fecch 0000h res bpstop time slot assigner (tsa) channel c registers tsccon 2d0h fed0h 0000h en res mode ! res fscp drvlvl res esadj tscstart 2d2h fed2h 0000h res bpstart tscstop 2d4h fed4h 0000h res bpstop table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc cc ch cc ch cc register summary am186 ?cc/ch/cu microcontrollers users manual a-13 time slot assigner (tsa) channel d registers tsdcon 2d8h fed8h 0000h en res mode ! res fscp drvlvl res esadj tsdstart 2dah fedah 0000h res bpstart tsdstop 2dch fedch 0000h res bpstop synchronous serial interface (ssi) registers ssstat 2f0h fef0h 0000h enhctl res re/te dr/dt pb sscon 2f2h fef2h 0400h res clkp denp res msbf res clkexp res de1 de0 sstxd1 2f4h fef4h 0000h res txdata sstxd0 2f6h fef6h 0000h res txdata ssrxd 2f8h fef8h 0000h res rxdata interrupt controller registers ch0con 300h ff00h 003fh res msk pr ch1con 302h ff02h 000fh res ltm msk pr ch2con 304h ff04h 000fh res src ! ltm msk pr ch3con 306h ff06h 000fh res src ltm msk pr ch4con ! 308h ff08h 003fh res msk pr ch5con ! 30ah ff0ah 003fh res msk pr ch6con ! 30ch ff0ch 003fh res msk pr ch7con ! 30eh ff0eh 003fh res msk pr ch8con 310h ff10h 000fh res src ! ltm msk pr ch9con 312h ff12h 000fh res src ltm msk pr ch10con 314h ff14h 000fh res src ltm msk pr ch11con 316h ff16h 000fh res src ltm msk pr ch12con 318h ff18h 000fh res ltm msk pr ch13con 31ah ff1ah 000fh res ltm msk pr ch14con 31ch ff1ch 001fh res msk pr eoi 320h ff20h 0000h nspec res s poll 322h ff22h 0000h ireq res s pollst 324h ff24h 0000h ireq res s imask 326h ff26h ffffh res ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 primsk 328h ff28h 0007h res prm table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. cc register summary a-14 am186 ?cc/ch/cu microcontrollers users manual inserv 32ah ff2ah 0000h res ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 reqst 32ch ff2ch 0000h res ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 intsts 32eh ff2eh 0000h res dma3 dma2 dma1 dma0 tim2 tim1 tim0 dmahlt 330h ff30h 0000h dhlt res shreq 332h ff32h 0000h pio35 pio34 pio33 pio30 pio29 pio27 pio15 pio5 int7 int6 int5 int4 int3 int2 int1 res shmask 334h ff34h ffffh pio35 pio34 pio33 pio30 pio29 pio27 pio15 pio5 int7 int6 int5 int4 int3 int2 int1 res intpol 336h ff36h ffffh res int8 int7 int6 int5 int4 int3 int2 int1 int0 piopol 338h ff38h ffffh pio35 pio34 pio33 pio30 pio29 pio27 pio15 pio5 res timer registers t0con 340h ff40h 0000h en inh int riu res mc rtg p ext alt cont t0cnt 342h ff42h 0000h tc t0cmpa 344h ff44h 0000h tc t0cmpb 346h ff46h 0000h tc t1con 348h ff48h 0000h en inh int riu res mc rtg p ext alt cont t1cnt 34ah ff4ah 0000h tc t1cmpa 34ch ff4ch 0000h tc t1cmpb 34eh ff4eh 0000h tc t2con 350h ff50h 0000h en inh int res mc res cont t2cnt 352h ff52h 0000h tc t2cmpa 354h ff54h 0000h tc chip select registers umcs 3a0h ffa0h f01bh f03bh res lb res da uden usiz res r2 r1 r0 lmcs 3a2h ffa2h 0f1bh res ub res da lden lsiz res r2 r1 r0 pacs 3a4h ffa4h 0073h ba[19C11] res r3 r2 r1 r0 mmcs 3a6h ffa6h 7fdbh ba[19C13] res mcs0_ only res r2 r1 r0 mpcs 3a8h ffa8h 8183h res m[6C0] res ms omsiz iosiz r3 r2 r1 r0 dram controller registers cdram 3aah ffaah 0000h res rc edram 3ach ffach 0000h en res t table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. register summary am186 ?cc/ch/cu microcontrollers users manual a-15 programmable i/o (pio) registers piomode0 3c0h ffc0h 0000h pmode 15 pmode 14 pmode 13 pmode 12 pmode 11 pmode 10 pmode 9 pmode 8 pmode 7 pmode 6 pmode 5 pmode 4 pmode 3 pmode 2 pmode 1 pmode 0 piodir0 3c2h ffc2h 1effh pdir15 pdir14 pdir13 pdir12 pdir11 pdir10 pdir9 pdir8 pdir7 pdir6 pdir5 pdir4 pdir3 pdir2 pdir1 pdir0 piodata0 3c4h ffc4h ????h pdata15 pdata14 pdata13 pdata12 pdata11 pdata10 pdata9 pdata8 pdata7 pdata6 pdata5 pdata4 pdata3 pdata2 pdata1 pdata0 pioset0 3c6h ffc6h 0000h pset15 pset14 pset13 pset12 pset11 pset10 pset9 pset8 pset7 pset6 pset5 pset4 pset3 pset2 pset1 pset0 pioclr0 3c8h ffc8h 0000h pclr15 pclr14 pclr13 pclr12 pclr11 pclr10 pclr9 pclr8 pclr7 pclr6 pclr5 pclr4 pclr3 pclr2 pclr1 pclr0 piomode1 3cah ffcah 0000h pmode 31 pmode 30 pmode 29 pmode 28 pmode 27 pmode 26 pmode 25 pmode 24 pmode 23 pmode 22 pmode 21 pmode 20 pmode 19 pmode 18 pmode 17 pmode 16 piodir1 3cch ffcch 9fffh pdir31 pdir30 pdir29 pdir28 pdir27 pdir26 pdir25 pdir24 pdir23 pdir22 pdir21 pdir20 pdir19 pdir18 pdir17 pdir16 piodata1 3ceh ffceh ????h pdata31 pdata30 pdata29 pdata28 pdata27 pdata26 pdata25 pdata24 pdata23 pdata22 pdata21 pdata20 pdata19 pdata18 pdata17 pdata16 pioset1 3d0h ffd0h 0000h pset31 pset30 pset29 pset28 pset27 pset26 pset25 pset24 pset23 pset22 pset21 pset20 pset19 pset18 pset17 pset16 pioclr1 3d2h ffd2h 0000h pclr31 pclr30 pclr29 pclr28 pclr27 pclr26 pclr25 pclr24 pclr23 pclr22 pclr21 pclr20 pclr19 pclr18 pclr17 pclr16 piomode2 3d4h ffd4h 0000h pmode 47 pmode 46 pmode 45 pmode 44 pmode 43 pmode 42 pmode 41 pmode 40 pmode 39 pmode 38 pmode 37 pmode 36 pmode 35 pmode 34 pmode 33 pmode 32 piodir2 3d6h ffd6h fff1h pdir47 pdir46 pdir45 pdir44 pdir43 pdir42 pdir41 pdir40 pdir39 pdir38 pdir37 pdir36 pdir35 pdir34 pdir33 pdir32 piodata2 3d8h ffd8h ????h pdata47 pdata46 pdata45 pdata44 pdata43 pdata42 pdata41 pdata40 pdata39 pdata38 pdata37 pdata36 pdata35 pdata34 pdata33 pdata32 pioset2 3dah ffdah 0000h pset47 pset46 pset45 pset44 pset43 pset42 pset41 pset40 pset39 pset38 pset37 pset36 pset35 pset34 pset33 pset32 pioclr2 3dch ffdch 0000h pclr47 pclr46 pclr45 pclr44 pclr43 pclr42 pclr41 pclr40 pclr39 pclr38 pclr37 pclr36 pclr35 pclr34 pclr33 pclr32 reset configuration register rescon 3deh ffdeh ????h rcd15 rcd14 rcd13 rcd12 rcd11 rcd10 rcd9 rcd8 rcd7 rcd6 rcd5 rcd4 rcd3 rcd2 rcd1 rcd0 watchdog timer register wdtcon 3e0h ffe0h c180h ena wrst rstflag nmiflag res exrst es miscellaneous registers syscon 3f0h fff0h 0000h res dsden pwd dismem disio itf4 ! exsync ! res disclk res prl 3f4h fff4h 4001h prl reloc 3feh fffeh 20fch dual res m/io r[19C10] res table a-1 am186cc/ch/cu microcontrollers register summary (continued) name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset default location default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ! = see the register or bit description in the am186?cc/ch/cu microcontrollers register set manual, order #21916, for controller-specific details. register summary a-16 am186?cc/ch/cu microcontrollers users manual am186?cc/ch/cu microcontrollers users manual glossary-1 glossary a a bus nonmultiplexed address bus. ack acknowledgment. ad bus multiplexed address and data bus. adccp advanced data communication control procedures. adsl asymmetrical digital subscriber line. see dsl. ansi american national standards institute. asynchronous pertaining to two or more processes that do not depend on the occurrence of specific events such as common timing signals. asynchronous transmission data transmission in which each information character is individually synchronized (usually by the use of start and stop elements). compare to synchronous transmis- sion and isochronous transmission. at interface a method of communicating with and controlling modems. developed by hayes microcomputer prod- ucts, the at command set has become a de facto standard most modems are designed to use. b bit stuffing adding bits to a transmitted message to round out a fixed frame or to break up a pattern of data bits that could be misconstrued as control codes. also called zero-bit insertion. compare to bit unstuffing. bit unstuffing deleting bits from a received message to remove any bits added to round out a fixed frame or to break up a pattern of data bits that could be misconstrued as con- trol codes. also called zero-bit deletion. compare to bit stuffing. break during serial communications, a constant low signal on the receive data line for one frame time or greater. in the am186cc/ch/cu microcontrollers, this is reported as a zero character with the framing error (fer) and break (brk) status bits set in the (h)spstat register. bri basic rate interface. buffer (1) a routine or storage space used to compensate for a difference in rate of data flow, or time of occurrence of events, when transferring data from one device to another. (2) a portion of storage space used to tempo- rarily hold input or output data. buffer queue a block of memory to which data is written or from which data is read during a dma transfer. software specifies the length and base address of the buffer queue. the dma transfer writes data to each byte or word of the buffer queue until it reaches the end of the transfer or the end of the buffer queue. compare to circular buffer. buffer descriptor ring see descriptor ring. bulk transfer a nonperiodic data transmission process that typically consists of large bursts of information. bulk transmis- sion is typically used for a transfer that can use any available bandwidth and also can be delayed until band- width is available. byte a group of eight adjacent binary digits (bits). c ccit international telegraph and telephone consultative committee. circular buffer a block of memory to which data is written or from which data is read during a dma transfer. software specifies the length and base address of the circular buffer. the dma transfer writes data to or reads data from each byte or word of the circular buffer. if the transfer reaches the end of the buffer, the dma control hardware points glossary glossary-2 am186?cc/ch/cu microcontrollers users manual back to the beginning of the buffer and continues writing or reading data. sometimes called a ring buffer. com- pare to buffer queue. co central office. codec coder-decoder. also referred to as a compressor- decompressor. any technology used to encode (or com- press) and decode (or decompress) data, which can be done with hardware, software, or any combination of the two. typically used for digital audio or video data streams. control endpoint a usb endpoint used to transfer usb commands and device configuration data between the host and device. the control endpoint is common to, and is required by, all usb device class specifications. the control end- point features are not programmable. compare to interrupt endpoint and data endpoint . cpu central processing unit. the control unit or micropro- cessor of a computer system. crc cyclic redundancy check. a check performed on data to see if an error has occurred in transmitting, reading, or writing the data. the result of a crc is typically stored or transmitted with the checked data. the stored or transmitted result is compared to a crc value calcu- lated for the data to determine if an error has occurred. ctr clear to receive. cts/rtr clear-to-send/ready-to-receive. a symmetrical interface between two serial ports that provides hardware flow control when both ports are sending and receiving data. the cts signal of each port is connected to the rtr signal of the other port. when the transmitter sends a cts signal and the receiver sends a rtr signal, data can be transferred from the transmitter to the receiver between the ports. d data endpoint a usb endpoint used to transfer data from the host to the device, or vice versa. each data endpoint is individ- ually programmable as to direction (in or out relative to the host), transfer type (bulk, isochronous, or inter- rupt), and maximum packet size. compare to control endpoint and interrupt endpoint . data transparency a data stream that happens to contain a data sequence that is the same as a flag, mark, or abort sequence is disguised during transmission so it is not misconstrued as an actual flag, mark, or abort. see also bit stuffing and bit unstuffing. dce data communications equipment. any device that con- nects a computer to a network, such as a modem. see also raw dce. default address an address defined by the usb specification and used by a usb device when it is first powered on or reset. the default address is 00h. descriptor ring a block of memory that the cpu and software use to control and describe data buffers. destination-synchronized transfer see synchronized transfer. device see usb device. device address the address of a device on the usb. the device address is the default address when the usb device is first powered on or reset. hubs and functions are assigned a unique device address by usb software. dma direct memory access. a means of transferring data from a source (a device or block of memory) directly to a destination (also a device or block of memory) without passing the information through the processor. see also general-purpose dma and smartdma channel . dma latency the time period between the dma request generation and the actual running of the bus cycles associated with the dma transfer. see also latency, interrupt latency, and hold latency. dma mode one of three modes supported by the am186cc/ch/ cu microcontrollers for serial communications. in dma mode, software programs the dma transfer registers, then the dma hardware performs the entire transfer with no software intervention except for error-handling. compare to polled mode and interrupt mode . dma transfer a unit of work involving the transferring of data into or out of memory using dma capabilities. glossary am186?cc/ch/cu microcontrollers users manual glossary-3 dram dynamic random access memory. a type of computer memory that employs a system of transistors and capacitors to retain data. dram is slower and less dependable than static ram because the capacitors cannot maintain an electrical charge and need to be refreshed every millisecond, but it is cheaper, takes up less space, and uses less power. compare to sram. dsl digital subscriber line. a modem technology that increases the digital speed of ordinary telephone lines by a substantial factor over common v.34 (33600 bps) modems. dsl modems may provide symmetrical or asymmetrical (adsl) operation. asymmetrical provides faster downstream speeds and is suited for internet usage and video on demand, where the heaviest trans- mission requirement is from the provider to the customer. dsl uses packet switching technology that operates independently from the voice telephone system. this allows the telephone companies to provide digital ser- vice and not lock up voice circuits for long calls. because of this, dsl is not as well suited to videocon- ferencing as is isdn. isdn is circuit switched, which keeps the line open and connected throughout the session. dte data terminal equipment. a hardware component con- nected to some type of communications device. a pc is a piece of data terminal equipment; a modem is a com- munications device. duplex the ability of a serial communications connection to transmit data in both directions. see also half duplex and full duplex . compare to simplex . e edo extended data out. endpoint see usb endpoint. endpoint address the combination of a device address and an endpoint number on a usb device. endpoint number a unique pipe endpoint on a usb device. eom end of message. even parity se e parity. external reset the reset of the am186cc/ch/cu microcontrollers ini- tiated by asserting the res signal. also called a power- on reset. compare to internal reset and system reset. f fcs frame check sequence. the fcs contains the gener- ated crc code for the frame being transmitted. all data transmitted between the opening and closing flags (excluding inserted 0s) is included in the crc calcula- tion. the transmitter appends the calculated crc to the end of the frame just before the closing flag. fifo first in first out. (1) describes a method of processing data in the order in which it is received. (2) a block of memory or other storage used as a first-in-first-out buffer. fifo high-water mark see fifo threshold . fifo threshold a system-dependent, software threshold value that indi- cates action should be taken so data is not lost from the fifo buffer. fly-by-transfer during a smartdma channel transfer, the read and write operations execute in a single bus cycle, instead of the two cycles required during a general-purpose dma transfer. frame the unit of information transferred across a data link. typically, there are control frames for link management and information frames for the transfer of message data. frame synchronization (frame sync) during an hdlc transfer, the process of signaling the beginning of the frame with a start flag and the end of the frame with a stop flag. framing error in asynchronous serial communication, a condition resulting from the receiver losing bit count alignment with the transmitter. in this situation, if the last bit of a unit (a frame) is a zero, the receiver may read that bit as the start bit of the next frame, thus the term framing error. full duplex the ability of a serial communications connection to transmit data in both directions at the same time. see also duplex and simplex. compare to half duplex. glossary glossary-4 am186?cc/ch/cu microcontrollers users manual g gci general circuit interface, also called iom-2. one of the external interfaces supported by the am186cc commu- nications controller hdlc channels. gci is an interface specification developed jointly by alcatel, italtel, gpt, and siemens. this specification defines an industry standard serial bus for interconnecting telecommunica- tions integrated circuits. the standard covers linecard, nt1, and terminal architectures for integrated services digital network (isdn) applications. the am186cc communications controller supports the terminal ver- sion of gci. gci on the am186cc communications controller supports polled and interrupt modes, but does not support dma mode. see iom-2. general-purpose dma the term used to describe standard or typical dma pro- cessing as opposed to dma processing using the smartdma channels in the am186cc/ch/cu micro- controllers. see also dma and smartdma. h half duplex the ability of a serial communications connection to transmit data in both directions, but not at the same time. compare to full duplex. hardware interrupt any one of the maskable interrupts, or an nmi or watch- dog timer interrupt. when a hardware interrupt is generated, the if flag is cleared unless in polled mode. compare to software interrupt. hdlc high-level data link control. a very common bit-oriented data link protocol (osi layer 2) issued by iso. similar protocols are adccp, lap-b, and sdlc. the am186cc communications controller provides four hdlc channels. the hdlc channels support full- duplex transfers in polled, interrupt, and dma modes. hold latency the time between a hold request and the hold acknowledge. host the host computer system where the usb host control- ler is installed. this includes the host hardware platform (cpu, bus, etc.) and the operating system in use. i ice in-circuit emulator. a device for testing and program- ming an integrated circuit outside of any actual system in which the device will be used. internal peripherals components on a microcontroller integrated circuit other than the embedded cpu that provide control over some specific function. on the am186cc/ch/cu microcontrollers, internal peripherals would include but not be limited to the hdlc controller, the dma control- ler, the usb peripheral controller, and the dram controller. for lists of the internal peripherals in the am186cc/ch/cu microcontrollers, see features on page 1-1. internal reset the reset of the am186cc communications controller initiated by the watchdog timer. compare to external reset and system reset. interrupt a command or signal that tells the processor to stop what it is doing and wait for further instruction. the inter- rupt may require the processor to suspend its current job and perform another function that is more pressing. interrupt channel the group of logic that is comprised of a control register, an in-service bit, a request bit, and a mask bit. the inter- rupt channel controls the behavior of a maskable interrupt. interrupt endpoint a usb endpoint used for small data transfers that in the past have been interrupt-driven. the interrupt endpoint is polled at a regular programmable interval to allow the device to transfer interrupt data such as event notifica- tion, keyboard characters, and pointing device coordinates to the host. compare to control endpoint and data endpoint . interrupt latency the time period between an interrupt request and the servicing of the interrupt. see also latency , dma latency, and hold latency . interrupt mode one of three modes supported by the am186cc com- munications controller for serial communications. in interrupt mode, software performs other tasks until an interrupt tells it to service a serial channel. compare to dma mode and polled mode . interrupt source any source (internal or external) that can request an interrupt. this can be a physical pin, or an on-chip peripheral. glossary am186?cc/ch/cu microcontrollers users manual glossary-5 interrupt transfer one of four usb transfer types. interrupt transfers have the following characteristics: small data, nonperiodic, low frequency, and bounded latency. they are device- initiated communications typically used to notify the host of device service needs. interrupt type an eight-bit number assigned to each discrete interrupt (see table 7-3 on page 7-12). each interrupt type does not need a unique interrupt channel; one interrupt chan- nel can support more than one interrupt type. however, if two interrupt types are supported by one channel, then those two types have the same level of program- mable priority. interrupt vector address equals the interrupt type times four and is the location in the interrupt vector table that stores the address of the interrupt service routine for each interrupt type. interrupt vector table a memory area of 1 kbyte beginning at address 00h that contains up to 256 four-byte interrupt vector addresses. iom-2 isdn-oriented modular interface, revision 2. see gci. isdn integrated services digital network. a telecommunica- tions network that allows for digital voice, video, and data transmissions. isdn replaces the analog tele- phone system with a fast and efficient digital communications network. isdn lines contain two chan- nels: a b channel, which has a 64-kbit/s data transmission rate, and a d channel, which has either a 16-kbit/s or 64-kbit/s transmission rate. when the two lines are used together, transmitted data can travel at 128 kbit/s. isochronous transmission a data transmission process in which there is always an integral number of unit intervals between any two signif- icant instants. compare to synchronous transmission and asynchronous transmission. isochronous transfer one of four usb transfer types. isochronous transfers are used when working with isochronous data. isochro- nous transfers provide periodic, continuous communication between host and device. isr interrupt service routine. the software executed when the interrupt processing unit receives an interrupt request. the interrupt vector points to this code. l lance local area network controller for ethernet. lap-b link access procedure, balanced. lap-d link access procedure, d channel. latency a time period for an event to cause another event. see also interrupt latency , dma latency , and hold latency. lsb least significant bit. m maskable interrupt an interrupt that can be enabled (unmasked) or dis- abled (masked) by setting or clearing a bit in the appropriate mask register. maskable interrupts as a group are enabled and disabled by setting or clearing the interrupt-enable flag (if) in the processor status flags (flags) register. nonmaskable interrupts are not affected by this bit setting. message pipe a pipe that transfers data using a request/data/status paradigm. the data has an imposed structure that allows requests to be reliably identified and communicated. msb most significant bit. multidrop a communication configuration in which more than two stations share a transmission path. a typical multidrop configuration has a number of secondary devices (e.g., terminals) and a primary device (e.g., host computer) on the same path or line. multiplexed mode the connection of an hdlc channel to an external interface through a tsa. in multiplexed mode, an hdlc channel can be connected to a pcm highway or gci interface. compare to nonmultiplexed mode. multiplexed signal a signal that shares a pin with at least one other signal. multipoint see multidrop. mux abbreviation for multiplexer. glossary glossary-6 am186?cc/ch/cu microcontrollers users manual n nack negative acknowledgment. nibble half a byte (four bits). nmi nonmaskable interrupt. an interrupt that cannot be dis- abled (masked). nonmultiplexed mode the connection of an hdlc channel directly to an exter- nal interface without going through a tsa. in nonmultiplexed mode, an hdlc channel can be con- nected to a raw dce interface. compare to multiplexed mode. nrz non-return to zero. nrzi non-return to zero, inverted. o odd parity see parity. once on-circuit emulation. osi open systems interconnection. an iso standard for worldwide communications that defines a framework for implementing protocols in seven layers. control is passed from one layer to the next. overall priority each interrupt source has an overall priority number that is used only to arbitrate between two interrupt sources that have priority requests pending with the same programmable priority level. overall priority is not used if the programmable priority is sufficient to resolve the pending highest-priority request. p pabx private automatic branch exchange. packet a self-contained message unit transmitted through a communications network. typically, the transmitter breaks a longer message into packets to avoid the net- work performance degradation caused by long messages. a packet contains three parts: control infor- mation (source, destination address, length), the data to be transmitted, and error detection and correction bits. a packet may be made up of one or more frames. packet buffer the logical buffer used by a usb device for sending or receiving a single packet. this determines the maxi- mum packet size the device can send or receive. packet id a field in a usb packet that indicates the type of packet, and by inference the format of the packet and the type of error detection applied to the packet. parity an error-checking procedure for checking the accuracy of serial data streams based on whether the number of 1 bits is even or odd. a parity bit is added to each group of data bits in a transmission. in even parity , the parity bit is set to 1 whenever it is needed to bring the total number of 1 bits to an even number. in odd parity , the parity bit is set to 1 whenever it is needed to bring the total number of 1 bits to an odd number. pcb peripheral control block. each 16-bit read/write periph- eral register is in the internal 1-kbyte peripheral control block (pcb). registers are physically located in the peripheral devices they control, but they are addressed as a single 1-kbyte block. this block is located in either memory or i/o space, at the location pointed to by the peripheral control block relocation (reloc) register. because the base address of the block can change, the address of each register is specified as an offset from the reloc register, rather than as an absolute address. the register address is found by adding the offset to the base address to determine the physical location in memory or i/o space. the pcb base address can be set to any even 1-kbyte boundary in memory or i/o space (i.e., the lower 10 bits of the base address must be 0). the reloc register resides in the last register address of the pcb, at offset 03feh. at reset, the base of the pcb is set to fc00h in i/o space. this places the reloc register at fffeh. pcm pulse code modulation. a technique for converting ana- log signals into digital form that is widely used by the telephone companies in their t1 circuits. in north amer- ica and japan, pcm samples the analog waves 8,000 times per second and converts each sample into an 8- bit number, resulting in a 64-kbit/s data stream. the sampling rate is twice the 4-khz bandwidth required for a toll-quality conversation. pcm highway pulse code modulation highway. one of the external interfaces supported by the am186cc communications controller hdlc channels. glossary am186?cc/ch/cu microcontrollers users manual glossary-7 pin refers to a physical wire on a chip which is available externally. compare to signal. pinstrap a pinstrap is used to enable or disable features based on the state of the pin during an external reset. the pin- strap must be held in its desired state for at least 4.5 clock cycles after the deassertion of the res signal. note that the pinstraps are sampled in an external reset only (when the res signal is asserted) not during an internal watchdog-timer generated reset. pio programmable input/output. physical pins on the am186cc communications controller that can be used for any purpose the system designer requires. the sig- nal on a pio pin can be sampled through a register and can be driven high or low by setting or clearing the associated bit in the appropriate register. pipe a logical abstraction representing the association between an endpoint on a usb device and software on the host. a pipe has several attributes; for example, a pipe may transfer data as streams (stream pipe) or mes- sages (message pipe). polled mode one of three modes supported by the am186cc com- munications controller for serial communications. in polled mode, software reads a status register in a loop, and reads received data or transmits data depending on the status register indicator bits. compare to interrupt mode and dma mode. port point of access to or from a system or circuit. for usb, the point where a usb device is attached. pots plain old telephone service. power-on reset see external reset. ppp point to point protocol. pri primary rate interface. programmable priority each interrupt channel has eight levels of programma- ble priority that are set in the channels control register. programmable priority determines which interrupt to service when two interrupts are requested at the same time. an interrupt service routine is interrupted by another interrupt request of equal or higher programma- ble priority, as long as the interrupt-enable flag (if) in the processor status flags (flags) register is set. for more information about setting the flags register, see the am186?cc/ch/cu microcontrollers register set manual , order #21916. if the programmable priority lev- els are equal, the overall priority number is used. pwd pulse width demodulation. r raw dce one of the external interfaces supported by the am186cc communications controller hdlc channels. raw dce is a synchronous serial bus generally used in modem and other high-speed serial applications. raw dce runs at up to 10 mbit/s. the am186cc communi- cations controller implementation requires transmit (tclk) and receive (rclk) clock inputs, and has receive data (rxd), transmit data (txd), and the clear- to-send (cts) and ready-to-receive (rtr) flow con- trol signals. receiver the portion of logic for an hdlc channel, smartdma channel, or uart that processes information coming into the am186cc communications controller. reset see external reset , internal reset , and system reset. ring buffer see circular buffer. router the part of a communications network that receives transmissions and forwards them to their destinations using the shortest route available. data may travel through multiple routers on the way to their destination. rtr ready-to-receive. see cts/rtr. rts ready-to-send. s scit special circuit interface for terminals. sdlc synchronous data link control. a data transmission pro- tocol used by networks using systems network architecture (a communications format, advanced by ibm, used on local-area networks to allow multiple sys- tems access to centralized data). sdlc defines the format used to transmit the data traveling over network lines. glossary glossary-8 am186?cc/ch/cu microcontrollers users manual short frame during an hdlc transfer, a frame containing a number of bytes between the start and stop flags that is less than the minimum length specified in the minrl bit field of the hxrcon0 register. signal refers to the electrical signal that flows across a pin. compare to pin. simplex the ability of a serial communications connection to transmit data in one direction only. compare to duplex. slic subscriber line interface circuit. slac? subscriber line audio-processing circuit. smartdma? channel an amd proprietary technique for increasing the perfor- mance of dma transfers. smartdma channels provide a method for the transmission and reception of data across multiple memory buffers and a sophisticated buffer-chaining mechanism. these channels are always used in pairs: transmitter and receiver. the transmit channels can only transfer data from memory to a peripheral; the receive channels can only transfer data from a peripheral to memory. see also dma and gen- eral-purpose dma. soho small office/home office. sram static random access memory. a type of semiconductor memory that preserves stored information as long as there is enough power flow to keep the device running. sram does not need refreshing like dram. sram is faster and more dependable, but also is more expen- sive, takes up more space, and uses more power than dram. software exception a software interrupt that occurs when an instruction causes a particular condition in the processor. software interrupt an interrupt initiated by the int or into software instruction, or by a software exception. a software inter- rupt does not affect the if flag in the flags register. compare to hardware interrupt. source-synchronized transfer see synchronized transfer. ssi synchronous serial interface. an amd proprietary tech- nology for providing half-duplex, bidirectional data transfers at transfer rates of up to 25 mbit/s with a 50-mhz cpu clock. the ssi supports only polled mode, not interrupt or dma modes. stream pipe a pipe that transfers data as a stream of samples with no defined usb structure. synchronization type a classification that characterizes an isochronous end- point's capability to connect to other isochronous endpoints. synchronized transfer a transfer of information in which the transmitter and receiver coordinate their operations with a clock signal or some other technique so the receiver knows when the next piece of information is available from the trans- mitter. in dma operations, a synchronized transfer takes place when either the source of the data (source- synchronized) or the destination of the data (destina- tion-synchronized) generates a drq to request the transfer. compare to unsynchronized transfer. synchronous transmission data transmission in which the time of occurrence of each signal representing a bit is related to a fixed time frame. typically, the transmitter sends a clock signal along with the data so the receiver knows when to receive each bit. compare to asynchronous transmis- sion and isochronous transmission. system reset the reset of the am186cc/ch/cu microcontrollers (the cpu plus the internal peripherals) as well as any exter- nal peripherals connected to the resout pin. an external reset always causes a system reset; an internal reset can optionally cause a system reset. compare to internal reset and external reset. t tdm time-division multiplex. a method of transmitting multi- ple signals (data, voice, and/or video) simultaneously over one communications medium by interleaving a piece of each signal one after another. tic terminal interchip communication. top of fifo the memory address or register where the next item in a first-in-first-out buffer can be read. glossary am186?cc/ch/cu microcontrollers users manual glossary-9 trace interrupt the trace interrupt is the highest priority interrupt. it is a software interrupt in that it is initiated by software, but unlike other software interrupts, it does clears the if flag. transparency see data transparency. transparent mode a mode of operation for an hdlc transmit channel that transmits the data exactly as it appears in the fifo. transparent mode does no bit stuffing, no framing with flags, and does not support crc. transparent mode is useful for transmitting raw data streams such as audio data (for use with a codec or dsp). transaction the delivery of service to an endpoint. a transaction consists of a token packet, an optional data packet, and an optional handshake packet. specific packets are allowed or required based on the transaction type. transceiver a transmitter/receiver that can send and accept information. transfer one or more bus transactions to move information between a software client and its function. transfer type determines the characteristics of the data flow between a software client and its function. four usb transfer types are defined: control, interrupt, bulk, and isochronous. transmitter the portion of logic for an hdlc channel or smartdma channel that sends information out from the am186cc/ ch/cu microcontrollers. tsa time-slot assigner. the portion of logic in an hdlc channel that directs data from the hdlc channel to an external communication interface or vice versa. a tsas main function is to allow the transmission and reception of data to and from an individual hdlc by providing the appropriate hdlc clock and clock enable signals dur- ing its programmed time slot within an 8-khz frame. the am186cc/ch/cu microcontrollers support the follow- ing external interfaces: raw dce and pcm highway. in addition, the am186cc communications controller sup- ports gci. u uart universal asynchronous receiver/transmitter. a device that provides full-duplex, bidirectional data transfer in rs-232 format. the am186cc/ch/cu microcontrollers have a uart that supports speeds up to 115.2 kbaud and a high-speed uart that supports speeds up to 460 kbaud. the uarts support full-duplex transfers in polled, interrupt, and dma modes. unsynchronized transfer a transfer of information in which the transmitter sends data without regard for any signal or other indication from the receiver. during an unsynchronized transfer in dma operations, drq is always asserted; and the transfer takes place continually until the correct number of transfers occur. compare to synchronized transfer. usb universal serial bus. usb is an industry standard exten- sion to the pc architecture that provides an easy-to-use port for connecting up to 127 peripheral devices at transfer rates up to 12 mbit/s. the usb specification supports isochronous (real-time) data transfers for voice, audio, and compressed video; bulk data transfers for devices such as printers and terminal adapters; and interrupt data transfers for event-driven devices such as pointing devices and keyboards. the usb portion of the am186cc and am186cu microcontrollers supports half-duplex transfers in polled, interrupt, and dma modes. usb device a logical or physical entity that performs a function. the actual entity described depends on the context of the reference. at the lowest level, the term device may refer to a single hardware component, as in a memory device. at a higher level, it may refer to a collection of hardware components that perform a particular func- tion, such as a usb interface device. at an even higher level, the term device may refer to the function per- formed by an entity attached to the usb; for example, a data/fax modem device. devices may be physical, electrical, addressable, and logical. usb endpoint a uniquely identifiable portion of a usb device that is the source or sink of information in a communication flow between the host and device. each endpoint is sup- ported by a first-in-first-out buffer (fifo). the fifo is a temporary storage location for the data that is passed between the microcontrollers cpu or memory bus and the integrated usb peripheral controller. see also con- trol endpoint , data endpoint , and interrupt endpoint . glossary glossary-10 am186?cc/ch/cu microcontrollers users manual v very short frame during an hdlc transfer, a frame containing less than two bytes (zero or one) between the start and stop flags. w wait state a pause in a microprocessors clock cycles that allows for differences in speed between one component and others in a computer (such as input/output devices or ram). wait states are common in systems where the microprocessor has a much higher clock speed than other components, requiring the latter to play catch up. during a wait state, the microprocessor idles for one or more cycles while data comes in from ram or other components. wait states also are not uncommon between buses and devices connected to the bus. wan wide area network. word in the x86 environment, a group of 16 adjacent binary digits (bits) or two bytes. z zero-bit deletion see bit unstuffing. zero-bit insertion see bit stuffing. am186?cc/ch/cu microcontrollers users manual index-1 index numerics 32-channel linecard application, 1-15 a a bus, definition, glossary-1 a19Ca0 signals description, 3-10 emulator support, 4-2 ack, definition, glossary-1 acknowledge dma, 8-10 interrupt, 7-10 activation, gci, 17-10 ad bus, definition, glossary-1 ad15Cad0 signals description, 3-10 emulator support, 4-2 adccp, definition, glossary-1 adding data buffers, 8-32, 8-34 address generation, 2-5, 2-6 multiplexing, dram, 6-4 address and data bus (ad15Cad0) description, 3-10 address bit, uart, 13-9, 13-10 address bus configuring chip select, 5-9 description, 3-10, 3-13 overview, 3-30 addressing mode, 2-9, 2-10 aden signal description, 3-7 emulator support, 4-2 adsl, definition, glossary-1 aepbufs register, 18-8 aepctl register, 18-8 aepdat register, 18-8 aepdef1 register, 18-8 aepdef2 register, 18-9 aepdef3 register, 18-9 aepsiz register, 18-8 ale signal description, 3-10 emulator support, 4-3 am186cc microcontroller, block diagram, 1-5 am186cc/ch/cc microcontroller block diagrams, 1-4 clocks, 3-33 dma channel use, 8-8, 8-9 embedded cpu overview, 1-6 signal description table, 3-10 am186ch hdlc microcontroller, block diagram, 1-5 am186cu usb microcontroller, block diagram, 1-5 ansi, definition, glossary-1 application basic-rate gci with isdn, 16-10 gci, 17-8 gci-pcm highway conversion, 12-5 isdn, 12-5 isdn-to-ethernet low-end router, 1-14 linecard, 1-15, 12-4 overview, 1-13 pcm highway, 16-11 serial communication overview, 12-3 synchronous serial interface, 14-3 arbitration, gci d-channel, 17-17 architectural overview, 1-6 arcvpk register, 18-8 ardy signal description, 3-10 emulator support, 4-3 array bounds exception interrupt, 7-20 asynchronous communications high-speed uart signal descriptions, 3-22 overview, 12-6 uart signal descriptions, 3-22 asynchronous serial interface. see uart. asynchronous transmission, definition, glossary-1 asynchronous, definition, glossary-1 at interface, definition, glossary-1 autobaud. see baud rate, detection. index index-2 am186?cc/ch/cu microcontrollers users manual b basic-rate gci, 16-10 baud rate detection description, 13-16 enhancement, 13-18 error, 13-17 procedure, 13-7 range, 13-17 programming, 13-15 setting, 13-6 table, uart, 13-15 bepbufs register, 18-9 bepctl register, 18-9 bepdat register, 18-9 bepdef1 register, 18-9 bepdef2 register, 18-9 bepdef3 register, 18-9 bepsiz register, 18-9 bhe signal description, 3-11 emulator support, 4-2, 4-3 bit sampling, uart, 13-16 bit stuffing, definition, glossary-1 bit unstuffing, definition, glossary-1 block diagram am186cc microcontroller, 1-5 am186cc/ch/cu microcontrollers, 1-4 am186ch hdlc microcontroller, 1-5 am186cu usb microcontroller, 1-5 chip select, 5-2 dma, 8-3 dram, 6-2 gci, 17-1 hdlc, 15-2 hdlc receiver, 15-15 hdlc transmitter, 15-10 interrupt, 7-2 interrupt (partial), 7-15 maskable interrupt, 7-15 programmable i/o, 9-1 synchronous serial interface, 14-1 tsa, 16-3 typical system, 3-29 uart, 13-2 usb, 18-2 watchdog timer, 11-1 bounds exception interrupt, 7-20 brcvpk register, 18-9 break detection and generation, uart, 13-20 break, definition, glossary-1 breakpoint interrupt, 7-19 bri, definition, glossary-1 bsize8 signal description, 3-11 emulator support, 4-3 buffer adding, 8-32, 8-34 descriptor ring, creating, 8-31, 8-33 descriptor ring, definition, glossary-1 queues, using, 8-20 replacing, 8-35 buffer queue, definition, glossary-1 buffer, definition, glossary-1 bulk transfer, definition, glossary-1 bus address bus description, 3-10, 3-13 bus status pins, 3-13 data. see data bus. gci. see gci bus. system. see system bus. bus interface, signal list, 3-10 byte transfers, dma, 8-15 byte write enables, 3-31 byte, definition, glossary-1 c c/i channel, gci, 17-15 c/i0 arbitration, gci, 17-18 cas1 Ccas0 signals description, 3-19 emulator support, 4-3 ccit, definition, glossary-1 cdram register, 6-3 cepbufs register, 18-9 cepctl register, 18-9 cepdat register, 18-9 cepdef1 register, 18-9 cepdef2 register, 18-9 cepdef3 register, 18-9 cepsiz register, 18-9 chip select block diagram, 5-2 comparison to other devices, 5-11 configuring address and data buses, 5-9 dram signal functions, 5-7 hardware considerations, 5-10 i/o space, 5-7 i/o, selecting, 5-5 initialization, 5-11 lcs signal, 5-5 mcs3 Cmcs0 signals, 5-5 memory space, 5-6 memory, selecting, 5-5 multiplexed signals, 5-3 index am186?cc/ch/cu microcontrollers users manual index-3 operation, 5-4 overlapping, 5-8 overlapping pcs with dram, 6-5 overview, 1-12 pcs, 5-9 pcs7 Cpcs0 signals, 5-6 ranges and dram configuration, 3-10, 3-19 ready signal programming, 5-10 registers, 5-3 selecting dram, 5-7 signal descriptions, 3-17 software considerations, 5-10 system design, 5-2 timing, 5-10 ucs signal, 5-5 usage, 5-4 wait state programming, 5-10 chxcon register, 7-5 circular buffer definition, glossary-1 small or misaligned, 8-25 using, 8-20, 8-23 clearing pio data, 9-6 clkout signal description, 3-14 emulator support, 4-3 clksel1 signal, 3-7 clksel2 signal, 3-7 clock clkout signal description, 3-14 control, 3-32 overview, 1-11 source, uart, 13-14 uart, 13-15 usb, 18-5 cntctl register, 18-8 cntdat register, 18-8 cntdef1 register, 18-8 cntdef2 register, 18-8 cntrpk register, 18-8 cntsiz register, 18-8 co, definition, glossary-2 codec definition, glossary-2 timing parameters, 16-14 collision detection gci d-channel, 17-17 gci monitor channel, 17-14 command, usb handled by hardware, 18-27 handled by software, 18-26 handling, 18-26 protocol, 18-28 configuration of maskable interrupts, 7-7 register, 3-4 summary, 2-4 connect, usb, 18-3 control endpoint definition, 18-30, 18-31, glossary-2 interrupts, 18-29 programming, 18-11 controller-specific information, xxiii conventions, documentation, xxii converted gci signals, 17-14 cpu addressing mode example, 2-10 addressing modes, 2-9 cpu pll modes, 3-7 data types, 2-8, 2-9 definition, glossary-2 i/o space, 2-6 instruction set, 2-7 memory and i/o space, 2-7 memory operands, 2-9 memory organization and address generation, 2-5 overview, 1-6 processor registers, 2-1 register and immediate operands, 2-9 register set, 2-1, 2-2 segment register, 2-7, 2-8 states, following power-on reset, 3-6 crc, definition, glossary-2 crcvpk register, 18-9 create buffer descriptor ring, 8-31, 8-33 ctr, definition, glossary-2 cts hdlc end of transmit control, 15-14 inactive at end of frame, 15-14 start of transmit control, 15-14 protocol overview, 12-7 uart flow control, 13-13 cts/rtr, definition, glossary-2 cts_hu signal, 3-23 cts_u signal, 3-22 d data buffers, adding, 8-32, 8-34 dma transfers, 8-11 gci, receiving, 17-7 handling usb data, 18-18 programmable i/o, 9-6 replacing used data buffers, 8-35 transparency, definition, glossary-2 index index-4 am186?cc/ch/cu microcontrollers users manual types, 2-8, 2-9 uart data overflow, 13-8 description, 13-8 receiving, 13-7, 13-10 usb control endpoint, 18-29 interrupt endpoint, 18-30 transmission types, 18-16 data bus configuring chip select, 5-9 overview, 3-30 data endpoint defining, 18-32 definition, glossary-2 dce (data communications equipment) definition, glossary-2 signal descriptions, 3-23 dce_cts_a signal, 3-24 dce_cts_b signal, 3-24 dce_cts_c signal, 3-24 dce_cts_d signal, 3-25 dce_rclk_a signal, 3-23 dce_rclk_b signal, 3-24 dce_rclk_c signal, 3-24 dce_rclk_d signal, 3-25 dce_rtr_a signal, 3-24 dce_rtr_b signal, 3-24 dce_rtr_c signal, 3-25 dce_rtr_d signal, 3-25 dce_rxd_a signal, 3-23 dce_rxd_b signal, 3-24 dce_rxd_c signal, 3-24 dce_rxd_d signal, 3-25 dce_tclk_a signal, 3-23 dce_tclk_b signal, 3-24 dce_tclk_c signal, 3-24 dce_tclk_d signal, 3-25 dce_txd_a signal, 3-23 dce_txd_b signal, 3-24 dce_txd_c signal, 3-24 dce_txd_d signal, 3-25 d-channel, gci, 17-17 deactivation, gci, 17-10 debug support signals, 3-17 decrementing dma address, 8-15 default address, definition, glossary-2 den signal, 3-11 depbufs register, 18-9 depctl register, 18-9 depdat register, 18-9 depdef1 register, 18-9 depdef2 register, 18-9 depdef3 register, 18-9 depsiz register, 18-9 descriptor format, 8-38 descriptor ring creating, 8-31, 8-33 definition, glossary-2 transmit, 8-30, 8-31 destination address, 8-13 synchronization, 8-10 destination-synchronized transfer definition, glossary-2 description, 8-18 detectable baud ranges, 13-17 device address, definition, glossary-2 device, definition, glossary-2 differences, controller, xxiii disconnect, usb, 18-3 divide error exception interrupt, 7-19 dma see also smartdma channel. acknowledge, 8-10 adding data buffers, 8-32, 8-34 availability, 18-19 block diagram, 8-3 byte or word transfers, 8-15 channel use, 8-8, 8-9 circular buffers, 8-23 comparison to other devices, 8-43 create descriptor ring, 8-31, 8-33 deasserting drq, 8-19 decrementing address, 8-15 definition, glossary-2 destination synchronization, 8-10, 8-18 enabling peripheral device, 8-35 receive channel, 8-33, 8-35 transmit channel, 8-31, 8-33 fifo interaction, 18-20 general-purpose channels, 8-11 cycle, 8-12 data transfers, 8-11 interrupts, 8-13 operations, 8-14 request source, 8-17 source and destination addresses, 8-13 synchronization, 8-17 terminal count, 8-14 usage, 8-12 generating interrupts, 8-15 hardware flow control, 8-24 incrementing address, 8-15 index am186?cc/ch/cu microcontrollers users manual index-5 initialization, 8-44 interface to uart, 13-21 latency, definition, glossary-2 maximum transfer rates, 8-19 mode, definition, glossary-2 mode, uart, 13-12 multiplexed signals, 8-4 operation, 8-7 overview, 1-10 priority, 8-9 receive descriptor ring, 8-31 receive errors, 8-25 receive multitasking, 8-25 receive xon/xoff flow control, 8-24 registers, 8-4 replacing used data buffers, 8-35 request signals, 3-11 request sources, 8-15, 8-16 request synchronization, 8-10 serial communication overview, 12-7 setting synchronization, 8-17 setting up for usb, 18-21 small or misaligned circular buffer, 8-25 software considerations, 8-43 source synchronization, 8-10, 8-17 system design, 8-4 trade-offs, 18-6 transfer, definition, glossary-2 transmit descriptor ring, 8-30 uart example, 8-21 uart fifo, 13-12 unsynchronized transfers, 8-17 usb endpoints, 18-20 using buffer queues, 8-20 using circular buffers, 8-20 using with usb, 18-19 with interrupts, 8-10 with timer 2, 8-16 with uart, 8-16 with usb, 8-17, 8-43 dmahlt register, 7-5 documentation conventions, xxii downstream gci monitor channel data reception, 17-15 versus upstream, 17-11, 17-12 dram address multiplexing, 6-4 block diagram, 6-2 chip select, 5-7 chip selects and dram configuration, 3-10 comparison to other devices, 6-7 definition, glossary-3 hardware considerations, 6-6 initialization, 6-7 interface, 6-4 multiplexed signals, 6-2 operation, 6-3 overlapping pcs, 6-5 overview, 1-11, 3-32 refresh, 6-5 refresh interval, 6-6 refreshing, 6-1 register summary, 6-3 signal descriptions, 3-19 signal functions, 5-7 software considerations, 6-6 speeds and wait states, 6-4 supported devices, 6-3 system design, 6-2 usage, 6-3 drcvpk register, 18-9 drq1Cdrq0 signals deassertion, 8-19 description, 3-11 ds signal, 3-12 dsl, definition, glossary-3 dt/r signal, 3-12 dte, definition, glossary-3 duplex, definition, glossary-3 dynamic random access memory. see dram. e edo, definition, glossary-3 edram register, 6-3 emulator support a19Ca0 signals, 4-2 ad15Cad0 signals, 4-2 aden , 4-2 ale signal, 4-3 ardy signal, 4-3 bhe signal, 4-2, 4-3 bsize8 signal, 4-3 cas1 Ccas0 signals, 4-3 clkout signal, 4-3 comparison to other devices, 4-5 connection, 4-1 hardware considerations, 4-5 initialization, 4-5 lcs signal, 4-3 mcs3 Cmcs0 signals, 4-4 multiplexed signals, 4-1 once signal, 4-4 operation, 4-2 overview, 1-12 qs1Cqs0 signals, 4-4 ras1 Cras0 signals, 4-3, 4-4 rd signal, 4-4 related signals, 4-2 res signal, 4-4 resout signal, 4-4 s2 Cs0 signals, 4-5 index index-6 am186?cc/ch/cu microcontrollers users manual s6 signal, 4-5 signals used by emulators, 3-17 srdy signal, 4-3, 4-5 system design, 4-1 ucs signal, 4-5 ucsx8 signal , 4-5 usage, 4-2 whb signal, 4-5 wlb signal, 4-5 wr signal, 4-5 end of hdlc transmit, cts control, 15-14 end-of-interrupt (eoi), 7-10 endpoint address, definition, glossary-3 control endpoint, defining, 18-30, 18-31 control endpoint, interrupts, 18-29 defining, 18-30 definition, glossary-3 number, definition, glossary-3 eoi register, 7-5 eom, definition, glossary-3 error recovery dma receive, 8-25 usb endpoints, 18-22, 18-23 esc opcode exception interrupt, 7-20 ethernet-to-isdn application, 1-14 even parity, definition, glossary-3 example automatic baud rate detection, 13-18 dma register settings, 8-22 dma with uart, 8-21 memory addressing mode, 2-10 uart break character, 13-20 extended reads and writes, 13-10 external interface. see tsa. external reset, definition, glossary-3 external transceiver, usb, 18-5 f fcs, definition, glossary-3 features am186cc microcontroller, 1-1 am186ch hdlc microcontroller, 1-2 am186cu usb microcontroller, 1-3 comparison, 1-4 overview, 1-1 system, 3-32 fifo definition, glossary-3 dma, 18-20 high-water mark, definition, glossary-3 serial communications overview, 12-7 uart, 13-11 uart receive, 13-12 flags register, 2-2, 2-3 flow control dma, 8-24 overview, 12-6 uart, 13-13 fly-by-transfer, definition, glossary-3 four-pin interface, gci, 17-13 fpmcnt register, 18-7 frame definition, glossary-3 hldc, 15-1 uart, 13-8 frame synchronization (frame sync) definition, glossary-3 tsa, 16-13 framing error, definition, glossary-3 full duplex definition, glossary-3 description, 12-8 g gci activation, 17-10 applications, 17-8 basic-rate gci with isdn, 16-10 block diagram, 17-1 bus deactivation and activation, 17-9, 17-10 description, 17-9 reversal, 17-11, 17-12, 17-13 c/i channel, 17-15 c/i0 arbitration, 17-18 channels, 17-14 codec timing parameters, 16-14 comparison to other devices, 17-20 d-channel, 17-17 deactivation, 17-10 definition, glossary-4 downstream monitor channel data reception, 17-15 downstream tic format, 17-16 downstream versus upstream, 17-11, 17-12 four-pin interface, 17-13 frame sync and clock conversion, 16-12 frequencies, 17-14 gci-to-pcm conversion, 17-14 hdlc channel steering, 17-14 ic channel operation, 17-19 index am186?cc/ch/cu microcontrollers users manual index-7 initialization, 17-20 interface signals, 17-13 interrupts, 17-19 monitor channel, 17-14 operation, 17-5 overview, 1-8 pcm highway conversion with isdn, 12-5 receiving data, 17-7 registers, 17-5 signal conversion, 17-14 signal descriptions, 3-27 signals, 17-13 software considerations, 17-20 structure, 17-8 tic bus, 17-16 transmitting data, 17-6 upstream monitor channel transmission, 17-15 upstream tic format, 17-16 usage, 17-5 with tsa, 16-14 gci_dcl_a signal, 3-27 gci_dd_a signal, 3-27 gci_du_a signal, 3-27 gci_fsc_a signal, 3-27 gcird0 register, 17-5 gcird0p register, 17-5 gcird1 register, 17-5 gcird1p register, 17-5 gcitd0 register, 17-5 gcitd1 register, 17-5 gdxcon0 register, 8-4, 8-5 gdxcon1 register, 8-4, 8-5 gdxdsth register, 8-5 gdxdstl register, 8-4, 8-5 gdxsrch register, 8-4, 8-5 gdxsrcl register, 8-4, 8-5 gdxtc register, 8-5 general circuit interface. see gci. general-purpose dma see also dma, general-purpose. definition, glossary-4 gicrd register, 17-5 gicrdp register, 17-5 gictd register, 17-5 gimsk register, 17-5 gistat register, 17-5 gmrd register, 17-5 gmrdp register, 17-5 gmtd register, 17-5 gpcon register, 17-5 ground pins, 3-16 gtic register, 17-5 h half duplex definition, glossary-4 description, 12-8 handling usb data, 18-18 hardware considerations chip select, 5-10 dram, 6-6 emulator support, 4-5 hdlc, 15-20 programmable i/o (pio), 9-7 system, 3-34 uart, 13-22 watchdog timer, 11-4 hardware flow control dma, 8-24 overview, 12-6 uart, 13-13 hardware interrupt, definition, glossary-4 hdlc block diagram, 15-2 comparison to other devices, 15-21 control application, 12-4 cts control, 15-14 definition, glossary-4 frame, 15-1 general options, 15-9 hardware considerations, 15-20 initialization, 15-21 interface, 15-7 interrupts, 15-20 operation, 15-7 overview, 1-7 programmed i/o, 15-8 receive interrupt, 15-20 receiver, 15-14, 15-19 receiver block diagram, 15-15 register summary, 15-6 rtr timing, 15-18 signal descriptions, 3-23 software considerations, 15-21 transmit interrupt, 15-20 transmitter, 15-10, 15-18 transmitter block diagram, 15-10 usage, 15-7 with smartdma channel, 15-18 high-speed uart. see uart. hlda signal, 3-12 hold latency, definition, glossary-4 hold signal, 3-13 host, definition, glossary-4 hspab0 register, 13-4 hspab1 register, 13-4 hspab2 register, 13-4 index index-8 am186?cc/ch/cu microcontrollers users manual hspab3 register, 13-4 hspbdv register, 13-4 hspcon0 register, 13-4 hspcon1 register, 13-4 hspimsk register, 13-4 hspm0 register, 13-4 hspm1 register, 13-4 hspm2 register, 13-4 hsprxd register, 13-4 hsprxdp register, 13-4 hspstat register, 13-4 hsptxd register, 13-4 hxa0 register, 15-7 hxa0msk register, 15-7 hxa1 register, 15-7 hxa1msk register, 15-7 hxa2 register, 15-7 hxa2msk register, 15-7 hxa3 register, 15-7 hxa3msk register, 15-7 hxcon register, 15-6 hximsk0 register, 15-6 hximsk1 register, 15-6 hxistat0 register, 15-6 hxistat1 register, 15-6 hxmacnt register, 15-6 hxmacntp register, 15-7 hxrcon0 register, 15-6 hxrcon1 register, 15-6 hxrd register, 15-6 hxrdp register, 15-6 hxrfs1 register, 15-6 hxrfs2 register, 15-6 hxrfs3 register, 15-6 hxsfcnt register, 15-6 hxsfcntp register, 15-6 hxstate register, 15-6 hxtcon0 register, 15-6 hxtcon1 register, 15-6 hxtd register, 15-6 i i/o space and memory, 2-7 chip select, 5-5 description, 2-6 pcs, 5-9 ic channel, gci, 17-19 ice, definition, glossary-4 iepctl register, 18-8 iepdat register, 18-8 iepdef1 register, 18-8 iepdef2 register, 18-8 imask register, 7-5 immediate operands, cpu, 2-9 in-circuit emulator (ice) support, 1-12 incrementing dma address, 8-15 initialization chip select, 5-11 dma, 8-44 dram, 6-7 emulator support, 4-5 gci, 17-20 hdlc, 15-21 interrupt, 7-20 programmable i/o (pio), 9-7 synchronous serial interface (ssi), 14-9 system, 3-5, 3-34 tsa, 16-14 uart, 13-23 uart receiver, 13-6 uart transmitter, 13-5 usb, 18-33 watchdog timer, 11-5 inserv register, 7-5 instruction set, cpu, 2-7 int0 detected overflow exception interrupt, 7-19 int8Cint0 signals, 3-19 interface, hdlc, 15-7 internal peripherals definition, glossary-4 state following power-on reset, 3-6 internal reset, definition, glossary-4 internal transceiver, usb, 18-4 interrupt acknowledge, 7-10 array bounds exception, 7-20 block diagram, 7-2 breakpoint, 7-19 channel map, 7-16 channel sources, 7-17 channel, definition, glossary-4 comparison to other devices, 7-20 conditions, 7-9 definition, glossary-4 divide error exception, 7-19 dma, 8-13, 8-15 end-of-interrupt (eoi), 7-10 endpoint, definition, glossary-4 esc opcode exception, 7-20 gci interrupts, 17-19 hdlc interrupts, 15-20 initialization, 7-20 index am186?cc/ch/cu microcontrollers users manual index-9 int0 detected overflow exception, 7-19 int0 overflow detected, 7-19 iret instruction, 7-10 latency, definition, glossary-4 maskable block diagram, 7-15 configuring, 7-7 cycle, 7-13 overview, 7-14 priority, 7-11 processing, 7-13 mode, definition, glossary-4 multiplexed signals, 7-4 nmi considerations, 7-14 nonmaskable considerations, 7-14 description, 7-18, 7-19 nonmaskable (nmi), 7-11, 7-18, 7-19 operation, 7-6 overview, 1-9 partial block diagram, 7-15 polled mode, 7-14 priority, 7-11 register summary, 7-5 registers, 7-4, 7-18 requesting, 7-9 return, 7-10 sequence, 7-9 serial communication overview, 12-7 servicing, 7-10 signal descriptions, 3-19 smartdma channel, 8-42 software considerations, 7-20 software interrupt, 7-14, 7-19 source, definition, glossary-4 system design, 7-3 terminology, 7-8 trace, 7-19 transfer, definition, glossary-5 trap considerations, 7-14 type, definition, glossary-5 types, 7-12 uart fifo, 13-12 uart sources, 13-19 unused opcode exception, 7-20 usage, 7-6 usb interrupt endpoint, 18-30, 18-31 usb interrupts, 18-19 vector address, definition, glossary-5 vector table, definition, glossary-5 vector translation, 7-9 with dma, 8-10 with uart, 13-12 interrupt endpoint programming, 18-11 intpol register, 7-6 intsts register, 7-5 iom-2 see also gci. definition, glossary-5 iret instruction, 7-10 isctl register, 18-7 isdn application basic-rate gci, 16-10 gci-pcm highway conversion, 12-5 isdn-to-ethernet, 1-14 low-end router, 1-14 serial communications overview, 12-5 terminal adapter overview, 1-14 isdn, definition, glossary-5 isochronous transfer definition, glossary-5 features, 18-24 synchronization, 18-6, 18-23 isochronous transmission, definition, glossary-5 isr, definition, glossary-5 l lance, definition, glossary-5 lap-b, definition, glossary-5 lap-d, definition, glossary-5 latency, definition, glossary-5 lcs signal chip select, 5-5, 5-9 description, 3-17 emulator support, 4-3 linecard application, 1-15, 12-4 lmcs register, 5-3 low-end router application, 1-14 lsb, definition, glossary-5 m maskable interrupt see also interrupt, maskable. definition, glossary-5 mastering, bus, 3-31 maximum dma transfer rates, 8-19 mcs3 Cmcs0 signals chip select, 5-5 description, 3-17 emulator support, 4-4 memory addressing mode example, 2-10 and i/o space, 2-7 chip select, 5-5 interface overview, 1-11 lower chip select, 5-5, 5-9 midrange chip select, 5-5 index index-10 am186?cc/ch/cu microcontrollers users manual operands, 2-9 organization and address generation, 2-5 refresh cycle, 6-1 upper chip select, 4-5, 5-5 message pipe, definition, glossary-5 misaligned circular buffer, 8-25 mmcs register, 5-3 monitor channel, gci, 17-14, 17-15 mpcs register, 5-3 msb, definition, glossary-5 multidrop, definition, glossary-5 multiplexed mode, definition, glossary-5 multiplexed signal chip select, 5-3 definition, glossary-5 dma, 8-4 dram, 6-2 emulator support, 4-1 interrupt, 7-4 list, 9-3 serial communication, 12-2 synchronous serial interface, 14-2 system, 3-1, 12-2 tsa muxing logic, 16-8 uart, 13-3 usb, 18-3 watchdog timer, 11-2 multipoint, definition, glossary-5 multitasking, dma receive, 8-25 mux, definition, glossary-5 n nack, definition, glossary-6 nibble, definition, glossary-6 nmi see also interrupt, nonmaskable. definition, glossary-6 signal, 3-20 nonmaskable interrupt. see interrupt. nonmultiplexed mode, definition, glossary-6 non-ucs and non-lcs bus width, 5-9 nrz, definition, glossary-6 nrzi, definition, glossary-6 o odd parity, definition, glossary-6 once signal description, 3-7 emulator support, 4-4 once, definition, glossary-6 open-drain output, pio, 9-6 operands, register and immediate, 2-9 operation chip select, 5-4 dma, 8-7 dram, 6-3 emulator support, 4-2 gci, 17-5 hdlc, 15-7 interrupt, 7-6 programmable i/o (pio), 9-5 synchronous serial interface (ssi), 14-4 system, 3-30 tsa, 16-7 uart, 13-4 usb, 18-10 watchdog timer, 11-3 osi, definition, glossary-6 output enable, 3-31 overall priority, definition, glossary-6 overflow exception interrupt, 7-19 overlapping chip selects, 5-8 pcs with dram, 6-5 p pabx, definition, glossary-6 packet buffer, definition, glossary-6 packet id, definition, glossary-6 packet, definition, glossary-6 pacs register, 5-3 parity, definition, glossary-6 pcb, definition, glossary-6 pcm highway conversion application, 12-5 definition, glossary-6 description, 16-11 signal descriptions, 3-25 pcm, definition, glossary-6 pcm_clk_a signal, 3-25 pcm_clk_b signal, 3-26 pcm_clk_c signal, 3-26 pcm_clk_d signal, 3-26 pcm_fsc_a signal, 3-25 pcm_fsc_b signal, 3-26 pcm_fsc_c signal, 3-26 pcm_fsc_d signal, 3-27 pcm_rxd_a signal, 3-25 pcm_rxd_b signal, 3-26 pcm_rxd_c signal, 3-26 pcm_rxd_d signal, 3-26 pcm_tsc_a signal, 3-25 index am186?cc/ch/cu microcontrollers users manual index-11 pcm_tsc_b signal, 3-26 pcm_tsc_c signal, 3-26 pcm_tsc_d signal, 3-27 pcm_txd_a signal, 3-25 pcm_txd_b signal, 3-26 pcm_txd_c signal, 3-26 pcm_txd_d signal, 3-26 pcs i/o space, 5-9 pcs7 Cpcs0 signals, description, 3-18, 5-6 peripheral interface, overview, 1-11 on-chip, overview, 1-9 pcs chip select, 5-9 registers, 2-4, 2-5 physical address generation, 2-6 pin definition, glossary-7 reserved, 3-16 pinstrap definition, glossary-7 pinstraps table, 3-7 pio multiplexed signals, 9-3 pio, definition, glossary-7 pio47Cpio0 signals, 3-21 pioclr0 register, 9-5 pioclr1 register, 9-5 pioclr2 register, 9-5 piodata0 register, 9-5 piodata1 register, 9-5 piodata2 register, 9-5 piodir0 register, 9-5 piodir1 register, 9-5 piodir2 register, 9-5 piomode0 register, 9-5 piomode1 register, 9-5 piomode2 register, 9-5 piopol register, 7-6 pioset0 register, 9-5 pioset1 register, 9-5 pioset2 register, 9-5 pipe, definition, glossary-7 pll (phase-locked loop) mode, usb, 18-6 modes, 3-7 pll bypass (cpu), 3-7 poll register, 7-5 polled mode definition, glossary-7 serial communication overview, 12-7 uart, 13-12 usb, 18-18 pollst register, 7-5 port, definition, glossary-7 pots definition, glossary-7 linecard application, 12-4 power ground pins, 3-16 power pins, 3-16 power-on reset, definition, glossary-7 ppp, definition, glossary-7 pri, definition, glossary-7 primsk register, 7-5 priority dma, 8-9 interrupt, 7-11 prl register, 3-4 processor registers, 2-1 processor status flags register, 2-2, 2-3 programmable bus sizing, 3-30 programmable i/o (pio) as interrupt source, 7-18 block diagram, 9-1 comparison to other devices, 9-7 defining input or output, 9-5 driving data, 9-6 hardware considerations, 9-7 initialization, 9-7 mode and direction, 9-6 operation, 9-5 overview, 1-10 register summary, 9-5 registers, 9-5 set and clear registers, 9-6 setting and clearing data, 9-6 signal descriptions, 3-21 software considerations, 9-7 system design, 9-2 usage, 9-5 using as open-drain output, 9-6 programmable priority, definition, glossary-7 programmed i/o, hdlc, 15-8 protocol, usb, 18-17 pwd signal, 3-21 pwd, definition, glossary-7 q qs1Cqs0 signals description, 3-17 emulator support, 4-4 index index-12 am186?cc/ch/cu microcontrollers users manual r ras1 Cras0 signals description, 3-19 emulator support, 4-3, 4-4 raw dce definition, glossary-7 description, 16-11 rd signal description, 3-13 emulator support, 4-4 ready signal, chip select, 5-10 receive dma circular buffers, 8-23 descriptor ring, 8-31 errors, 8-25 hardware flow control, 8-24 multitasking, 8-25 xon/xoff flow control, 8-24 gci, data, 17-7 hdlc interrupt, 15-20 programmed i/o, hdlc, 15-8 uart address bit, 13-10 bit sampling, 13-16 data, 13-7 description, 13-6 fifo, 13-12 special character matching, 13-21 status and data, 13-10 receiver definition, glossary-7 hdlc, 15-14, 15-19 refresh, 6-1 refresh, dram, 6-5, 6-6 register operands, cpu, 2-9 registers chip select, 5-3 configuration, 2-4 cpu, 2-1, 2-2 dma, 8-4 gci, 17-5 interrupt, 7-4, 7-18 processor, 2-1 programmable i/o (pio), 9-5 synchronous serial interface (ssi), 14-3 tsa, 16-7 uart, 13-3 usb, 18-7 watchdog timer, 11-3 remote wakeup, usb, 18-16 reqst register, 7-5 request, dma, 8-17 res signal description, 3-15 emulator support, 4-4 rescon register, 3-4 reserved pins, 3-16 reset definition, glossary-7 definition of types, 3-9 system, 3-5 usb, 18-17 reset configuration pins see pinstraps, 3-7 resout signal description, 3-15 emulator support, 4-4 resume, usb, 18-16 reversal, gci bus, 17-12 ring adding buffers, 8-32, 8-34 buffer, definition, glossary-7 create, 8-31, 8-33 router, definition, glossary-7 rsvd_x pins, 3-16 rtfmcnt register, 18-7 rtr definition, glossary-7 protocol overview, 12-7 timing, 15-18 uart flow control, 13-13 rtr_hu signal behavior, 13-14 description, 3-23 rtr_u signal behavior, 13-14 description, 3-22 rts, definition, glossary-7 rxd_hu signal, 3-22 rxd_u signal, 3-22 s s2 Cs0 signals description, 3-13 emulator support, 4-5 s6 signal description, 3-13 emulator support, 4-5 sample applications, 12-3 scit, definition, glossary-7 sclk signal, 3-23 sdata signal, 3-23 sden signal, 3-23 sdlc, definition, glossary-7 index am186?cc/ch/cu microcontrollers users manual index-13 sdxcbd register, 8-6, 8-7 sdxcon register, 8-6, 8-7 sdxcrad register, 8-6, 8-7 sdxctad register, 8-6, 8-7 sdxrrah register, 8-6, 8-7 sdxrrcal register, 8-6, 8-7 sdxstat register, 8-6, 8-7 sdxtrah register, 8-6, 8-7 sdxtrcal register, 8-6, 8-7 segment register, cpu, 2-7, 2-8 selecting dram, 5-7 serial communication cts/rtr protocol, 12-7 hardware flow control, 12-6 hdlc control application, 12-4 introduction, 12-6 isdn application, 12-5 multiplexed signals, 12-2 overview, 12-7 polled, interrupt, and dma mode, 12-7 support overview, 1-6 setting pio data, 9-6 shmask register, 7-6 short frame, definition, glossary-8 short packet, usb, 18-21 shreq register, 7-6 signal descriptions, 3-8, 3-10 signal multiplexing, 9-3 signal, definition, glossary-8 simplex definition, glossary-8 description, 12-8 slac, definition, glossary-8 slic, definition, glossary-8 small circular buffer, 8-25 smartdma channel see also dma. cycle, 8-35 definition, glossary-8 descriptor format, 8-38 descriptor polling, 8-41 descriptor ring, 8-29 interface, 15-8 interrupts, 8-42 introduction, 8-26 memory management, 8-30 memory overview, 8-28 overview, 1-8 receive cycle, 8-37 receive descriptor format, 8-40 receive flow diagram, 8-38 request source and synchronization, 8-27, 8-28 transmit cycle, 8-35 transmit descriptor format, 8-39 transmit flow diagram, 8-37 usage, 8-31 using without cpu intervention, 8-42 with hdlc, 15-18 software considerations chip select, 5-10 dma, 8-43 dram, 6-6 gci, 17-20 hdlc, 15-21 interrupt, 7-20 programmable i/o (pio), 9-7 synchronous serial interface (ssi), 14-8 tsa, 16-14 uart, 13-22 usb, 18-33 watchdog timer, 11-5 software exception, definition, glossary-8 software interrupt considerations, 7-14 definition, glossary-8 nonmaskable, 7-19 see interrupt. soho, definition, glossary-8 source address, dma, 8-13 source synchronization, 8-10, 8-17 source-synchronized transfer, definition, glossary-8 spbdv register, 13-4 spcon0 register, 13-4 spcon1 register, 13-4 special-character matching, uart, 13-21 spimsk register, 13-4 sprxd register, 13-4 sprxdp register, 13-4 spstat register, 13-4 sptxd register, 13-4 sram definition, glossary-8 example system, 3-29 srdy signal description, 3-14 emulator support, 4-3, 4-5 sscon register, 14-3 ssi see also synchronous serial interface. definition, glossary-8 ssrxd register, 14-3 ssstat register, 14-3 sstxd0 register, 14-3 sstxd1 register, 14-3 start of hdlc transmit, cts control, 15-14 index index-14 am186?cc/ch/cu microcontrollers users manual status, uart receive, 13-10 stream pipe, definition, glossary-8 suspend, usb, 18-16 synchronization dma, 8-17 isochronous, 18-6, 18-23 synchronization type, definition, glossary-8 synchronized transfer, definition, glossary-8 synchronous communication overview, 12-6 synchronous serial interface (ssi) application example, 14-3 block diagram, 14-1 comparison to other devices, 14-8 initialization, 14-9 master/slave configuration, 14-4 multiple transmit with pio, 14-7 multiple transmit with sden, 14-7 multiplexed signals, 14-2 operation, 14-4 overview, 1-9 register summary, 14-3 registers, 14-3 signal descriptions, 3-23 signal interface, 14-4 single transmit, multiple receive with sden, 14-8 software considerations, 14-8 system design, 14-2 usage, 14-4 synchronous transmission, definition, glossary-8 syscon register, 3-4 system byte write enables, 3-31 clock control, 3-32 clock overview, 1-11 clocks, 3-33 comparison to other devices, 3-34 configuration register, 3-4 hardware considerations, 3-34 initialization, 3-5, 3-34 interface overview, 1-11 multiplexed signals, 3-1, 12-2 operation, 3-30 output enable, 3-31 reset, 3-5, glossary-8 signal descriptions, 3-8 sram example, 3-29 system design, 3-1 typical block diagram, 3-29 system bus address bus overview, 3-30 data bus overview, 3-30 interface, 3-28 mastering, 3-31 programmable bus sizing, 3-30 width, 3-31, 5-9 system reset, definition, glossary-8 t tdm, definition, glossary-8 terminal adapter, isdn, overview, 1-14 terminal count, dma, 8-14 terminology, interrupt, 7-8 tic bus bits, 17-16 downstream format, 17-16 support, 17-16 upstream format, 17-16 tic, definition, glossary-8 time slots, tsa, 16-8 timer overview, 1-10 signal descriptions, 3-21 with dma, 8-16 timing parameters, tsa, 16-14 tmrin1Ctmrin0 signals, 3-22 tmrout1Ctmrout0 signals, 3-22 top of fifo, definition, glossary-8 trace interrupt, 7-19 trade-offs dma, 18-6 usb, 18-2 transaction, definition, glossary-9 transceiver definition, glossary-9 usb, 18-3 transfer type, definition, glossary-9 transfer, definition, glossary-9 transmitter definition, glossary-9 hdlc, 15-10, 15-18 transparency, definition, glossary-9 transparent mode, definition, glossary-9 trap considerations, 7-14 tsa block diagram, 16-3 comparison to other devices, 16-14 definition, glossary-9 external interfaces, 16-11 frame sync, 16-13 gci clock and frame sync conversion, 16-13 gci conversion, 16-12 gci timing parameters, 16-14 initialization, 16-14 muxing logic, 16-8 operation, 16-7 overview, 1-7 pcm highway, 16-11 raw dce, 16-11 register summary, 16-7 registers, 16-7 index am186?cc/ch/cu microcontrollers users manual index-15 simplified block diagram, 16-3 software considerations, 16-14 time slots, 16-8 usage, 16-7 with gci, 16-14 tstmp register, 18-7 tstmpm register, 18-7 tsxcon register, 16-7 tsxstart register, 16-7 tsxstop register, 16-7 txd_hu signal, 3-22 txd_u signal, 3-22 u uart address bits, 13-9, 13-10 automatic baud rate detection, 13-7, 13-16, 13-18 baud rate, 13-14, 13-15 block diagram, 13-2 break detection and generation, 13-20 clock, 13-14, 13-15 comparison to other devices, 13-23 cts flow control, 13-13 data, 13-8 data overflow, 13-8 definition, glossary-9 detectable baud ranges, 13-17 dma example, 8-21 extended reads and writes, 13-10 fifo, 13-11 frame, 13-8 hardware considerations, 13-22 high-speed uart signal descriptions, 3-22 initialization, 13-23 interface to dma, 13-21 interrupt sources, 13-19 multiplexed signals, 13-3 operation, 13-4 overview, 1-9 receive fifo, 13-12 receive status and data, 13-10 receiver bit sampling, 13-16 receiving data, 13-6, 13-7 registers, 13-3 registers , 13-4 rtr flow control, 13-13 rtr_hu signal, 13-14 rtr_u signal, 13-14 setting the baud rate, 13-6 signal descriptions, 3-22 software considerations, 13-22 special-character matching, 13-21 system design, 13-3 timing, 13-8 transmit fifo, 13-11 transmitting address bit, 13-9 transmitting data, 13-5 usage, 13-4 using fifo, 13-12 with dma, 8-16 worst case autobaud error, 13-17 uclk signal, 3-15 ucs signal chip select, 5-5, 5-9 description, 3-18 emulator support, 4-5 ucsx8 signal description, 3-7 emulator support, 4-5 udmns signal, 3-27 udpls signal, 3-27 uimask1 register, 18-7 uimask2 register, 18-7 uistat1 register, 18-7 uistat2 register, 18-7 umcs register, 5-3 unsynchronized transfer definition, glossary-9 description, 8-17 unused opcode exception interrupt, 7-20 upstream gci versus downstream, 17-11, 17-12 upstream monitor channel transmission, 17-15 usage chip select, 5-4 dram, 6-3 emulator support, 4-2 gci, 17-5 hdlc, 15-7 interrupt, 7-6 programmable i/o (pio), 9-5 synchronous serial interface (ssi), 14-4 tsa, 16-7 uart, 13-4 usb, 18-10 watchdog timer, 11-3 usb block diagram, 18-2 clock source, 18-5 command handled by hardware, 18-27, 18-28 handled by software, 18-26, 18-27 handling, 18-26 processing, 18-30 protocol, 18-28 connect and disconnect, 18-3 control endpoint definition, 18-30, 18-31 interrupts, 18-29 programming, 18-11 data endpoint definition, 18-32 index index-16 am186?cc/ch/cu microcontrollers users manual data transfer via control endpoint, 18-29 data transfer via interrupt endpoint, 18-30 data transmission types, 18-16 definition, glossary-9 device, definition, glossary-9 endpoint definitions, 18-30 endpoint programming, 18-12 endpoint, definition, glossary-9 endpoints used with dma, 18-20 error recovery bulk endpoints, 18-22 interrupt endpoints, 18-22 isochronous endpoints, 18-23 example bulk in, non-dma, 18-14 bulk out, general-purpose dma, 18-15 bulk out, non-dma, 18-14 external transceiver, 18-5 external transceiver signals, 3-27 general programming issues, 18-10 handling data, 18-18 initialization, 18-33 internal transceiver, 18-4 interrupt endpoint commands, 18-30 definition, 18-31 description, 18-29 interrupts, 18-30 programming, 18-11 interrupt-driven i/o, 18-19 isochronous features, 18-24 isochronous synchronization, 18-6, 18-23 multiplexed signals, 18-3 operation, 18-10 overview, 1-6 pll mode, 18-6 pll modes, 3-7 polled i/o, 18-18 protocol handling, 18-17 registers, 18-7 remote wakeup, 18-16 reset, 18-17 resume, 18-16 setting up dma, 18-21 short packet, 18-21 signal descriptions, 3-27 signal trade-offs, 18-2 software considerations, 18-33 suspend, 18-16 system design, 18-2 transceiver, 18-3 usage, 18-10 with dma, 8-17, 8-43, 18-19 usbdC signal, 3-27 usbd+ signal, 3-27 usbmfr register, 18-7 usbsci signal, 3-27 usbsel1 signal, 3-7 usbsel2 signal, 3-7 usbsof signal, 3-27 usbxcvr signal, 3-7 utxdmns signal, 3-27 utxdpls signal, 3-28 uxvoe signal, 3-28 uxvrcv signal, 3-28 v v cc description, 3-16 v cc _a description, 3-16 v cc _usb description, 3-16 vector, interrupt, 7-9 very short frame, definition, glossary-10 v ss description, 3-16 v ss _a description, 3-16 v ss _usb description, 3-16 w wait state chip select, 5-10 definition, glossary-10 wakeup, usb, 18-16 wan, definition, glossary-10 watchdog timer block diagram, 11-1 comparison to other devices, 11-5 hardware considerations, 11-4 initialization, 11-5 multiplexed signals, 11-2 operation, 11-3 overview, 1-11 register, 11-3, 11-3, 11-3 res and watchdog timer reset, 3-15 software considerations, 11-5 system design, 11-2 usage, 11-3 wdtcon register, 11-3, 11-3 whb signal description, 3-14 emulator support, 4-5 width, bus, 5-9 index am186?cc/ch/cu microcontrollers users manual index-17 wlb signal description, 3-14 emulator support, 4-5 word transfers, dma, 8-15 word, definition, glossary-10 worst-case error, autobaud, 13-17 wr signal description, 3-14 emulator support, 4-5 x x1 signal, 3-15 x2 signal, 3-15 xon/xoff flow control, dma receive, 8-24 z zero-bit deletion, definition, glossary-10 zero-bit insertion, definition, glossary-10 index index-18 am186?cc/ch/cu microcontrollers users manual |
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